* [PATCH][next][V2] ixgbe: fix potential u32 overflow on shift
@ 2019-06-07 18:19 Colin King
2019-06-07 20:12 ` Keller, Jacob E
2019-06-19 23:13 ` [Intel-wired-lan] " Bowers, AndrewX
0 siblings, 2 replies; 3+ messages in thread
From: Colin King @ 2019-06-07 18:19 UTC (permalink / raw)
To: Jacob Keller, Jeff Kirsher, David S . Miller, intel-wired-lan, netdev
Cc: kernel-janitors, linux-kernel
From: Colin Ian King <colin.king@canonical.com>
The u32 variable rem is being shifted using u32 arithmetic however
it is being passed to div_u64 that expects the expression to be a u64.
The 32 bit shift may potentially overflow, so cast rem to a u64 before
shifting to avoid this. Also remove comment about overflow.
Addresses-Coverity: ("Unintentional integer overflow")
Fixes: cd4583206990 ("ixgbe: implement support for SDP/PPS output on X550 hardware")
Fixes: 68d9676fc04e ("ixgbe: fix PTP SDP pin setup on X540 hardware")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
---
V2: update comment
---
drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c | 14 ++++----------
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
index 2c4d327fcc2e..0be13a90ff79 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
@@ -205,11 +205,8 @@ static void ixgbe_ptp_setup_sdp_X540(struct ixgbe_adapter *adapter)
*/
rem = (NS_PER_SEC - rem);
- /* Adjust the clock edge to align with the next full second. This
- * assumes that the cycle counter shift is small enough to avoid
- * overflowing when shifting the remainder.
- */
- clock_edge += div_u64((rem << cc->shift), cc->mult);
+ /* Adjust the clock edge to align with the next full second. */
+ clock_edge += div_u64(((u64)rem << cc->shift), cc->mult);
trgttiml = (u32)clock_edge;
trgttimh = (u32)(clock_edge >> 32);
@@ -291,11 +288,8 @@ static void ixgbe_ptp_setup_sdp_X550(struct ixgbe_adapter *adapter)
*/
rem = (NS_PER_SEC - rem);
- /* Adjust the clock edge to align with the next full second. This
- * assumes that the cycle counter shift is small enough to avoid
- * overflowing when shifting the remainder.
- */
- clock_edge += div_u64((rem << cc->shift), cc->mult);
+ /* Adjust the clock edge to align with the next full second. */
+ clock_edge += div_u64(((u64)rem << cc->shift), cc->mult);
/* X550 hardware stores the time in 32bits of 'billions of cycles' and
* 32bits of 'cycles'. There's no guarantee that cycles represents
--
2.20.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* RE: [PATCH][next][V2] ixgbe: fix potential u32 overflow on shift
2019-06-07 18:19 [PATCH][next][V2] ixgbe: fix potential u32 overflow on shift Colin King
@ 2019-06-07 20:12 ` Keller, Jacob E
2019-06-19 23:13 ` [Intel-wired-lan] " Bowers, AndrewX
1 sibling, 0 replies; 3+ messages in thread
From: Keller, Jacob E @ 2019-06-07 20:12 UTC (permalink / raw)
To: Colin King, Kirsher, Jeffrey T, David S . Miller,
intel-wired-lan, netdev
Cc: kernel-janitors, linux-kernel
> -----Original Message-----
> From: Colin King [mailto:colin.king@canonical.com]
> Sent: Friday, June 07, 2019 11:19 AM
> To: Keller, Jacob E <jacob.e.keller@intel.com>; Kirsher, Jeffrey T
> <jeffrey.t.kirsher@intel.com>; David S . Miller <davem@davemloft.net>; intel-wired-
> lan@lists.osuosl.org; netdev@vger.kernel.org
> Cc: kernel-janitors@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [PATCH][next][V2] ixgbe: fix potential u32 overflow on shift
>
> From: Colin Ian King <colin.king@canonical.com>
>
> The u32 variable rem is being shifted using u32 arithmetic however
> it is being passed to div_u64 that expects the expression to be a u64.
> The 32 bit shift may potentially overflow, so cast rem to a u64 before
> shifting to avoid this. Also remove comment about overflow.
>
> Addresses-Coverity: ("Unintentional integer overflow")
> Fixes: cd4583206990 ("ixgbe: implement support for SDP/PPS output on X550
> hardware")
> Fixes: 68d9676fc04e ("ixgbe: fix PTP SDP pin setup on X540 hardware")
> Signed-off-by: Colin Ian King <colin.king@canonical.com>
> ---
>
> V2: update comment
Thanks Colin!
Acked-by: Jacob Keller <jacob.e.keller@intel.com>
Regards,
Jake
>
> ---
> drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c | 14 ++++----------
> 1 file changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
> b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
> index 2c4d327fcc2e..0be13a90ff79 100644
> --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
> +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
> @@ -205,11 +205,8 @@ static void ixgbe_ptp_setup_sdp_X540(struct
> ixgbe_adapter *adapter)
> */
> rem = (NS_PER_SEC - rem);
>
> - /* Adjust the clock edge to align with the next full second. This
> - * assumes that the cycle counter shift is small enough to avoid
> - * overflowing when shifting the remainder.
> - */
> - clock_edge += div_u64((rem << cc->shift), cc->mult);
> + /* Adjust the clock edge to align with the next full second. */
> + clock_edge += div_u64(((u64)rem << cc->shift), cc->mult);
> trgttiml = (u32)clock_edge;
> trgttimh = (u32)(clock_edge >> 32);
>
> @@ -291,11 +288,8 @@ static void ixgbe_ptp_setup_sdp_X550(struct
> ixgbe_adapter *adapter)
> */
> rem = (NS_PER_SEC - rem);
>
> - /* Adjust the clock edge to align with the next full second. This
> - * assumes that the cycle counter shift is small enough to avoid
> - * overflowing when shifting the remainder.
> - */
> - clock_edge += div_u64((rem << cc->shift), cc->mult);
> + /* Adjust the clock edge to align with the next full second. */
> + clock_edge += div_u64(((u64)rem << cc->shift), cc->mult);
>
> /* X550 hardware stores the time in 32bits of 'billions of cycles' and
> * 32bits of 'cycles'. There's no guarantee that cycles represents
> --
> 2.20.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [Intel-wired-lan] [PATCH][next][V2] ixgbe: fix potential u32 overflow on shift
2019-06-07 18:19 [PATCH][next][V2] ixgbe: fix potential u32 overflow on shift Colin King
2019-06-07 20:12 ` Keller, Jacob E
@ 2019-06-19 23:13 ` Bowers, AndrewX
1 sibling, 0 replies; 3+ messages in thread
From: Bowers, AndrewX @ 2019-06-19 23:13 UTC (permalink / raw)
To: intel-wired-lan, netdev; +Cc: kernel-janitors, linux-kernel
> -----Original Message-----
> From: Intel-wired-lan [mailto:intel-wired-lan-bounces@osuosl.org] On
> Behalf Of Colin King
> Sent: Friday, June 7, 2019 11:19 AM
> To: Keller, Jacob E <jacob.e.keller@intel.com>; Kirsher, Jeffrey T
> <jeffrey.t.kirsher@intel.com>; David S . Miller <davem@davemloft.net>;
> intel-wired-lan@lists.osuosl.org; netdev@vger.kernel.org
> Cc: kernel-janitors@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [Intel-wired-lan] [PATCH][next][V2] ixgbe: fix potential u32
> overflow on shift
>
> From: Colin Ian King <colin.king@canonical.com>
>
> The u32 variable rem is being shifted using u32 arithmetic however it is being
> passed to div_u64 that expects the expression to be a u64.
> The 32 bit shift may potentially overflow, so cast rem to a u64 before shifting
> to avoid this. Also remove comment about overflow.
>
> Addresses-Coverity: ("Unintentional integer overflow")
> Fixes: cd4583206990 ("ixgbe: implement support for SDP/PPS output on X550
> hardware")
> Fixes: 68d9676fc04e ("ixgbe: fix PTP SDP pin setup on X540 hardware")
> Signed-off-by: Colin Ian King <colin.king@canonical.com>
> ---
>
> V2: update comment
>
> ---
> drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c | 14 ++++----------
> 1 file changed, 4 insertions(+), 10 deletions(-)
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-06-19 23:13 UTC | newest]
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2019-06-19 23:13 ` [Intel-wired-lan] " Bowers, AndrewX
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