* [PATCH net-next 1/2] net: ethernet: mediatek: Add MT7621 TRGMII mode support
2019-06-16 18:20 [PATCH net-next 0/2] net: mediatek: Add MT7621 TRGMII mode support René van Dorst
@ 2019-06-16 18:20 ` René van Dorst
2019-06-16 18:20 ` [PATCH net-next 2/2] net: dsa: mt7530: " René van Dorst
2019-06-17 14:02 ` [PATCH net-next 0/2] net: mediatek: " Andrew Lunn
2 siblings, 0 replies; 11+ messages in thread
From: René van Dorst @ 2019-06-16 18:20 UTC (permalink / raw)
To: Sean Wang, Florian Fainelli, David S . Miller, Matthias Brugger,
Andrew Lunn, Vivien Didelot
Cc: netdev, john, linux-mediatek, linux-mips, René van Dorst
MT7621 SOC also supports TRGMII.
TRGMII speed is 1200MBit.
Signed-off-by: René van Dorst <opensource@vdorst.com>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 38 ++++++++++++++++++---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 ++++++
2 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 362eacd82b92..628adbf79710 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -140,6 +140,28 @@ static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
return _mtk_mdio_read(eth, phy_addr, phy_reg);
}
+static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
+ phy_interface_t interface)
+{
+ u32 val;
+
+ /* Check DDR memory type. Currently DDR2 is not supported. */
+ regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
+ if (val & SYSCFG_DRAM_TYPE_DDR2) {
+ dev_err(eth->dev,
+ "TRGMII mode with DDR2 memory is not supported!\n");
+ return -EOPNOTSUPP;
+ }
+
+ val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
+ ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
+
+ regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
+ ETHSYS_TRGMII_MT7621_MASK, val);
+
+ return 0;
+}
+
static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
{
u32 val;
@@ -189,9 +211,17 @@ static void mtk_phy_link_adjust(struct net_device *dev)
break;
}
- if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&
- !mac->id && !mac->trgmii)
- mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed);
+ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && !mac->id) {
+ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) {
+ if (mt7621_gmac0_rgmii_adjust(mac->hw,
+ dev->phydev->interface))
+ return;
+ } else {
+ if (!mac->trgmii)
+ mtk_gmac0_rgmii_adjust(mac->hw,
+ dev->phydev->speed);
+ }
+ }
if (dev->phydev->link)
mcr |= MAC_MCR_FORCE_LINK;
@@ -2613,7 +2643,7 @@ static const struct mtk_soc_data mt2701_data = {
};
static const struct mtk_soc_data mt7621_data = {
- .caps = MTK_SHARED_INT,
+ .caps = MT7621_CAPS,
.required_clks = MT7621_CLKS_BITMAP,
.required_pctl = false,
};
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index a0aa5008d5cc..9abb4015477f 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -369,6 +369,10 @@
#define MT7622_ETH 7622
#define MT7621_ETH 7621
+/* ethernet system control register */
+#define ETHSYS_SYSCFG 0x10
+#define SYSCFG_DRAM_TYPE_DDR2 BIT(4)
+
/* ethernet subsystem config register */
#define ETHSYS_SYSCFG0 0x14
#define SYSCFG0_GE_MASK 0x3
@@ -383,6 +387,9 @@
/* ethernet subsystem clock register */
#define ETHSYS_CLKCFG0 0x2c
#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
+#define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6))
+#define ETHSYS_TRGMII_MT7621_APLL BIT(6)
+#define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5)
/* ethernet reset control register */
#define ETHSYS_RSTCTRL 0x34
@@ -622,6 +629,7 @@ enum mtk_eth_path {
#define MTK_SHARED_SGMII BIT(7)
#define MTK_HWLRO BIT(8)
#define MTK_SHARED_INT BIT(9)
+#define MTK_TRGMII_MT7621_CLK BIT(10)
/* Supported path present on SoCs */
#define MTK_PATH_BIT(x) BIT((x) + 10)
@@ -673,6 +681,9 @@ enum mtk_eth_path {
#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
+#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
+ MTK_GMAC2_RGMII | MTK_SHARED_INT | MTK_TRGMII_MT7621_CLK)
+
#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
MTK_MUX_GDM1_TO_GMAC1_ESW | \
--
2.20.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH net-next 2/2] net: dsa: mt7530: Add MT7621 TRGMII mode support
2019-06-16 18:20 [PATCH net-next 0/2] net: mediatek: Add MT7621 TRGMII mode support René van Dorst
2019-06-16 18:20 ` [PATCH net-next 1/2] net: ethernet: " René van Dorst
@ 2019-06-16 18:20 ` René van Dorst
2019-06-17 14:02 ` [PATCH net-next 0/2] net: mediatek: " Andrew Lunn
2 siblings, 0 replies; 11+ messages in thread
From: René van Dorst @ 2019-06-16 18:20 UTC (permalink / raw)
To: Sean Wang, Florian Fainelli, David S . Miller, Matthias Brugger,
Andrew Lunn, Vivien Didelot
Cc: netdev, john, linux-mediatek, linux-mips, René van Dorst
MT7621 internal MT7530 switch also supports TRGMII mode.
TRGMII speed is 1200MBit.
Signed-off-by: René van Dorst <opensource@vdorst.com>
---
drivers/net/dsa/mt7530.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index c7d352da5448..88de4e880417 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -435,11 +435,20 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
trgint = 0;
ncpo1 = 0x0c80;
ssc_delta = 0x87;
+
+ /* Port 6 delay settings RGMII central align */
+ mt7530_rmw(priv, MT7530_TRGMII_TXCTRL, BIT(30) | BIT(28), 0);
+ mt7530_write(priv, MT7530_TRGMII_TCK_CTRL, 0x0855);
break;
case PHY_INTERFACE_MODE_TRGMII:
trgint = 1;
- ncpo1 = 0x1400;
+ /* PLL frequency: MT7621 150MHz, other 162.5MHz */
+ ncpo1 = (priv->id == ID_MT7621 ? 0x0780 : 0x1400);
ssc_delta = 0x57;
+
+ /* Port 6 delay settings TRGMII central align */
+ mt7530_rmw(priv, MT7530_TRGMII_TXCTRL, 0, BIT(30));
+ mt7530_write(priv, MT7530_TRGMII_TCK_CTRL, 0x0055);
break;
default:
dev_err(priv->dev, "xMII mode %d not supported\n", mode);
@@ -507,7 +516,9 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
mt7530_rmw(priv, MT7530_TRGMII_RD(i),
RD_TAP_MASK, RD_TAP(16));
else
- mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII);
+ if (priv->id != ID_MT7621)
+ mt7623_trgmii_set(priv, GSW_INTF_MODE,
+ INTF_MODE_TRGMII);
return 0;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH net-next 0/2] net: mediatek: Add MT7621 TRGMII mode support
2019-06-16 18:20 [PATCH net-next 0/2] net: mediatek: Add MT7621 TRGMII mode support René van Dorst
2019-06-16 18:20 ` [PATCH net-next 1/2] net: ethernet: " René van Dorst
2019-06-16 18:20 ` [PATCH net-next 2/2] net: dsa: mt7530: " René van Dorst
@ 2019-06-17 14:02 ` Andrew Lunn
2019-06-17 21:33 ` René van Dorst
2 siblings, 1 reply; 11+ messages in thread
From: Andrew Lunn @ 2019-06-17 14:02 UTC (permalink / raw)
To: René van Dorst
Cc: Sean Wang, Florian Fainelli, David S . Miller, Matthias Brugger,
Vivien Didelot, netdev, john, linux-mediatek, linux-mips
On Sun, Jun 16, 2019 at 08:20:08PM +0200, René van Dorst wrote:
> Like many other mediatek SOCs, the MT7621 SOC and the internal MT7530 switch both
> supports TRGMII mode. MT7621 TRGMII speed is 1200MBit.
Hi René
Is TRGMII used only between the SoC and the Switch? Or does external
ports of the switch also support 1200Mbit/s? If external ports support
this, what does ethtool show for Speed?
Thanks
Andrew
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH net-next 0/2] net: mediatek: Add MT7621 TRGMII mode support
2019-06-17 14:02 ` [PATCH net-next 0/2] net: mediatek: " Andrew Lunn
@ 2019-06-17 21:33 ` René van Dorst
2019-06-17 21:44 ` Andrew Lunn
2019-06-17 22:19 ` Florian Fainelli
0 siblings, 2 replies; 11+ messages in thread
From: René van Dorst @ 2019-06-17 21:33 UTC (permalink / raw)
To: Andrew Lunn
Cc: Sean Wang, Florian Fainelli, David S . Miller, Matthias Brugger,
Vivien Didelot, netdev, john, linux-mediatek, linux-mips
Quoting Andrew Lunn <andrew@lunn.ch>:
> On Sun, Jun 16, 2019 at 08:20:08PM +0200, René van Dorst wrote:
>> Like many other mediatek SOCs, the MT7621 SOC and the internal
>> MT7530 switch both
>> supports TRGMII mode. MT7621 TRGMII speed is 1200MBit.
>
> Hi René
>
Hi Andrew,
> Is TRGMII used only between the SoC and the Switch? Or does external
> ports of the switch also support 1200Mbit/s? If external ports support
> this, what does ethtool show for Speed?
Only the first GMAC of the SOC and port 6 of the switch supports this mode.
The switch can be internal in the SOC but also a separate chip.
PHYLINK and ethertool reports the link as 1Gbit.
The link is fixed-link with speed = 1000.
dmesg output with unposted PHYLINK patches:
[ 5.236763] mt7530 mdio-bus:1f: configuring for fixed/trgmii link mode
[ 5.249813] mt7530 mdio-bus:1f: phylink_mac_config:
mode=fixed/trgmii/1Gbps/Full adv=00,00000000,00000220 pause=12 link=1
an=1
[ 6.389435] mtk_soc_eth 1e100000.ethernet eth0: phylink_mac_config:
mode=fixed/trgmii/1Gbps/Full adv=00,00000000,00000220 pause=12 link=1
an=1
# ethtool eth0
Settings for eth0:
Supported ports: [ MII ]
Supported link modes: 1000baseT/Full
Supported pause frame use: No
Supports auto-negotiation: No
Supported FEC modes: Not reported
Advertised link modes: 1000baseT/Full
Advertised pause frame use: No
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: 1000Mb/s
Duplex: Full
Port: MII
PHYAD: 0
Transceiver: internal
Auto-negotiation: on
Current message level: 0x000000ff (255)
drv probe link timer ifdown ifup rx_err tx_err
Link detected: yes
I already have report from a MT7623 user that this patch gives issues.
I send v2 of the patch if I fixed that issue.
Also I think it is better to add a XTAL frequency check.
The PLL values are only valid with a 40MHz crystal.
Any other comments for v2?
Greats,
René
>
> Thanks
> Andrew
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH net-next 0/2] net: mediatek: Add MT7621 TRGMII mode support
2019-06-17 21:33 ` René van Dorst
@ 2019-06-17 21:44 ` Andrew Lunn
2019-06-17 23:20 ` René van Dorst
2019-06-17 22:19 ` Florian Fainelli
1 sibling, 1 reply; 11+ messages in thread
From: Andrew Lunn @ 2019-06-17 21:44 UTC (permalink / raw)
To: René van Dorst
Cc: Sean Wang, Florian Fainelli, David S . Miller, Matthias Brugger,
Vivien Didelot, netdev, john, linux-mediatek, linux-mips
On Mon, Jun 17, 2019 at 09:33:12PM +0000, René van Dorst wrote:
> Quoting Andrew Lunn <andrew@lunn.ch>:
>
> >On Sun, Jun 16, 2019 at 08:20:08PM +0200, René van Dorst wrote:
> >>Like many other mediatek SOCs, the MT7621 SOC and the internal MT7530
> >>switch both
> >>supports TRGMII mode. MT7621 TRGMII speed is 1200MBit.
> >
> >Hi René
> >
>
> Hi Andrew,
>
> >Is TRGMII used only between the SoC and the Switch? Or does external
> >ports of the switch also support 1200Mbit/s? If external ports support
> >this, what does ethtool show for Speed?
>
> Only the first GMAC of the SOC and port 6 of the switch supports this mode.
> The switch can be internal in the SOC but also a separate chip.
>
> PHYLINK and ethertool reports the link as 1Gbit.
> The link is fixed-link with speed = 1000.
>
> dmesg output with unposted PHYLINK patches:
> [ 5.236763] mt7530 mdio-bus:1f: configuring for fixed/trgmii link mode
> [ 5.249813] mt7530 mdio-bus:1f: phylink_mac_config:
> mode=fixed/trgmii/1Gbps/Full adv=00,00000000,00000220 pause=12 link=1 an=1
> [ 6.389435] mtk_soc_eth 1e100000.ethernet eth0: phylink_mac_config:
> mode=fixed/trgmii/1Gbps/Full adv=00,00000000,00000220 pause=12 link=1 an=1
With PHYLINK, you can probably set the fixed link to the true 1.2Gbps.
> # ethtool eth0
> Settings for eth0:
> Supported ports: [ MII ]
> Supported link modes: 1000baseT/Full
> Supported pause frame use: No
> Supports auto-negotiation: No
> Supported FEC modes: Not reported
> Advertised link modes: 1000baseT/Full
> Advertised pause frame use: No
> Advertised auto-negotiation: No
> Advertised FEC modes: Not reported
> Speed: 1000Mb/s
We could consider adding 1200BaseT/Full?
Andrew
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH net-next 0/2] net: mediatek: Add MT7621 TRGMII mode support
2019-06-17 21:44 ` Andrew Lunn
@ 2019-06-17 23:20 ` René van Dorst
2019-06-18 1:53 ` Andrew Lunn
0 siblings, 1 reply; 11+ messages in thread
From: René van Dorst @ 2019-06-17 23:20 UTC (permalink / raw)
To: Andrew Lunn
Cc: Sean Wang, Florian Fainelli, David S . Miller, Matthias Brugger,
Vivien Didelot, netdev, john, linux-mediatek, linux-mips
Quoting Andrew Lunn <andrew@lunn.ch>:
Hi Andrew,
> On Mon, Jun 17, 2019 at 09:33:12PM +0000, René van Dorst wrote:
>> Quoting Andrew Lunn <andrew@lunn.ch>:
>>
>> >On Sun, Jun 16, 2019 at 08:20:08PM +0200, René van Dorst wrote:
>> >>Like many other mediatek SOCs, the MT7621 SOC and the internal MT7530
>> >>switch both
>> >>supports TRGMII mode. MT7621 TRGMII speed is 1200MBit.
>> >
>> >Hi René
>> >
>>
>> Hi Andrew,
>>
>> >Is TRGMII used only between the SoC and the Switch? Or does external
>> >ports of the switch also support 1200Mbit/s? If external ports support
>> >this, what does ethtool show for Speed?
>>
>> Only the first GMAC of the SOC and port 6 of the switch supports this mode.
>> The switch can be internal in the SOC but also a separate chip.
>>
>> PHYLINK and ethertool reports the link as 1Gbit.
>> The link is fixed-link with speed = 1000.
>>
>> dmesg output with unposted PHYLINK patches:
>> [ 5.236763] mt7530 mdio-bus:1f: configuring for fixed/trgmii link mode
>> [ 5.249813] mt7530 mdio-bus:1f: phylink_mac_config:
>> mode=fixed/trgmii/1Gbps/Full adv=00,00000000,00000220 pause=12 link=1 an=1
>> [ 6.389435] mtk_soc_eth 1e100000.ethernet eth0: phylink_mac_config:
>> mode=fixed/trgmii/1Gbps/Full adv=00,00000000,00000220 pause=12 link=1 an=1
>
> With PHYLINK, you can probably set the fixed link to the true 1.2Gbps.
By adding some extra speed states in the code it seems to work.
+ if (state->speed == 1200)
+ mcr |= PMCR_FORCE_SPEED_1000;
dmesg:
[ 5.261375] mt7530 mdio-bus:1f: configuring for fixed/trgmii link mode
[ 5.274390] mt7530 mdio-bus:1f: phylink_mac_config:
mode=fixed/trgmii/Unsupported (update phy-core.c)/Full
adv=00,00000000,00000200 pause=12 link=1 an=1
[ 6.296614] mtk_soc_eth 1e100000.ethernet eth0: configuring for
fixed/trgmii link mode
[ 6.313608] mtk_soc_eth 1e100000.ethernet eth0: phylink_mac_config:
mode=fixed/trgmii/Unsupported (update phy core.c)/Full
adv=00,00000000,00000200 pause=12 link=1 an=1
# ethtool eth0
Settings for eth0:
Supported ports: [ MII ]
Supported link modes: Not reported
Supported pause frame use: No
Supports auto-negotiation: No
Supported FEC modes: Not reported
Advertised link modes: Not reported
Advertised pause frame use: No
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: 1200Mb/s
Duplex: Full
Port: MII
PHYAD: 0
Transceiver: internal
Auto-negotiation: on
Current message level: 0x000000ff (255)
drv probe link timer ifdown ifup rx_err tx_err
Link detected: yes
>> # ethtool eth0
>> Settings for eth0:
>> Supported ports: [ MII ]
>> Supported link modes: 1000baseT/Full
>> Supported pause frame use: No
>> Supports auto-negotiation: No
>> Supported FEC modes: Not reported
>> Advertised link modes: 1000baseT/Full
>> Advertised pause frame use: No
>> Advertised auto-negotiation: No
>> Advertised FEC modes: Not reported
>> Speed: 1000Mb/s
>
> We could consider adding 1200BaseT/Full?
I don't have any opinion about this.
It is great that it shows nicely in ethtool but I think supporting more
speeds in phy_speed_to_str() is enough.
Also you may want to add other SOCs trgmii ranges too:
- 1200BaseT/Full for mt7621 only
- 2000BaseT/Full for mt7623 and mt7683
- 2600BaseT/Full for mt7623 only
I leave the decision to you.
Greats,
René
>
> Andrew
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH net-next 0/2] net: mediatek: Add MT7621 TRGMII mode support
2019-06-17 23:20 ` René van Dorst
@ 2019-06-18 1:53 ` Andrew Lunn
2019-06-18 2:21 ` Florian Fainelli
0 siblings, 1 reply; 11+ messages in thread
From: Andrew Lunn @ 2019-06-18 1:53 UTC (permalink / raw)
To: René van Dorst
Cc: Sean Wang, Florian Fainelli, David S . Miller, Matthias Brugger,
Vivien Didelot, netdev, john, linux-mediatek, linux-mips
> By adding some extra speed states in the code it seems to work.
>
> + if (state->speed == 1200)
> + mcr |= PMCR_FORCE_SPEED_1000;
Hi René
Is TRGMII always 1.2G? Or can you set it to 1000 or 1200? This
PMCR_FORCE_SPEED_1000 feels wrong.
> >We could consider adding 1200BaseT/Full?
>
> I don't have any opinion about this.
> It is great that it shows nicely in ethtool but I think supporting more
> speeds in phy_speed_to_str() is enough.
>
> Also you may want to add other SOCs trgmii ranges too:
> - 1200BaseT/Full for mt7621 only
> - 2000BaseT/Full for mt7623 and mt7683
> - 2600BaseT/Full for mt7623 only
Are these standardised in any way? Or MTK proprietary? Also, is the T
in BaseT correct? These speeds work over copper cables? Or should we
be talking about 1200BaseKX?
Thanks
Andrew
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH net-next 0/2] net: mediatek: Add MT7621 TRGMII mode support
2019-06-18 1:53 ` Andrew Lunn
@ 2019-06-18 2:21 ` Florian Fainelli
2019-06-18 11:46 ` René van Dorst
0 siblings, 1 reply; 11+ messages in thread
From: Florian Fainelli @ 2019-06-18 2:21 UTC (permalink / raw)
To: Andrew Lunn, René van Dorst
Cc: Sean Wang, David S . Miller, Matthias Brugger, Vivien Didelot,
netdev, john, linux-mediatek, linux-mips
On 6/17/2019 6:53 PM, Andrew Lunn wrote:
>> By adding some extra speed states in the code it seems to work.
>>
>> + if (state->speed == 1200)
>> + mcr |= PMCR_FORCE_SPEED_1000;
>
> Hi René
>
> Is TRGMII always 1.2G? Or can you set it to 1000 or 1200? This
> PMCR_FORCE_SPEED_1000 feels wrong.
It is not uncommon to have to "force" 1G to get a higher speed, there is
something similar with B53 switches configuring the CPU ports at 2GB/sec
(proprietary too and not standardized either).
>
>>> We could consider adding 1200BaseT/Full?
>>
>> I don't have any opinion about this.
>> It is great that it shows nicely in ethtool but I think supporting more
>> speeds in phy_speed_to_str() is enough.
>>
>> Also you may want to add other SOCs trgmii ranges too:
>> - 1200BaseT/Full for mt7621 only
>> - 2000BaseT/Full for mt7623 and mt7683
>> - 2600BaseT/Full for mt7623 only
>
> Are these standardised in any way? Or MTK proprietary? Also, is the T
> in BaseT correct? These speeds work over copper cables? Or should we
> be talking about 1200BaseKX?
Looks like this is MTK proprietary:
http://lists.infradead.org/pipermail/linux-mediatek/2016-September/007083.html
https://patchwork.kernel.org/patch/9341129/
--
Florian
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH net-next 0/2] net: mediatek: Add MT7621 TRGMII mode support
2019-06-18 2:21 ` Florian Fainelli
@ 2019-06-18 11:46 ` René van Dorst
0 siblings, 0 replies; 11+ messages in thread
From: René van Dorst @ 2019-06-18 11:46 UTC (permalink / raw)
To: Florian Fainelli
Cc: Andrew Lunn, Sean Wang, David S . Miller, Matthias Brugger,
Vivien Didelot, netdev, john, linux-mediatek, linux-mips
Quoting Florian Fainelli <f.fainelli@gmail.com>:
Hi Andrew and Florian,
> On 6/17/2019 6:53 PM, Andrew Lunn wrote:
>>> By adding some extra speed states in the code it seems to work.
>>>
>>> + if (state->speed == 1200)
>>> + mcr |= PMCR_FORCE_SPEED_1000;
>>
>> Hi René
>>
>> Is TRGMII always 1.2G? Or can you set it to 1000 or 1200?
In case of the MT7621 SOC yes, according to the SDKs the MT7623 has 2 options
2GBit and 2.6Gbit. The current mt7530 driver only set TRGMII speed at 2Gbit.
>> This PMCR_FORCE_SPEED_1000 feels wrong.
>
> It is not uncommon to have to "force" 1G to get a higher speed, there is
> something similar with B53 switches configuring the CPU ports at 2GB/sec
> (proprietary too and not standardized either).
On the SOC MAC side it is basicly only a MAC clock change.
MAC control registers still need to be set forced 1G.
>
>>
>>>> We could consider adding 1200BaseT/Full?
>>>
>>> I don't have any opinion about this.
>>> It is great that it shows nicely in ethtool but I think supporting more
>>> speeds in phy_speed_to_str() is enough.
>>>
>>> Also you may want to add other SOCs trgmii ranges too:
>>> - 1200BaseT/Full for mt7621 only
>>> - 2000BaseT/Full for mt7623 and mt7683
>>> - 2600BaseT/Full for mt7623 only
>>
>> Are these standardised in any way? Or MTK proprietary? Also, is the T
>> in BaseT correct? These speeds work over copper cables? Or should we
>> be talking about 1200BaseKX?
>
> Looks like this is MTK proprietary:
>
> http://lists.infradead.org/pipermail/linux-mediatek/2016-September/007083.html
> https://patchwork.kernel.org/patch/9341129/
> --
> Florian
MTK proprietary, But I think it is equal too the RGMII but with a
faster clock.
But do we need a "xxxxBaseT/Full" at all for these fixed-link cases?
If I am correct a "xxxxBaseT/Full" is only needed to automatically select the
best option. But with fixed-link we force it so extra "xxxxBaseT/Full" is not
needed.
Greats,
René
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH net-next 0/2] net: mediatek: Add MT7621 TRGMII mode support
2019-06-17 21:33 ` René van Dorst
2019-06-17 21:44 ` Andrew Lunn
@ 2019-06-17 22:19 ` Florian Fainelli
1 sibling, 0 replies; 11+ messages in thread
From: Florian Fainelli @ 2019-06-17 22:19 UTC (permalink / raw)
To: René van Dorst, Andrew Lunn
Cc: Sean Wang, David S . Miller, Matthias Brugger, Vivien Didelot,
netdev, john, linux-mediatek, linux-mips
On 6/17/19 2:33 PM, René van Dorst wrote:
> Quoting Andrew Lunn <andrew@lunn.ch>:
>
>> On Sun, Jun 16, 2019 at 08:20:08PM +0200, René van Dorst wrote:
>>> Like many other mediatek SOCs, the MT7621 SOC and the internal MT7530
>>> switch both
>>> supports TRGMII mode. MT7621 TRGMII speed is 1200MBit.
>>
>> Hi René
>>
>
> Hi Andrew,
>
>> Is TRGMII used only between the SoC and the Switch? Or does external
>> ports of the switch also support 1200Mbit/s? If external ports support
>> this, what does ethtool show for Speed?
>
> Only the first GMAC of the SOC and port 6 of the switch supports this mode.
> The switch can be internal in the SOC but also a separate chip.
>
> PHYLINK and ethertool reports the link as 1Gbit.
> The link is fixed-link with speed = 1000.
>
> dmesg output with unposted PHYLINK patches:
> [ 5.236763] mt7530 mdio-bus:1f: configuring for fixed/trgmii link mode
> [ 5.249813] mt7530 mdio-bus:1f: phylink_mac_config:
> mode=fixed/trgmii/1Gbps/Full adv=00,00000000,00000220 pause=12 link=1 an=1
> [ 6.389435] mtk_soc_eth 1e100000.ethernet eth0: phylink_mac_config:
> mode=fixed/trgmii/1Gbps/Full adv=00,00000000,00000220 pause=12 link=1 an=1
>
> # ethtool eth0
> Settings for eth0:
> Supported ports: [ MII ]
> Supported link modes: 1000baseT/Full
> Supported pause frame use: No
> Supports auto-negotiation: No
> Supported FEC modes: Not reported
> Advertised link modes: 1000baseT/Full
> Advertised pause frame use: No
> Advertised auto-negotiation: No
> Advertised FEC modes: Not reported
> Speed: 1000Mb/s
> Duplex: Full
> Port: MII
> PHYAD: 0
> Transceiver: internal
> Auto-negotiation: on
> Current message level: 0x000000ff (255)
> drv probe link timer ifdown ifup rx_err
> tx_err
> Link detected: yes
>
>
>
> I already have report from a MT7623 user that this patch gives issues.
>
> I send v2 of the patch if I fixed that issue.
>
> Also I think it is better to add a XTAL frequency check.
> The PLL values are only valid with a 40MHz crystal.
>
> Any other comments for v2?
Looks good to me otherwise.
--
Florian
^ permalink raw reply [flat|nested] 11+ messages in thread