From: Robert Beckett <bob.beckett@collabora.com>
To: netdev@vger.kernel.org
Cc: Robert Beckett <bob.beckett@collabora.com>,
Andrew Lunn <andrew@lunn.ch>,
Vivien Didelot <vivien.didelot@gmail.com>,
Florian Fainelli <f.fainelli@gmail.com>,
"David S. Miller" <davem@davemloft.net>
Subject: [PATCH 0/7] net: dsa: mv88e6xxx: features to handle network storms
Date: Tue, 10 Sep 2019 16:41:46 +0100 [thread overview]
Message-ID: <20190910154238.9155-1-bob.beckett@collabora.com> (raw)
This patch-set adds support for some features of the Marvell switch
chips that can be used to handle packet storms.
The rationale for this was a setup that requires the ability to receive
traffic from one port, while a packet storm is occuring on another port
(via an external switch with a deliberate loop). This is needed to
ensure vital data delivery from a specific port, while mitigating any
loops or DoS that a user may introduce on another port (can't guarantee
sensible users).
[patch 1/7] configures auto negotiation for CPU ports connected with
phys to enable pause frame propogation.
[patch 2/7] allows setting of port's default output queue priority for
any ingressing packets on that port.
[patch 3/7] dt-bindings for patch 2.
[patch 4/7] allows setting of a port's queue scheduling so that it can
prioritise egress of traffic routed from high priority ports.
[patch 5/7] dt-bindings for patch 4.
[patch 6/7] allows ports to rate limit their egress. This can be used to
stop the host CPU from becoming swamped by packet delivery and exhasting
descriptors.
[patch 7/7] dt-bindings for patch 6.
Robert Beckett (7):
net/dsa: configure autoneg for CPU port
net: dsa: mv88e6xxx: add ability to set default queue priorities per
port
dt-bindings: mv88e6xxx: add ability to set default queue priorities
per port
net: dsa: mv88e6xxx: add ability to set queue scheduling
dt-bindings: mv88e6xxx: add ability to set queue scheduling
net: dsa: mv88e6xxx: add egress rate limiting
dt-bindings: mv88e6xxx: add egress rate limiting
.../devicetree/bindings/net/dsa/marvell.txt | 38 +++++
drivers/net/dsa/mv88e6xxx/chip.c | 122 ++++++++++++---
drivers/net/dsa/mv88e6xxx/chip.h | 5 +-
drivers/net/dsa/mv88e6xxx/port.c | 140 +++++++++++++++++-
drivers/net/dsa/mv88e6xxx/port.h | 24 ++-
include/dt-bindings/net/dsa-mv88e6xxx.h | 22 +++
net/dsa/port.c | 10 ++
7 files changed, 327 insertions(+), 34 deletions(-)
create mode 100644 include/dt-bindings/net/dsa-mv88e6xxx.h
--
2.18.0
next reply other threads:[~2019-09-10 15:43 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-10 15:41 Robert Beckett [this message]
2019-09-10 15:41 ` [PATCH 1/7] net/dsa: configure autoneg for CPU port Robert Beckett
2019-09-10 16:14 ` Vivien Didelot
2019-09-10 16:56 ` Florian Fainelli
2019-09-10 18:26 ` Andrew Lunn
2019-09-10 18:29 ` Florian Fainelli
2019-09-11 9:16 ` Robert Beckett
2019-09-11 9:54 ` Robert Beckett
2019-09-11 22:52 ` Andrew Lunn
2019-09-12 10:14 ` Robert Beckett
2019-09-12 10:43 ` Andrew Lunn
2019-09-11 11:43 ` kbuild test robot
2019-09-14 7:16 ` kbuild test robot
2019-09-10 15:41 ` [PATCH 2/7] net: dsa: mv88e6xxx: add ability to set default queue priorities per port Robert Beckett
2019-09-10 16:43 ` Vivien Didelot
2019-09-10 15:41 ` [PATCH 3/7] dt-bindings: " Robert Beckett
2019-09-10 16:42 ` Florian Fainelli
2019-09-10 16:49 ` Vivien Didelot
2019-09-10 20:46 ` Vladimir Oltean
2019-09-10 15:41 ` [PATCH 4/7] net: dsa: mv88e6xxx: add ability to set queue scheduling Robert Beckett
2019-09-10 17:18 ` Vivien Didelot
2019-09-10 15:41 ` [PATCH 5/7] dt-bindings: " Robert Beckett
2019-09-10 15:41 ` [PATCH 6/7] net: dsa: mv88e6xxx: add egress rate limiting Robert Beckett
2019-09-10 17:13 ` Vivien Didelot
2019-09-11 12:26 ` kbuild test robot
2019-09-10 15:41 ` [PATCH 7/7] dt-bindings: " Robert Beckett
2019-09-10 16:49 ` [PATCH 0/7] net: dsa: mv88e6xxx: features to handle network storms Florian Fainelli
2019-09-11 9:43 ` Robert Beckett
2019-09-11 11:21 ` Ido Schimmel
2019-09-11 11:49 ` Robert Beckett
2019-09-11 22:58 ` Andrew Lunn
2019-09-12 9:05 ` Ido Schimmel
2019-09-12 9:03 ` Ido Schimmel
2019-09-12 9:21 ` Andrew Lunn
2019-09-12 16:25 ` Florian Fainelli
2019-09-12 16:46 ` Robert Beckett
2019-09-12 17:41 ` Florian Fainelli
2019-09-13 12:47 ` Robert Beckett
2019-09-10 17:19 ` Vivien Didelot
2019-09-11 9:46 ` Robert Beckett
2019-09-11 15:31 ` Vivien Didelot
2019-09-11 23:01 ` Andrew Lunn
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