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From: Andrew Lunn <andrew@lunn.ch>
To: Robert Beckett <bob.beckett@collabora.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>,
	netdev@vger.kernel.org, Vivien Didelot <vivien.didelot@gmail.com>,
	"David S. Miller" <davem@davemloft.net>,
	bob.beckett@gmail.com
Subject: Re: [PATCH 1/7] net/dsa: configure autoneg for CPU port
Date: Thu, 12 Sep 2019 12:43:33 +0200	[thread overview]
Message-ID: <20190912104333.GE17773@lunn.ch> (raw)
In-Reply-To: <8d63d4dbd9d075b5c238fd8933673b95b2fa96e9.camel@collabora.com>

> > It actually has nothing to do with PHY to PHY connections. You can
> > use
> > pause frames with direct MAC to MAC connections. PHY auto-negotiation
> > is one way to indicate both ends support it, but there are also other
> > ways. e.g.
> > 
> > ethtool -A|--pause devname [autoneg on|off] [rx on|off] [tx on|off]
> > 
> > on the SoC you could do
> > 
> > ethtool --pause eth0 autoneg off rx on tx on
> > 
> > to force the SoC to send and process pause frames. Ideally i would
> > prefer a solution like this, since it is not a change of behaviour
> > for
> > everybody else.
> 
> Good point, well made.
> The reason for using autoneg in this series was due to having no netdev
> to run ethtool against for the CPU port.

Do you need one? It is the IMX which is the bottle neck. It is the one
which needs to send pause frames. You have a netdev for that. Have you
checked if the switch will react on pause frames without your
change. Play with the command i give above on the master interface. It
looks like the FEC driver fully supports synchronous pause
configuration.

> However, given that the phy on the marvell switch is capable of
> autoneg , is it not reasonable to setup the advertisement and let
> autoneg take care of it if using phy to phy connection?

Most designs don't use back to back PHYs for the CPU port. They save
the cost and connect MACs back to back using RGMII, or maybe SERDES.
If we are going for a method which can configure pause between the CPU
and the switch, it needs to be generic and work for both setups.

    Andrew

  reply	other threads:[~2019-09-12 10:43 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-10 15:41 [PATCH 0/7] net: dsa: mv88e6xxx: features to handle network storms Robert Beckett
2019-09-10 15:41 ` [PATCH 1/7] net/dsa: configure autoneg for CPU port Robert Beckett
2019-09-10 16:14   ` Vivien Didelot
2019-09-10 16:56   ` Florian Fainelli
2019-09-10 18:26   ` Andrew Lunn
2019-09-10 18:29     ` Florian Fainelli
2019-09-11  9:16       ` Robert Beckett
2019-09-11  9:54         ` Robert Beckett
2019-09-11 22:52         ` Andrew Lunn
2019-09-12 10:14           ` Robert Beckett
2019-09-12 10:43             ` Andrew Lunn [this message]
2019-09-11 11:43   ` kbuild test robot
2019-09-14  7:16   ` kbuild test robot
2019-09-10 15:41 ` [PATCH 2/7] net: dsa: mv88e6xxx: add ability to set default queue priorities per port Robert Beckett
2019-09-10 16:43   ` Vivien Didelot
2019-09-10 15:41 ` [PATCH 3/7] dt-bindings: " Robert Beckett
2019-09-10 16:42   ` Florian Fainelli
2019-09-10 16:49     ` Vivien Didelot
2019-09-10 20:46       ` Vladimir Oltean
2019-09-10 15:41 ` [PATCH 4/7] net: dsa: mv88e6xxx: add ability to set queue scheduling Robert Beckett
2019-09-10 17:18   ` Vivien Didelot
2019-09-10 15:41 ` [PATCH 5/7] dt-bindings: " Robert Beckett
2019-09-10 15:41 ` [PATCH 6/7] net: dsa: mv88e6xxx: add egress rate limiting Robert Beckett
2019-09-10 17:13   ` Vivien Didelot
2019-09-11 12:26   ` kbuild test robot
2019-09-10 15:41 ` [PATCH 7/7] dt-bindings: " Robert Beckett
2019-09-10 16:49 ` [PATCH 0/7] net: dsa: mv88e6xxx: features to handle network storms Florian Fainelli
2019-09-11  9:43   ` Robert Beckett
2019-09-11 11:21   ` Ido Schimmel
2019-09-11 11:49     ` Robert Beckett
2019-09-11 22:58       ` Andrew Lunn
2019-09-12  9:05         ` Ido Schimmel
2019-09-12  9:03       ` Ido Schimmel
2019-09-12  9:21         ` Andrew Lunn
2019-09-12 16:25         ` Florian Fainelli
2019-09-12 16:46           ` Robert Beckett
2019-09-12 17:41             ` Florian Fainelli
2019-09-13 12:47               ` Robert Beckett
2019-09-10 17:19 ` Vivien Didelot
2019-09-11  9:46   ` Robert Beckett
2019-09-11 15:31     ` Vivien Didelot
2019-09-11 23:01     ` Andrew Lunn

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