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From: Andrew Lunn <andrew@lunn.ch>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Vivien Didelot <vivien.didelot@gmail.com>,
	Florian Fainelli <f.fainelli@gmail.com>,
	netdev <netdev@vger.kernel.org>, DENG Qingfang <dqfext@gmail.com>
Subject: Re: [net-next PATCH 1/5] net: dsa: tag_rtl4_a: Implement Realtek 4 byte A tag
Date: Thu, 4 Jun 2020 02:54:07 +0200	[thread overview]
Message-ID: <20200604005407.GA977471@lunn.ch> (raw)
In-Reply-To: <CACRpkdbu4O_6SvgTU3A5mYVrAn-VWpr9=0LD+M+LduuqVnjsnA@mail.gmail.com>

> > Where is spanning tree performed? In the switch, or by the
> > host?
> 
> In the switch I think.
> There is a register in the ASIC to set the spanning tree status
> to disabled, blocking, learning or forwarding.

Hi Linus

Spanning tree needs two parts. You need to be able to change the ports
between disabled, blocking, learning, forwarding. And you need to be
able to send/receive frames.

If spanning tree is performed in the ASIC, i don't see why there would
be registers to control the port status. It would do it all itself,
and not export these controls.

So i would not give up on spanning tree as a way to reverse engineer
this.

    Andrew

  reply	other threads:[~2020-06-04  0:54 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-02 20:54 [net-next PATCH 1/5] net: dsa: tag_rtl4_a: Implement Realtek 4 byte A tag Linus Walleij
2020-06-02 20:54 ` [net-next PATCH 2/5] net: dsa: rtl8366rb: Support the CPU DSA tag Linus Walleij
2020-06-02 20:54 ` [net-next PATCH 3/5] net: dsa: rtl8366: Split out default VLAN config Linus Walleij
2020-06-02 20:54 ` [net-next PATCH 4/5] net: dsa: rtl8366: VLAN 0 as disable tagging Linus Walleij
2020-06-02 20:54 ` [net-next PATCH 5/5] net: dsa: rtl8366: Use top VLANs for default Linus Walleij
2020-06-03  2:19   ` DENG Qingfang
2020-06-03  8:33     ` Linus Walleij
2020-06-02 22:48 ` [net-next PATCH 1/5] net: dsa: tag_rtl4_a: Implement Realtek 4 byte A tag David Miller
2020-06-03  8:32   ` Linus Walleij
2020-06-03 13:52 ` Andrew Lunn
2020-06-03 22:01   ` Linus Walleij
2020-06-04  0:54     ` Andrew Lunn [this message]
2020-06-04  7:52       ` Linus Walleij
2020-06-04 11:22         ` Vladimir Oltean
2020-06-17  8:06           ` Linus Walleij
2020-06-18  3:17             ` DENG Qingfang

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