* [PATCH net-next V2 1/2] ethtool: Add support for 100Gbps per lane link modes
@ 2020-07-07 3:42 Saeed Mahameed
2020-07-07 3:42 ` [PATCH net-next V2 2/2] net/mlx5: Added " Saeed Mahameed
2020-07-08 22:30 ` [PATCH net-next V2 1/2] ethtool: Add " David Miller
0 siblings, 2 replies; 4+ messages in thread
From: Saeed Mahameed @ 2020-07-07 3:42 UTC (permalink / raw)
To: David S. Miller, Jakub Kicinski
Cc: netdev, Andrew Lunn, Meir Lichtinger, Aya Levin, Saeed Mahameed
From: Meir Lichtinger <meirl@mellanox.com>
Define 100G, 200G and 400G link modes using 100Gbps per lane
LR, ER and FR are defined as a single link mode because they are
using same technology and by design are fully interoperable.
EEPROM content indicates if the module is LR, ER, or FR, and the
user space ethtool decoder is planned to support decoding these
modes in the EEPROM.
Signed-off-by: Meir Lichtinger <meirl@mellanox.com>
CC: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Aya Levin <ayal@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
---
v2: Improved commit message according to Andrew's comments and questions.
drivers/net/phy/phy-core.c | 17 ++++++++++++++++-
include/uapi/linux/ethtool.h | 15 +++++++++++++++
net/ethtool/common.c | 15 +++++++++++++++
net/ethtool/linkmodes.c | 15 +++++++++++++++
4 files changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 46bd68e9ecfa..ff8e14b01eeb 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -8,7 +8,7 @@
const char *phy_speed_to_str(int speed)
{
- BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 75,
+ BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 90,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
"If a speed or mode has been added please update phy_speed_to_str "
"and the PHY settings array.\n");
@@ -78,12 +78,22 @@ static const struct phy_setting settings[] = {
PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full ),
PHY_SETTING( 400000, FULL, 400000baseDR8_Full ),
PHY_SETTING( 400000, FULL, 400000baseSR8_Full ),
+ PHY_SETTING( 400000, FULL, 400000baseCR4_Full ),
+ PHY_SETTING( 400000, FULL, 400000baseKR4_Full ),
+ PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full ),
+ PHY_SETTING( 400000, FULL, 400000baseDR4_Full ),
+ PHY_SETTING( 400000, FULL, 400000baseSR4_Full ),
/* 200G */
PHY_SETTING( 200000, FULL, 200000baseCR4_Full ),
PHY_SETTING( 200000, FULL, 200000baseKR4_Full ),
PHY_SETTING( 200000, FULL, 200000baseLR4_ER4_FR4_Full ),
PHY_SETTING( 200000, FULL, 200000baseDR4_Full ),
PHY_SETTING( 200000, FULL, 200000baseSR4_Full ),
+ PHY_SETTING( 200000, FULL, 200000baseCR2_Full ),
+ PHY_SETTING( 200000, FULL, 200000baseKR2_Full ),
+ PHY_SETTING( 200000, FULL, 200000baseLR2_ER2_FR2_Full ),
+ PHY_SETTING( 200000, FULL, 200000baseDR2_Full ),
+ PHY_SETTING( 200000, FULL, 200000baseSR2_Full ),
/* 100G */
PHY_SETTING( 100000, FULL, 100000baseCR4_Full ),
PHY_SETTING( 100000, FULL, 100000baseKR4_Full ),
@@ -94,6 +104,11 @@ static const struct phy_setting settings[] = {
PHY_SETTING( 100000, FULL, 100000baseLR2_ER2_FR2_Full ),
PHY_SETTING( 100000, FULL, 100000baseDR2_Full ),
PHY_SETTING( 100000, FULL, 100000baseSR2_Full ),
+ PHY_SETTING( 100000, FULL, 100000baseCR_Full ),
+ PHY_SETTING( 100000, FULL, 100000baseKR_Full ),
+ PHY_SETTING( 100000, FULL, 100000baseLR_ER_FR_Full ),
+ PHY_SETTING( 100000, FULL, 100000baseDR_Full ),
+ PHY_SETTING( 100000, FULL, 100000baseSR_Full ),
/* 56G */
PHY_SETTING( 56000, FULL, 56000baseCR4_Full ),
PHY_SETTING( 56000, FULL, 56000baseKR4_Full ),
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index d1413538ef30..60856e0f9618 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -1600,6 +1600,21 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72,
ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73,
ETHTOOL_LINK_MODE_FEC_LLRS_BIT = 74,
+ ETHTOOL_LINK_MODE_100000baseKR_Full_BIT = 75,
+ ETHTOOL_LINK_MODE_100000baseSR_Full_BIT = 76,
+ ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT = 77,
+ ETHTOOL_LINK_MODE_100000baseCR_Full_BIT = 78,
+ ETHTOOL_LINK_MODE_100000baseDR_Full_BIT = 79,
+ ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT = 80,
+ ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT = 81,
+ ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82,
+ ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT = 83,
+ ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT = 84,
+ ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT = 85,
+ ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT = 86,
+ ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87,
+ ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT = 88,
+ ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,
/* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS
};
diff --git a/net/ethtool/common.c b/net/ethtool/common.c
index aaecfc916a4d..d3f2e0de215a 100644
--- a/net/ethtool/common.c
+++ b/net/ethtool/common.c
@@ -175,6 +175,21 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
__DEFINE_LINK_MODE_NAME(400000, DR8, Full),
__DEFINE_LINK_MODE_NAME(400000, CR8, Full),
__DEFINE_SPECIAL_MODE_NAME(FEC_LLRS, "LLRS"),
+ __DEFINE_LINK_MODE_NAME(100000, KR, Full),
+ __DEFINE_LINK_MODE_NAME(100000, SR, Full),
+ __DEFINE_LINK_MODE_NAME(100000, LR_ER_FR, Full),
+ __DEFINE_LINK_MODE_NAME(100000, DR, Full),
+ __DEFINE_LINK_MODE_NAME(100000, CR, Full),
+ __DEFINE_LINK_MODE_NAME(200000, KR2, Full),
+ __DEFINE_LINK_MODE_NAME(200000, SR2, Full),
+ __DEFINE_LINK_MODE_NAME(200000, LR2_ER2_FR2, Full),
+ __DEFINE_LINK_MODE_NAME(200000, DR2, Full),
+ __DEFINE_LINK_MODE_NAME(200000, CR2, Full),
+ __DEFINE_LINK_MODE_NAME(400000, KR4, Full),
+ __DEFINE_LINK_MODE_NAME(400000, SR4, Full),
+ __DEFINE_LINK_MODE_NAME(400000, LR4_ER4_FR4, Full),
+ __DEFINE_LINK_MODE_NAME(400000, DR4, Full),
+ __DEFINE_LINK_MODE_NAME(400000, CR4, Full),
};
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c
index fd4f3e58c6f6..317a93129551 100644
--- a/net/ethtool/linkmodes.c
+++ b/net/ethtool/linkmodes.c
@@ -257,6 +257,21 @@ static const struct link_mode_info link_mode_params[] = {
__DEFINE_LINK_MODE_PARAMS(400000, DR8, Full),
__DEFINE_LINK_MODE_PARAMS(400000, CR8, Full),
__DEFINE_SPECIAL_MODE_PARAMS(FEC_LLRS),
+ __DEFINE_LINK_MODE_PARAMS(100000, KR, Full),
+ __DEFINE_LINK_MODE_PARAMS(100000, SR, Full),
+ __DEFINE_LINK_MODE_PARAMS(100000, LR_ER_FR, Full),
+ __DEFINE_LINK_MODE_PARAMS(100000, DR, Full),
+ __DEFINE_LINK_MODE_PARAMS(100000, CR, Full),
+ __DEFINE_LINK_MODE_PARAMS(200000, KR2, Full),
+ __DEFINE_LINK_MODE_PARAMS(200000, SR2, Full),
+ __DEFINE_LINK_MODE_PARAMS(200000, LR2_ER2_FR2, Full),
+ __DEFINE_LINK_MODE_PARAMS(200000, DR2, Full),
+ __DEFINE_LINK_MODE_PARAMS(200000, CR2, Full),
+ __DEFINE_LINK_MODE_PARAMS(400000, KR4, Full),
+ __DEFINE_LINK_MODE_PARAMS(400000, SR4, Full),
+ __DEFINE_LINK_MODE_PARAMS(400000, LR4_ER4_FR4, Full),
+ __DEFINE_LINK_MODE_PARAMS(400000, DR4, Full),
+ __DEFINE_LINK_MODE_PARAMS(400000, CR4, Full),
};
static const struct nla_policy
--
2.26.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH net-next V2 2/2] net/mlx5: Added support for 100Gbps per lane link modes
2020-07-07 3:42 [PATCH net-next V2 1/2] ethtool: Add support for 100Gbps per lane link modes Saeed Mahameed
@ 2020-07-07 3:42 ` Saeed Mahameed
2020-07-08 22:30 ` David Miller
2020-07-08 22:30 ` [PATCH net-next V2 1/2] ethtool: Add " David Miller
1 sibling, 1 reply; 4+ messages in thread
From: Saeed Mahameed @ 2020-07-07 3:42 UTC (permalink / raw)
To: David S. Miller, Jakub Kicinski
Cc: netdev, Andrew Lunn, Meir Lichtinger, Aya Levin, Saeed Mahameed
From: Meir Lichtinger <meirl@mellanox.com>
This patch exposes new link modes using 100Gbps per lane, including 100G,
200G and 400G modes.
Signed-off-by: Meir Lichtinger <meirl@mellanox.com>
Reviewed-by: Aya Levin <ayal@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
---
.../net/ethernet/mellanox/mlx5/core/en/port.c | 3 +++
.../ethernet/mellanox/mlx5/core/en_ethtool.c | 21 ++++++++++++++++++-
include/linux/mlx5/port.h | 3 +++
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/port.c b/drivers/net/ethernet/mellanox/mlx5/core/en/port.c
index 2a8950b3056f..be83db63aca0 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/port.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/port.c
@@ -76,6 +76,9 @@ static const u32 mlx5e_ext_link_speed[MLX5E_EXT_LINK_MODES_NUMBER] = {
[MLX5E_100GAUI_2_100GBASE_CR2_KR2] = 100000,
[MLX5E_200GAUI_4_200GBASE_CR4_KR4] = 200000,
[MLX5E_400GAUI_8] = 400000,
+ [MLX5E_100GAUI_1_100GBASE_CR_KR] = 100000,
+ [MLX5E_200GAUI_2_200GBASE_CR2_KR2] = 200000,
+ [MLX5E_400GAUI_4_400GBASE_CR4_KR4] = 400000,
};
static void mlx5e_port_get_speed_arr(struct mlx5_core_dev *mdev,
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
index ec5658bbe3c5..6183bee7d21b 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
@@ -194,6 +194,24 @@ void mlx5e_build_ptys2ethtool_map(void)
ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
+ MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,
+ ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
+ ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
+ ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
+ ETHTOOL_LINK_MODE_100000baseDR_Full_BIT,
+ ETHTOOL_LINK_MODE_100000baseCR_Full_BIT);
+ MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext,
+ ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
+ ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
+ ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
+ ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT,
+ ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT);
+ MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext,
+ ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
+ ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
+ ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
+ ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,
+ ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT);
}
static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
@@ -1012,7 +1030,8 @@ static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
unsigned long modes[2];
for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
- if (*ptys2ext_ethtool_table[i].advertised == 0)
+ if (ptys2ext_ethtool_table[i].advertised[0] == 0 &&
+ ptys2ext_ethtool_table[i].advertised[1] == 0)
continue;
memset(modes, 0, sizeof(modes));
bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
diff --git a/include/linux/mlx5/port.h b/include/linux/mlx5/port.h
index de9a272c9f3d..2d45a6af52a4 100644
--- a/include/linux/mlx5/port.h
+++ b/include/linux/mlx5/port.h
@@ -104,8 +104,11 @@ enum mlx5e_ext_link_mode {
MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8,
MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9,
MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10,
+ MLX5E_100GAUI_1_100GBASE_CR_KR = 11,
MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12,
+ MLX5E_200GAUI_2_200GBASE_CR2_KR2 = 13,
MLX5E_400GAUI_8 = 15,
+ MLX5E_400GAUI_4_400GBASE_CR4_KR4 = 16,
MLX5E_EXT_LINK_MODES_NUMBER,
};
--
2.26.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH net-next V2 1/2] ethtool: Add support for 100Gbps per lane link modes
2020-07-07 3:42 [PATCH net-next V2 1/2] ethtool: Add support for 100Gbps per lane link modes Saeed Mahameed
2020-07-07 3:42 ` [PATCH net-next V2 2/2] net/mlx5: Added " Saeed Mahameed
@ 2020-07-08 22:30 ` David Miller
1 sibling, 0 replies; 4+ messages in thread
From: David Miller @ 2020-07-08 22:30 UTC (permalink / raw)
To: saeedm; +Cc: kuba, netdev, andrew, meirl, ayal
From: Saeed Mahameed <saeedm@mellanox.com>
Date: Mon, 6 Jul 2020 20:42:32 -0700
> From: Meir Lichtinger <meirl@mellanox.com>
>
> Define 100G, 200G and 400G link modes using 100Gbps per lane
>
> LR, ER and FR are defined as a single link mode because they are
> using same technology and by design are fully interoperable.
> EEPROM content indicates if the module is LR, ER, or FR, and the
> user space ethtool decoder is planned to support decoding these
> modes in the EEPROM.
>
> Signed-off-by: Meir Lichtinger <meirl@mellanox.com>
> CC: Andrew Lunn <andrew@lunn.ch>
> Reviewed-by: Aya Levin <ayal@mellanox.com>
> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
> ---
> v2: Improved commit message according to Andrew's comments and questions.
Applied.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH net-next V2 2/2] net/mlx5: Added support for 100Gbps per lane link modes
2020-07-07 3:42 ` [PATCH net-next V2 2/2] net/mlx5: Added " Saeed Mahameed
@ 2020-07-08 22:30 ` David Miller
0 siblings, 0 replies; 4+ messages in thread
From: David Miller @ 2020-07-08 22:30 UTC (permalink / raw)
To: saeedm; +Cc: kuba, netdev, andrew, meirl, ayal
From: Saeed Mahameed <saeedm@mellanox.com>
Date: Mon, 6 Jul 2020 20:42:33 -0700
> From: Meir Lichtinger <meirl@mellanox.com>
>
> This patch exposes new link modes using 100Gbps per lane, including 100G,
> 200G and 400G modes.
>
> Signed-off-by: Meir Lichtinger <meirl@mellanox.com>
> Reviewed-by: Aya Levin <ayal@mellanox.com>
> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Applied.
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-07-08 22:31 UTC | newest]
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2020-07-07 3:42 [PATCH net-next V2 1/2] ethtool: Add support for 100Gbps per lane link modes Saeed Mahameed
2020-07-07 3:42 ` [PATCH net-next V2 2/2] net/mlx5: Added " Saeed Mahameed
2020-07-08 22:30 ` David Miller
2020-07-08 22:30 ` [PATCH net-next V2 1/2] ethtool: Add " David Miller
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