From: Andrew Lunn <andrew@lunn.ch>
To: Kai-Heng Feng <kai.heng.feng@canonical.com>
Cc: jeffrey.t.kirsher@intel.com,
"David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
"moderated list:INTEL ETHERNET DRIVERS"
<intel-wired-lan@lists.osuosl.org>,
"open list:NETWORKING DRIVERS" <netdev@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] e1000e: Increase iteration on polling MDIC ready bit
Date: Thu, 24 Sep 2020 17:53:55 +0200 [thread overview]
Message-ID: <20200924155355.GC3821492@lunn.ch> (raw)
In-Reply-To: <20200924150958.18016-1-kai.heng.feng@canonical.com>
On Thu, Sep 24, 2020 at 11:09:58PM +0800, Kai-Heng Feng wrote:
> We are seeing the following error after S3 resume:
> [ 704.746874] e1000e 0000:00:1f.6 eno1: Setting page 0x6020
> [ 704.844232] e1000e 0000:00:1f.6 eno1: MDI Write did not complete
> [ 704.902817] e1000e 0000:00:1f.6 eno1: Setting page 0x6020
> [ 704.903075] e1000e 0000:00:1f.6 eno1: reading PHY page 769 (or 0x6020 shifted) reg 0x17
> [ 704.903281] e1000e 0000:00:1f.6 eno1: Setting page 0x6020
> [ 704.903486] e1000e 0000:00:1f.6 eno1: writing PHY page 769 (or 0x6020 shifted) reg 0x17
> [ 704.943155] e1000e 0000:00:1f.6 eno1: MDI Error
> ...
> [ 705.108161] e1000e 0000:00:1f.6 eno1: Hardware Error
>
> As Andrew Lunn pointed out, MDIO has nothing to do with phy, and indeed
> increase polling iteration can resolve the issue.
>
> While at it, also move the delay to the end of loop, to potentially save
> 50 us.
You are unlikely to save any time. 64 bits at 2.5MHz is 25.6uS. So it
is very unlikely doing a read directly after setting is going is going
to have E1000_MDIC_READY set. So this change likely causes an addition
read on MDIC. Did you profile this at all, for the normal case?
I also don't fully understand the fix. You are now looping up to 6400
times, each with a delay of 50uS. So that is around 12800 times more
than it actually needs to transfer the 64 bits! I've no idea how this
hardware works, but my guess would be, something is wrong with the
clock setup?
Andrew
next prev parent reply other threads:[~2020-09-24 15:54 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-23 7:47 [PATCH] e1000e: Power cycle phy on PM resume Kai-Heng Feng
2020-09-23 12:17 ` Andrew Lunn
2020-09-23 14:44 ` Kai-Heng Feng
2020-09-23 15:37 ` Andrew Lunn
2020-09-24 12:50 ` Kai-Heng Feng
2020-09-23 13:28 ` [Intel-wired-lan] " Paul Menzel
2020-09-23 14:46 ` Kai-Heng Feng
2020-09-23 15:02 ` Paul Menzel
2020-09-23 19:28 ` Andrew Lunn
2020-09-24 13:02 ` Paul Menzel
2020-09-24 15:09 ` [PATCH v2] e1000e: Increase iteration on polling MDIC ready bit Kai-Heng Feng
2020-09-24 15:32 ` [Intel-wired-lan] " Paul Menzel
2020-09-24 16:04 ` Andrew Lunn
2020-09-24 15:53 ` Andrew Lunn [this message]
2020-09-24 16:04 ` Kai-Heng Feng
2020-09-25 8:50 ` David Laight
2020-09-25 13:29 ` Andrew Lunn
2020-09-26 10:08 ` David Laight
2020-09-24 16:45 ` [PATCH v3] " Kai-Heng Feng
2020-09-24 19:57 ` Andrew Lunn
2020-09-25 3:57 ` Kai-Heng Feng
2020-09-25 5:16 ` [Intel-wired-lan] " Paul Menzel
2020-09-28 8:36 ` [PATCH v4] e1000e: Increase polling timeout on " Kai-Heng Feng
2020-09-29 13:08 ` [Intel-wired-lan] " Neftin, Sasha
2020-09-29 13:31 ` Kai-Heng Feng
2020-09-29 13:46 ` Neftin, Sasha
2020-09-29 15:08 ` Kai-Heng Feng
2020-09-29 15:11 ` David Laight
2020-09-29 15:12 ` Kai-Heng Feng
2020-09-30 6:54 ` Vitaly Lifshits
2020-10-05 6:23 ` Kai-Heng Feng
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