From: Jakub Kicinski <kuba@kernel.org>
To: Pavana Sharma <pavana.sharma@digi.com>
Cc: andrew@lunn.ch, ashkan.boldaji@digi.com, davem@davemloft.net,
f.fainelli@gmail.com, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, marek.behun@nic.cz,
netdev@vger.kernel.org, vivien.didelot@gmail.com
Subject: Re: [PATCH v8 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell
Date: Thu, 5 Nov 2020 17:52:52 -0800 [thread overview]
Message-ID: <20201105175252.12bdc0d3@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com> (raw)
In-Reply-To: <e6d70ebf3b10a1e7222d8820bc585765001028b8.1604388359.git.pavana.sharma@digi.com>
On Tue, 3 Nov 2020 18:50:38 +1000 Pavana Sharma wrote:
> The Marvell 88E6393X device is a single-chip integration of a 11-port
> Ethernet switch with eight integrated Gigabit Ethernet (GbE) transceivers
> and three 10-Gigabit interfaces.
>
> This patch adds functionalities specific to mv88e6393x family (88E6393X,
> 88E6193X and 88E6191X)
Please fix all checkpatch --strict --min-conf-desc-length=80 warnings
and what I point out below
> Co-developed-by: Ashkan Boldaji <ashkan.boldaji@digi.com>
> Signed-off-by: Ashkan Boldaji <ashkan.boldaji@digi.com>
> Signed-off-by: Pavana Sharma <pavana.sharma@digi.com>
> + reg &= ~(MV88E6XXX_PORT_MAC_CTL_SPEED_MASK |
> + MV88E6390_PORT_MAC_CTL_ALTSPEED |
> + MV88E6390_PORT_MAC_CTL_FORCE_SPEED);
Align the continuation lines under the opening bracket, like the kernel
coding style require, please.
> +
> + if (speed != SPEED_UNFORCED)
> + reg |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
> +
> + reg |= ctrl;
> +
> + err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
> + if (err)
> + return err;
> +
> + return 0;
no need to set err, just directly do:
return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL,
reg);
> +}
> +
> static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
> phy_interface_t mode, bool force)
> {
> +/* Offset 0x0E: Policy & MGMT Control Register for FAMILY 6191X 6193X 6393X*/
Missing space at the end of that comment.
> +static int mv88e6393x_port_policy_write(struct mv88e6xxx_chip *chip, u16 pointer,
> + u8 data)
> +{
> +
> + int err = 0;
> + int port;
> + u16 reg;
> +
> + /* Setup per Port policy register */
> + for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
> + if (dsa_is_unused_port(chip->ds, port))
> + continue;
> +
> + /* Prevent the use of an invalid port. */
> + if (mv88e6xxx_is_invalid_port(chip, port)) {
> + dev_err(chip->dev, "port %d is invalid\n", port);
> + err = -EINVAL;
did you mean to exit here? this assignment looks pointless
> + }
> + reg = MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE | pointer | data;
> + err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_POLICY_MGMT_CTL, reg);
> + }
> + return err;
> +}
> +int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
> +{
> + u16 ptr;
> + int err;
> +
> + /* Consider the frames with reserved multicast destination
> + * addresses matching 01:80:c2:00:00:00 and
> + * 01:80:c2:00:00:02 as MGMT.
> + */
> + ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO;
> + err = mv88e6393x_port_policy_write(chip, ptr, 0xff);
> + if (err)
> + return err;
> +
> + ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI;
> + err = mv88e6393x_port_policy_write(chip, ptr, 0xff);
> + if (err)
> + return err;
> +
> + ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO;
> + err = mv88e6393x_port_policy_write(chip, ptr, 0xff);
> + if (err)
> + return err;
> +
> + ptr = MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI;
> + err = mv88e6393x_port_policy_write(chip, ptr, 0xff);
> + if (err)
> + return err;
> +
> + return 0;
return mv...
> +}
> +
> + err = mv88e6xxx_port_write(chip, port, MV88E6393X_PORT_EPC_CMD, val);
> + if (err)
> + return err;
> +
> + return 0;
ditto
> +}
> +
> +int mv88e6393x_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
> + bool on)
> +{
> + if (port == 0 || port == 9 || port == 10) {
Flip the condition, return early. Entire body of a function should not
have to be indented.
> + u8 cmode = chip->ports[port].cmode;
> +
> + mv88e6393x_serdes_port_config(chip, lane, on);
> +
> + switch (cmode) {
> + case MV88E6XXX_PORT_STS_CMODE_1000BASEX:
> + case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
> + return mv88e6390_serdes_power_sgmii(chip, lane, on);
> + case MV88E6XXX_PORT_STS_CMODE_10GBASER:
> + return mv88e6390_serdes_power_10g(chip, lane, on);
> + }
> + }
> +
> + return 0;
> +}
> @@ -130,7 +169,7 @@ int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
> void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
>
> /* Return the (first) SERDES lane address a port is using, ERROR otherwise. */
> -static inline u8 mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip,
> +static inline int mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip,
> int port)
Looks like this should be in patch 3?
> {
> if (!chip->info->ops->serdes_get_lane)
next prev parent reply other threads:[~2020-11-06 1:52 UTC|newest]
Thread overview: 101+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <djc@djc.id.au; danc86@gmail.com[PATCH v2] Add support for mv88e6393x family of Marvell.>
2020-10-16 2:09 ` [PATCH v3] Add support for mv88e6393x family of Marvell Pavana Sharma
2020-10-16 2:37 ` Florian Fainelli
2020-10-17 19:30 ` Andrew Lunn
2020-10-26 5:52 ` [PATCH v4 0/3] " Pavana Sharma
2020-10-26 5:54 ` [PATCH v4 1/3] " Pavana Sharma
2020-10-26 8:58 ` kernel test robot
2020-10-27 19:10 ` kernel test robot
2020-10-26 5:58 ` [PATCH v4 2/3] Add phy interface for 5GBASER mode Pavana Sharma
2020-10-26 13:38 ` Andrew Lunn
2020-10-26 13:42 ` Florian Fainelli
2020-10-26 5:58 ` [PATCH v4 3/3] Change serdes lane parameter from u8 type to int Pavana Sharma
2020-10-26 13:43 ` [PATCH v4 0/3] Add support for mv88e6393x family of Marvell Florian Fainelli
2020-10-28 0:07 ` [PATCH v5 " Pavana Sharma
2020-10-28 0:08 ` [PATCH v5 1/3] net: phy: Add 5GBASER interface mode Pavana Sharma
2020-10-28 12:03 ` Andrew Lunn
2020-10-28 0:09 ` [PATCH v5 2/3] dt-bindings: net: Add 5GBASER phy " Pavana Sharma
2020-10-28 12:03 ` Andrew Lunn
2020-10-28 0:09 ` [PATCH v5 3/3] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-10-28 2:03 ` Marek Behun
2020-10-28 12:21 ` Andrew Lunn
2020-10-29 5:40 ` [PATCH v6 0/4] " Pavana Sharma
2020-10-29 5:41 ` [PATCH v6 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-10-29 5:42 ` [PATCH v6 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-10-29 6:11 ` Marek Behun
2020-10-29 12:42 ` Andrew Lunn
2020-10-29 5:42 ` [PATCH v6 3/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-10-29 6:31 ` Marek Behun
2020-11-02 6:40 ` [PATCH v7 0/4] " Pavana Sharma
2020-11-02 6:41 ` [PATCH v7 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-11-02 6:42 ` [PATCH v7 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-11-02 13:09 ` Andrew Lunn
2020-11-03 1:34 ` Pavana Sharma
2020-11-03 2:12 ` Florian Fainelli
2020-11-03 3:16 ` Andrew Lunn
2020-11-03 8:48 ` [PATCH v8 0/4] Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-03 8:49 ` [PATCH v8 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-11-06 1:42 ` Jakub Kicinski
2020-11-03 8:49 ` [PATCH v8 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-11-03 8:50 ` [PATCH v8 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 type to int Pavana Sharma
2020-11-06 1:40 ` Jakub Kicinski
2020-11-03 8:50 ` [PATCH v8 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-06 1:52 ` Jakub Kicinski [this message]
2020-11-19 8:01 ` [PATCH v9 0/4] " Pavana Sharma
2020-11-19 8:02 ` [PATCH v9 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-11-19 8:03 ` [PATCH v9 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-11-19 8:03 ` [PATCH v9 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 type to int Pavana Sharma
2020-11-19 8:04 ` [PATCH v9 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-19 15:33 ` kernel test robot
2020-11-19 19:12 ` kernel test robot
2020-11-20 0:24 ` [PATCH v10 0/4] " Pavana Sharma
2020-11-20 0:25 ` [PATCH v10 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-11-20 0:52 ` Andrew Lunn
2020-11-20 0:25 ` [PATCH v10 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-11-20 0:55 ` Andrew Lunn
2020-11-20 0:26 ` [PATCH v10 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 type to int Pavana Sharma
2020-11-20 0:59 ` Andrew Lunn
2020-11-20 0:26 ` [PATCH v10 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-20 1:29 ` Andrew Lunn
2020-11-20 1:43 ` Marek Behun
2020-11-20 1:54 ` Andrew Lunn
2020-12-09 5:02 ` [PATCH v11 0/4] " Pavana Sharma
2020-12-09 5:03 ` [PATCH v11 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-12-09 23:15 ` Andrew Lunn
2020-12-10 13:43 ` Pavana Sharma
2020-12-09 5:04 ` [PATCH v11 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-12-09 23:18 ` Andrew Lunn
2020-12-09 5:05 ` [PATCH v11 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter type from u8 type to int Pavana Sharma
2020-12-09 23:24 ` Andrew Lunn
2020-12-09 5:05 ` [PATCH v11 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-12-09 23:40 ` Andrew Lunn
2020-12-09 19:37 ` [PATCH v11 0/4] " Jakub Kicinski
2020-12-11 12:44 ` [net-next PATCH v12 " Pavana Sharma
2020-12-11 12:46 ` [net-next PATCH v12 1/4] dt-bindings: net: Add 5GBASER phy interface mode Pavana Sharma
2020-12-14 22:56 ` Rob Herring
2020-12-11 12:46 ` [net-next PATCH v12 2/4] net: phy: Add 5GBASER " Pavana Sharma
2020-12-11 12:49 ` [net-next PATCH v12 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter type from u8 type to int Pavana Sharma
2020-12-11 12:51 ` [net-next PATCH v12 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2021-01-05 12:15 ` Marek Behún
2021-01-06 0:45 ` Pavana Sharma
2021-01-06 12:20 ` Marek Behún
2021-01-05 12:37 ` patch fixing mv88e6393x SERDES IRQ for Pavana's series Marek Behún
2021-01-08 9:47 ` [net-next PATCH v13 0/4] Add support for mv88e6393x family of Marvell Pavana Sharma
2021-01-08 9:48 ` [net-next PATCH v13 1/4] dt-bindings: net: Add 5GBASER phy interface Pavana Sharma
2021-01-08 13:49 ` Andrew Lunn
2021-01-08 9:49 ` [net-next PATCH v13 2/4] net: phy: Add 5GBASER interface mode Pavana Sharma
2021-01-08 13:50 ` Andrew Lunn
2021-01-08 9:50 ` [net-next PATCH v13 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter type from u8 type to int Pavana Sharma
2021-01-08 9:50 ` [net-next PATCH v13 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2021-01-08 13:51 ` Marek Behún
2021-01-08 14:02 ` Marek Behún
2021-01-08 14:36 ` [PATCH] changes for Pavana Marek Behún
2021-01-09 21:31 ` Marek Behún
2020-11-02 6:43 ` [PATCH v7 3/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 type to int Pavana Sharma
2020-11-02 13:34 ` Andrew Lunn
2020-11-02 13:40 ` Andrew Lunn
2020-11-02 6:43 ` [PATCH v7 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Pavana Sharma
2020-11-02 13:12 ` [PATCH v7 0/4] " Andrew Lunn
2020-10-29 5:43 ` [PATCH v6 4/4] net: dsa: mv88e6xxx: Change serdes lane parameter from u8 to int Pavana Sharma
2020-10-29 6:07 ` [PATCH v6 0/4] Add support for mv88e6393x family of Marvell Marek Behun
2020-10-28 23:12 ` [PATCH v5 3/3] net: dsa: mv88e6xxx: " Jakub Kicinski
2020-10-29 4:25 ` kernel test robot
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