* [PATCH net] net: ipa: fix inter-EE IRQ register definitions
@ 2021-05-05 22:36 Alex Elder
2021-05-07 0:03 ` Jakub Kicinski
0 siblings, 1 reply; 2+ messages in thread
From: Alex Elder @ 2021-05-05 22:36 UTC (permalink / raw)
To: davem, kuba
Cc: bjorn.andersson, evgreen, cpratapa, subashab, elder, netdev,
linux-kernel
In gsi_irq_setup(), two registers are written with the intention of
disabling inter-EE channel and event IRQs.
But the wrong registers are used (and defined); the ones used are
read-only registers that indicate whether the interrupt condition is
present.
Define the mask registers instead of the status registers, and use
them to disable the inter-EE interrupt types.
Fixes: 46f748ccaf01 ("net: ipa: explicitly disallow inter-EE interrupts")
Signed-off-by: Alex Elder <elder@linaro.org>
---
drivers/net/ipa/gsi.c | 4 ++--
drivers/net/ipa/gsi_reg.h | 16 ++++++++--------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c
index 9f06663cef263..e374079603cf7 100644
--- a/drivers/net/ipa/gsi.c
+++ b/drivers/net/ipa/gsi.c
@@ -211,8 +211,8 @@ static void gsi_irq_setup(struct gsi *gsi)
iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET);
/* The inter-EE registers are in the non-adjusted address range */
- iowrite32(0, gsi->virt_raw + GSI_INTER_EE_SRC_CH_IRQ_OFFSET);
- iowrite32(0, gsi->virt_raw + GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET);
+ iowrite32(0, gsi->virt_raw + GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET);
+ iowrite32(0, gsi->virt_raw + GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET);
iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);
}
diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h
index b4ac0258d6e10..cb42c5ae86fa2 100644
--- a/drivers/net/ipa/gsi_reg.h
+++ b/drivers/net/ipa/gsi_reg.h
@@ -53,15 +53,15 @@
#define GSI_EE_REG_ADJUST 0x0000d000 /* IPA v4.5+ */
/* The two inter-EE IRQ register offsets are relative to gsi->virt_raw */
-#define GSI_INTER_EE_SRC_CH_IRQ_OFFSET \
- GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(GSI_EE_AP)
-#define GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(ee) \
- (0x0000c018 + 0x1000 * (ee))
+#define GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET \
+ GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
+#define GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(ee) \
+ (0x0000c020 + 0x1000 * (ee))
-#define GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET \
- GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP)
-#define GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(ee) \
- (0x0000c01c + 0x1000 * (ee))
+#define GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET \
+ GSI_INTER_EE_N_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP)
+#define GSI_INTER_EE_N_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \
+ (0x0000c024 + 0x1000 * (ee))
/* All other register offsets are relative to gsi->virt */
--
2.27.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH net] net: ipa: fix inter-EE IRQ register definitions
2021-05-05 22:36 [PATCH net] net: ipa: fix inter-EE IRQ register definitions Alex Elder
@ 2021-05-07 0:03 ` Jakub Kicinski
0 siblings, 0 replies; 2+ messages in thread
From: Jakub Kicinski @ 2021-05-07 0:03 UTC (permalink / raw)
To: Alex Elder
Cc: davem, bjorn.andersson, evgreen, cpratapa, subashab, elder,
netdev, linux-kernel
On Wed, 5 May 2021 17:36:36 -0500 Alex Elder wrote:
> In gsi_irq_setup(), two registers are written with the intention of
> disabling inter-EE channel and event IRQs.
>
> But the wrong registers are used (and defined); the ones used are
> read-only registers that indicate whether the interrupt condition is
> present.
>
> Define the mask registers instead of the status registers, and use
> them to disable the inter-EE interrupt types.
>
> Fixes: 46f748ccaf01 ("net: ipa: explicitly disallow inter-EE interrupts")
> Signed-off-by: Alex Elder <elder@linaro.org>
Applied, thanks!
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