* [PATCH net-next 0/2] Add 5gbase-r support for mvpp2
@ 2021-11-22 20:51 Marek Behún
2021-11-22 20:51 ` [PATCH net-next 1/2] phy: marvell: phy-mvebu-cp110-comphy: add support for 5gbase-r Marek Behún
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Marek Behún @ 2021-11-22 20:51 UTC (permalink / raw)
To: netdev; +Cc: Russell King, Jakub Kicinski, Andrew Lunn, davem, Marek Behún
Hello,
this adds support for 5gbase-r for mvpp2 driver. Current versions of
TF-A firmware support changing the PHY to 5gbase-r via SMC calls, at
least on Macchiatobin.
Tested on Macchiatobin.
Marek Behún (2):
phy: marvell: phy-mvebu-cp110-comphy: add support for 5gbase-r
net: marvell: mvpp2: Add support for 5gbase-r
.../net/ethernet/marvell/mvpp2/mvpp2_main.c | 44 ++++++++++++++++---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 9 ++++
2 files changed, 46 insertions(+), 7 deletions(-)
--
2.32.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH net-next 1/2] phy: marvell: phy-mvebu-cp110-comphy: add support for 5gbase-r
2021-11-22 20:51 [PATCH net-next 0/2] Add 5gbase-r support for mvpp2 Marek Behún
@ 2021-11-22 20:51 ` Marek Behún
2021-11-22 20:51 ` [PATCH net-next 2/2] net: marvell: mvpp2: Add " Marek Behún
2021-11-23 12:20 ` [PATCH net-next 0/2] Add 5gbase-r support for mvpp2 patchwork-bot+netdevbpf
2 siblings, 0 replies; 4+ messages in thread
From: Marek Behún @ 2021-11-22 20:51 UTC (permalink / raw)
To: netdev; +Cc: Russell King, Jakub Kicinski, Andrew Lunn, davem, Marek Behún
Add support for PHY_INTERFACE_MODE_5GBASER mode within the Marvell CP110
common PHY driver.
This is currently only supported via SMC calls to TF-A. Legacy support
may be added later, if needed.
Signed-off-by: Marek Behún <kabel@kernel.org>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index bbd6f2ad6f24..34672e868a1e 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -141,6 +141,7 @@
#define COMPHY_FW_SPEED_1250 0
#define COMPHY_FW_SPEED_3125 2
#define COMPHY_FW_SPEED_5000 3
+#define COMPHY_FW_SPEED_515625 4
#define COMPHY_FW_SPEED_103125 6
#define COMPHY_FW_PORT_OFFSET 8
#define COMPHY_FW_PORT_MASK GENMASK(11, 8)
@@ -220,6 +221,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
ETH_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_2500BASEX),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI),
+ ETH_CONF(2, 0, PHY_INTERFACE_MODE_5GBASER, 0x1, COMPHY_FW_MODE_XFI),
ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GBASER, 0x1, COMPHY_FW_MODE_XFI),
GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),
GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
@@ -234,6 +236,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
/* lane 4 */
ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_2500BASEX),
+ ETH_CONF(4, 0, PHY_INTERFACE_MODE_5GBASER, 0x2, COMPHY_FW_MODE_XFI),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GBASER, 0x2, COMPHY_FW_MODE_XFI),
ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
GEN_CONF(4, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
@@ -241,6 +244,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = {
GEN_CONF(4, 1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_2500BASEX),
+ ETH_CONF(4, 1, PHY_INTERFACE_MODE_5GBASER, -1, COMPHY_FW_MODE_XFI),
ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GBASER, -1, COMPHY_FW_MODE_XFI),
/* lane 5 */
ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
@@ -790,6 +794,11 @@ static int mvebu_comphy_power_on(struct phy *phy)
lane->id);
fw_speed = COMPHY_FW_SPEED_3125;
break;
+ case PHY_INTERFACE_MODE_5GBASER:
+ dev_dbg(priv->dev, "set lane %d to 5GBASE-R mode\n",
+ lane->id);
+ fw_speed = COMPHY_FW_SPEED_515625;
+ break;
case PHY_INTERFACE_MODE_10GBASER:
dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n",
lane->id);
--
2.32.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH net-next 2/2] net: marvell: mvpp2: Add support for 5gbase-r
2021-11-22 20:51 [PATCH net-next 0/2] Add 5gbase-r support for mvpp2 Marek Behún
2021-11-22 20:51 ` [PATCH net-next 1/2] phy: marvell: phy-mvebu-cp110-comphy: add support for 5gbase-r Marek Behún
@ 2021-11-22 20:51 ` Marek Behún
2021-11-23 12:20 ` [PATCH net-next 0/2] Add 5gbase-r support for mvpp2 patchwork-bot+netdevbpf
2 siblings, 0 replies; 4+ messages in thread
From: Marek Behún @ 2021-11-22 20:51 UTC (permalink / raw)
To: netdev; +Cc: Russell King, Jakub Kicinski, Andrew Lunn, davem, Marek Behún
Add support for PHY_INTERFACE_MODE_5GBASER.
Signed-off-by: Marek Behún <kabel@kernel.org>
---
.../net/ethernet/marvell/mvpp2/mvpp2_main.c | 44 ++++++++++++++++---
1 file changed, 37 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index a3aefdf0784e..a48e804c46f2 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -1488,6 +1488,7 @@ static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
static bool mvpp2_is_xlg(phy_interface_t interface)
{
return interface == PHY_INTERFACE_MODE_10GBASER ||
+ interface == PHY_INTERFACE_MODE_5GBASER ||
interface == PHY_INTERFACE_MODE_XAUI;
}
@@ -1627,6 +1628,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port, phy_interface_t interface)
case PHY_INTERFACE_MODE_2500BASEX:
mvpp22_gop_init_sgmii(port);
break;
+ case PHY_INTERFACE_MODE_5GBASER:
case PHY_INTERFACE_MODE_10GBASER:
if (!mvpp2_port_supports_xlg(port))
goto invalid_conf;
@@ -2186,6 +2188,7 @@ static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port,
xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
switch (interface) {
+ case PHY_INTERFACE_MODE_5GBASER:
case PHY_INTERFACE_MODE_10GBASER:
val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
@@ -6126,7 +6129,10 @@ static void mvpp2_xlg_pcs_get_state(struct phylink_pcs *pcs,
struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
u32 val;
- state->speed = SPEED_10000;
+ if (port->phy_interface == PHY_INTERFACE_MODE_5GBASER)
+ state->speed = SPEED_5000;
+ else
+ state->speed = SPEED_10000;
state->duplex = 1;
state->an_complete = 1;
@@ -6879,12 +6885,36 @@ static int mvpp2_port_probe(struct platform_device *pdev,
MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
if (mvpp2_port_supports_xlg(port)) {
- __set_bit(PHY_INTERFACE_MODE_10GBASER,
- port->phylink_config.supported_interfaces);
- __set_bit(PHY_INTERFACE_MODE_XAUI,
- port->phylink_config.supported_interfaces);
- port->phylink_config.mac_capabilities |=
- MAC_10000FD;
+ /* If a COMPHY is present, we can support any of
+ * the serdes modes and switch between them.
+ */
+ if (comphy) {
+ __set_bit(PHY_INTERFACE_MODE_5GBASER,
+ port->phylink_config.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
+ port->phylink_config.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_XAUI,
+ port->phylink_config.supported_interfaces);
+ } else if (phy_mode == PHY_INTERFACE_MODE_5GBASER) {
+ __set_bit(PHY_INTERFACE_MODE_5GBASER,
+ port->phylink_config.supported_interfaces);
+ } else if (phy_mode == PHY_INTERFACE_MODE_10GBASER) {
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
+ port->phylink_config.supported_interfaces);
+ } else if (phy_mode == PHY_INTERFACE_MODE_XAUI) {
+ __set_bit(PHY_INTERFACE_MODE_XAUI,
+ port->phylink_config.supported_interfaces);
+ }
+
+ if (comphy)
+ port->phylink_config.mac_capabilities |=
+ MAC_10000FD | MAC_5000FD;
+ else if (phy_mode == PHY_INTERFACE_MODE_5GBASER)
+ port->phylink_config.mac_capabilities |=
+ MAC_5000FD;
+ else
+ port->phylink_config.mac_capabilities |=
+ MAC_10000FD;
}
if (mvpp2_port_supports_rgmii(port))
--
2.32.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH net-next 0/2] Add 5gbase-r support for mvpp2
2021-11-22 20:51 [PATCH net-next 0/2] Add 5gbase-r support for mvpp2 Marek Behún
2021-11-22 20:51 ` [PATCH net-next 1/2] phy: marvell: phy-mvebu-cp110-comphy: add support for 5gbase-r Marek Behún
2021-11-22 20:51 ` [PATCH net-next 2/2] net: marvell: mvpp2: Add " Marek Behún
@ 2021-11-23 12:20 ` patchwork-bot+netdevbpf
2 siblings, 0 replies; 4+ messages in thread
From: patchwork-bot+netdevbpf @ 2021-11-23 12:20 UTC (permalink / raw)
To: =?utf-8?q?Marek_Beh=C3=BAn_=3Ckabel=40kernel=2Eorg=3E?=
Cc: netdev, rmk+kernel, kuba, andrew, davem
Hello:
This series was applied to netdev/net-next.git (master)
by David S. Miller <davem@davemloft.net>:
On Mon, 22 Nov 2021 21:51:09 +0100 you wrote:
> Hello,
>
> this adds support for 5gbase-r for mvpp2 driver. Current versions of
> TF-A firmware support changing the PHY to 5gbase-r via SMC calls, at
> least on Macchiatobin.
>
> Tested on Macchiatobin.
>
> [...]
Here is the summary with links:
- [net-next,1/2] phy: marvell: phy-mvebu-cp110-comphy: add support for 5gbase-r
https://git.kernel.org/netdev/net-next/c/a1fb410a5751
- [net-next,2/2] net: marvell: mvpp2: Add support for 5gbase-r
https://git.kernel.org/netdev/net-next/c/4043ec701c43
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-11-23 12:20 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2021-11-22 20:51 [PATCH net-next 0/2] Add 5gbase-r support for mvpp2 Marek Behún
2021-11-22 20:51 ` [PATCH net-next 1/2] phy: marvell: phy-mvebu-cp110-comphy: add support for 5gbase-r Marek Behún
2021-11-22 20:51 ` [PATCH net-next 2/2] net: marvell: mvpp2: Add " Marek Behún
2021-11-23 12:20 ` [PATCH net-next 0/2] Add 5gbase-r support for mvpp2 patchwork-bot+netdevbpf
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