* commit 65ac79e181 breaks our ksz9567
@ 2022-08-18 11:03 Rasmus Villemoes
2022-08-18 11:28 ` Alvin Šipraga
2022-08-18 11:34 ` Vladimir Oltean
0 siblings, 2 replies; 4+ messages in thread
From: Rasmus Villemoes @ 2022-08-18 11:03 UTC (permalink / raw)
To: Network Development
Cc: Arun Ramadoss, Vladimir Oltean, Florian Fainelli, David S. Miller
We have a board in development which includes a ksz9567 switch, whose
cpu port is connected to a lan7801 usb chip. This works fine up until
5.18, but is broken in 5.19. The kernel log contains
ksz9477-switch 4-005f lan1 (uninitialized): validation of gmii with
support 00000000,00000000,000062ff and advertisement
00000000,00000000,000062ff failed: -EINVAL
ksz9477-switch 4-005f lan1 (uninitialized): failed to connect to PHY:
-EINVAL
ksz9477-switch 4-005f lan1 (uninitialized): error -22 setting up PHY
for tree 0, switch 0, port 0
and similar lines for the other four ports.
Bisecting points at
commit 65ac79e1812016d7c5760872736802f985ec7455
Author: Arun Ramadoss <arun.ramadoss@microchip.com>
Date: Tue May 17 15:13:32 2022 +0530
net: dsa: microchip: add the phylink get_caps
Our DT is, I think, pretty standard, and as I said works fine with 5.18:
ksz9567: switch@5f {
compatible = "microchip,ksz9567";
reg = <0x5f>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
....
port@6 {
reg = <6>;
label = "cpu";
ethernet = <ðernet3>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
...
ethernet3: ethernet@2 {
compatible = "usb424,7801";
reg = <2>;
phy-mode = "rgmii-id";
mdio {
compatible = "lan78xx-mdiobus";
#address-cells = <1>;
#size-cells = <0>;
};
fixed-link {
speed = <1000>;
full-duplex;
};
};
Any clues?
Thanks,
Rasmus
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: commit 65ac79e181 breaks our ksz9567
2022-08-18 11:03 commit 65ac79e181 breaks our ksz9567 Rasmus Villemoes
@ 2022-08-18 11:28 ` Alvin Šipraga
2022-08-18 11:31 ` Vladimir Oltean
2022-08-18 11:34 ` Vladimir Oltean
1 sibling, 1 reply; 4+ messages in thread
From: Alvin Šipraga @ 2022-08-18 11:28 UTC (permalink / raw)
To: Rasmus Villemoes
Cc: Network Development, Arun Ramadoss, Vladimir Oltean,
Florian Fainelli, David S. Miller
Hi Rasmus,
On Thu, Aug 18, 2022 at 01:03:13PM +0200, Rasmus Villemoes wrote:
> We have a board in development which includes a ksz9567 switch, whose
> cpu port is connected to a lan7801 usb chip. This works fine up until
> 5.18, but is broken in 5.19. The kernel log contains
>
> ksz9477-switch 4-005f lan1 (uninitialized): validation of gmii with
> support 00000000,00000000,000062ff and advertisement
> 00000000,00000000,000062ff failed: -EINVAL
> ksz9477-switch 4-005f lan1 (uninitialized): failed to connect to PHY:
> -EINVAL
> ksz9477-switch 4-005f lan1 (uninitialized): error -22 setting up PHY
> for tree 0, switch 0, port 0
>
> and similar lines for the other four ports.
I think this is because the phylink_get_caps callback does not set
PHY_INTERFACE_MODE_GMII for ports with integrated PHY, which is the
default interface mode for phylib.
You can try this and see if it works (not even compile tested):
---
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 92a500e1ccd2..0d8044f2bd38 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -453,9 +453,16 @@ void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
if (dev->info->supports_rgmii[port])
phy_interface_set_rgmii(config->supported_interfaces);
- if (dev->info->internal_phy[port])
+ if (dev->info->internal_phy[port]) {
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
config->supported_interfaces);
+
+ /* GMII is the default interface mode for phylib, so
+ * we have to support it for ports with integrated PHY.
+ */
+ __set_bit(PHY_INTERFACE_MODE_GMII,
+ config->supported_interfaces);
+ }
}
EXPORT_SYMBOL_GPL(ksz_phylink_get_caps);
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: commit 65ac79e181 breaks our ksz9567
2022-08-18 11:28 ` Alvin Šipraga
@ 2022-08-18 11:31 ` Vladimir Oltean
0 siblings, 0 replies; 4+ messages in thread
From: Vladimir Oltean @ 2022-08-18 11:31 UTC (permalink / raw)
To: Alvin Šipraga
Cc: Rasmus Villemoes, Network Development, Arun Ramadoss,
Florian Fainelli, David S. Miller
On Thu, Aug 18, 2022 at 11:28:46AM +0000, Alvin Šipraga wrote:
> Hi Rasmus,
>
> On Thu, Aug 18, 2022 at 01:03:13PM +0200, Rasmus Villemoes wrote:
> > We have a board in development which includes a ksz9567 switch, whose
> > cpu port is connected to a lan7801 usb chip. This works fine up until
> > 5.18, but is broken in 5.19. The kernel log contains
> >
> > ksz9477-switch 4-005f lan1 (uninitialized): validation of gmii with
> > support 00000000,00000000,000062ff and advertisement
> > 00000000,00000000,000062ff failed: -EINVAL
> > ksz9477-switch 4-005f lan1 (uninitialized): failed to connect to PHY:
> > -EINVAL
> > ksz9477-switch 4-005f lan1 (uninitialized): error -22 setting up PHY
> > for tree 0, switch 0, port 0
> >
> > and similar lines for the other four ports.
>
> I think this is because the phylink_get_caps callback does not set
> PHY_INTERFACE_MODE_GMII for ports with integrated PHY, which is the
> default interface mode for phylib.
>
> You can try this and see if it works (not even compile tested):
>
> ---
> diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
> index 92a500e1ccd2..0d8044f2bd38 100644
> --- a/drivers/net/dsa/microchip/ksz_common.c
> +++ b/drivers/net/dsa/microchip/ksz_common.c
> @@ -453,9 +453,16 @@ void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
> if (dev->info->supports_rgmii[port])
> phy_interface_set_rgmii(config->supported_interfaces);
>
> - if (dev->info->internal_phy[port])
> + if (dev->info->internal_phy[port]) {
> __set_bit(PHY_INTERFACE_MODE_INTERNAL,
> config->supported_interfaces);
> +
> + /* GMII is the default interface mode for phylib, so
> + * we have to support it for ports with integrated PHY.
> + */
> + __set_bit(PHY_INTERFACE_MODE_GMII,
> + config->supported_interfaces);
> + }
> }
> EXPORT_SYMBOL_GPL(ksz_phylink_get_caps);
What a strange coincidence, yesterday we got the exact same bug report but for KSZ8:
https://lore.kernel.org/netdev/967ef480-2fac-9724-61c7-2d5e69c26ec3@leemhuis.info/
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: commit 65ac79e181 breaks our ksz9567
2022-08-18 11:03 commit 65ac79e181 breaks our ksz9567 Rasmus Villemoes
2022-08-18 11:28 ` Alvin Šipraga
@ 2022-08-18 11:34 ` Vladimir Oltean
1 sibling, 0 replies; 4+ messages in thread
From: Vladimir Oltean @ 2022-08-18 11:34 UTC (permalink / raw)
To: Rasmus Villemoes
Cc: Network Development, Arun Ramadoss, Florian Fainelli, David S. Miller
On Thu, Aug 18, 2022 at 01:03:13PM +0200, Rasmus Villemoes wrote:
> We have a board in development which includes a ksz9567 switch, whose
> cpu port is connected to a lan7801 usb chip. This works fine up until
> 5.18, but is broken in 5.19. The kernel log contains
>
> ksz9477-switch 4-005f lan1 (uninitialized): validation of gmii with
> support 00000000,00000000,000062ff and advertisement
> 00000000,00000000,000062ff failed: -EINVAL
> ksz9477-switch 4-005f lan1 (uninitialized): failed to connect to PHY: -EINVAL
> ksz9477-switch 4-005f lan1 (uninitialized): error -22 setting up PHY for tree 0, switch 0, port 0
>
> and similar lines for the other four ports.
>
> Bisecting points at
>
> commit 65ac79e1812016d7c5760872736802f985ec7455
> Author: Arun Ramadoss <arun.ramadoss@microchip.com>
> Date: Tue May 17 15:13:32 2022 +0530
>
> net: dsa: microchip: add the phylink get_caps
>
> Our DT is, I think, pretty standard, and as I said works fine with 5.18:
Depends on what you mean by "pretty standard", see this change set which
I'll resubmit soon (today):
https://patchwork.kernel.org/project/netdevbpf/cover/20220806141059.2498226-1-vladimir.oltean@nxp.com/
>
> ksz9567: switch@5f {
> compatible = "microchip,ksz9567";
> reg = <0x5f>;
> status = "okay";
>
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> port@0 {
> reg = <0>;
> label = "lan1";
> };
> ....
> port@6 {
> reg = <6>;
> label = "cpu";
> ethernet = <ðernet3>;
> fixed-link {
> speed = <1000>;
> full-duplex;
> };
The CPU port has no phy-mode. Good luck figuring out it's an RGMII mode.
(not related to the reported breakage though, which complains about
missing phy-mode on the LAN ports)
> };
> };
>
> ...
> ethernet3: ethernet@2 {
> compatible = "usb424,7801";
> reg = <2>;
> phy-mode = "rgmii-id";
>
> mdio {
> compatible = "lan78xx-mdiobus";
> #address-cells = <1>;
> #size-cells = <0>;
> };
>
> fixed-link {
> speed = <1000>;
> full-duplex;
> };
> };
>
> Any clues?
>
> Thanks,
> Rasmus
^ permalink raw reply [flat|nested] 4+ messages in thread
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2022-08-18 11:03 commit 65ac79e181 breaks our ksz9567 Rasmus Villemoes
2022-08-18 11:28 ` Alvin Šipraga
2022-08-18 11:31 ` Vladimir Oltean
2022-08-18 11:34 ` Vladimir Oltean
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