Re: [PATCH v5 net-next 14/17] net/sched: taprio: only calculate gate mask per TXQ for igc, stmmac and tsnep

From: Vladimir Oltean <vladimir.oltean@nxp.com>
To: Roger Quadros <rogerq@kernel.org>
Cc: netdev@vger.kernel.org, Pekka Varis <p-varis@ti.com>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Claudiu Manoil <claudiu.manoil@nxp.com>,
	Vinicius Costa Gomes <vinicius.gomes@intel.com>,
	Kurt Kanzenbach <kurt@linutronix.de>,
	Jacob Keller <jacob.e.keller@intel.com>,
	Jamal Hadi Salim <jhs@mojatatu.com>,
	Cong Wang <xiyou.wangcong@gmail.com>,
	Jiri Pirko <jiri@resnulli.us>,
	Simon Horman <simon.horman@corigine.com>,
	Horatiu Vultur <horatiu.vultur@microchip.com>,
	Siddharth Vadapalli <s-vadapalli@ti.com>,
	Gerhard Engleder <gerhard@engleder-embedded.com>
Subject: Re: [PATCH v5 net-next 14/17] net/sched: taprio: only calculate gate mask per TXQ for igc, stmmac and tsnep
Date: Thu, 2 Feb 2023 14:31:46 +0200	[thread overview]
Message-ID: <20230202123146.paegzm3rwi3ithmy@skbuf> (raw)
In-Reply-To: <8fb9048b-059c-f965-8cfc-e5fd480481b8@kernel.org> <8fb9048b-059c-f965-8cfc-e5fd480481b8@kernel.org>

Hi Roger,

On Thu, Feb 02, 2023 at 10:04:53AM +0200, Roger Quadros wrote:
> Here is some documentation for this driver with usage example
> https://software-dl.ti.com/processor-sdk-linux/esd/AM65X/08_02_00_02/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/CPSW2g.html#enhancements-for-scheduled-traffic-est-offload
> 
> It looks like it is suggesting to create a TXQ for each TC?
> I'm not sure if this patch will break that usage example. 

It won't break that example, because there is only one TXQ per TC,
and the TXQ indices are exactly equal to the TC indices.

#Where num_tc is same as number of queues = 3, map, maps 16 priorities to one of 3 TCs, queues specify the
#Queue associated with each TC, TC0 - One queue @0, TC1 - One queue @1 and TC2 - One queue @2
tc qdisc replace dev eth0 parent root handle 100 taprio \
   num_tc 3 \
   map 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 \
   queues 1@0 1@1 1@2 \
   base-time 0000 \
   sched-entry S 4 125000 \
   sched-entry S 2 125000 \
   sched-entry S 1 250000 \
   flags 2

The question is if the driver works in fact with other queue configurations than that.
If it doesn't, then this patch set could serve as a good first step for
the driver to receive the mqprio queue configuration, and NACK invalid
TC:TXQ mappings.

> Here is explanation of fetch_allow register from TRM [1] 12.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
> 
> "When a fetch allow bit is set, the corresponding priority is enabled to begin packet transmission on an
> allowed priority subject to rate limiting. The actual packet transmission on the wire may carry over into the
> next fetch count and is the reason for the wire clear time in the fetch zero allow.
> When a fetch allow bit is cleared, the corresponding priority is not enabled to transmit for the fetch count time."
> 
> I can try to do some tests and confirm if it still works in a few days.

If you prefer, I can respin the patch set, with am65-cpsw kept with a
gate mask per TXQ, and you can look into it when it's most convenient to you.