* [PATCH net-next v7 2/5] ptp: clockmatrix: set write phase timer to 0 when not in PCW mode [not found] <20240104163641.15893-1-lnimi@hotmail.com> @ 2024-01-04 16:36 ` Min Li 2024-01-04 16:36 ` [PATCH net-next v7 3/5] ptp: clockmatrix: dco input-to-output delay is 20 FOD cycles + 8ns Min Li ` (2 subsequent siblings) 3 siblings, 0 replies; 11+ messages in thread From: Min Li @ 2024-01-04 16:36 UTC (permalink / raw) To: richardcochran, lee; +Cc: linux-kernel, netdev, Min Li From: Min Li <min.li.xe@renesas.com> In order for phase pull-in to work, write phase timer shall be 0 when not in write phase mode. Also Fix u8 -> u16, DPLL_WF_TIMER and DPLL_WP_TIMER are 2-byte registers Signed-off-by: Min Li <min.li.xe@renesas.com> --- drivers/ptp/ptp_clockmatrix.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c index f8556627befa..d069b6e451ef 100644 --- a/drivers/ptp/ptp_clockmatrix.c +++ b/drivers/ptp/ptp_clockmatrix.c @@ -1396,6 +1396,20 @@ static int idtcm_set_pll_mode(struct idtcm_channel *channel, struct idtcm *idtcm = channel->idtcm; int err; u8 dpll_mode; + u8 buf[2] = {0}; + + /* Setup WF/WP timer for phase pull-in to work correctly */ + err = idtcm_write(idtcm, channel->dpll_n, DPLL_WF_TIMER, + buf, sizeof(buf)); + if (err) + return err; + + if (mode == PLL_MODE_WRITE_PHASE) + buf[0] = 160; + err = idtcm_write(idtcm, channel->dpll_n, DPLL_WP_TIMER, + buf, sizeof(buf)); + if (err) + return err; err = idtcm_read(idtcm, channel->dpll_n, IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE), -- 2.39.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH net-next v7 3/5] ptp: clockmatrix: dco input-to-output delay is 20 FOD cycles + 8ns [not found] <20240104163641.15893-1-lnimi@hotmail.com> 2024-01-04 16:36 ` [PATCH net-next v7 2/5] ptp: clockmatrix: set write phase timer to 0 when not in PCW mode Min Li @ 2024-01-04 16:36 ` Min Li 2024-01-04 16:36 ` [PATCH net-next v7 4/5] ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO] Min Li 2024-01-04 16:36 ` [PATCH net-next v7 5/5] ptp: clockmatrix: move register and firmware related definition to idt8a340_reg.h Min Li 3 siblings, 0 replies; 11+ messages in thread From: Min Li @ 2024-01-04 16:36 UTC (permalink / raw) To: richardcochran, lee; +Cc: linux-kernel, netdev, Min Li From: Min Li <min.li.xe@renesas.com> Set dco input-to-output delay is 20 FOD cycles + 8ns Signed-off-by: Min Li <min.li.xe@renesas.com> --- drivers/ptp/ptp_clockmatrix.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c index d069b6e451ef..21f3a2c179f5 100644 --- a/drivers/ptp/ptp_clockmatrix.c +++ b/drivers/ptp/ptp_clockmatrix.c @@ -2165,7 +2165,7 @@ static int configure_channel_pll(struct idtcm_channel *channel) /* * Compensate for the PTP DCO input-to-output delay. - * This delay is 18 FOD cycles. + * This delay is 20 FOD cycles + 8ns. */ static u32 idtcm_get_dco_delay(struct idtcm_channel *channel) { @@ -2196,7 +2196,7 @@ static u32 idtcm_get_dco_delay(struct idtcm_channel *channel) fodFreq = (u32)div_u64(m, n); if (fodFreq >= 500000000) - return (u32)div_u64(18 * (u64)NSEC_PER_SEC, fodFreq); + return (u32)div_u64(20 * (u64)NSEC_PER_SEC, fodFreq) + 8; return 0; } -- 2.39.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH net-next v7 4/5] ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO] [not found] <20240104163641.15893-1-lnimi@hotmail.com> 2024-01-04 16:36 ` [PATCH net-next v7 2/5] ptp: clockmatrix: set write phase timer to 0 when not in PCW mode Min Li 2024-01-04 16:36 ` [PATCH net-next v7 3/5] ptp: clockmatrix: dco input-to-output delay is 20 FOD cycles + 8ns Min Li @ 2024-01-04 16:36 ` Min Li 2024-01-11 10:47 ` Lee Jones 2024-01-04 16:36 ` [PATCH net-next v7 5/5] ptp: clockmatrix: move register and firmware related definition to idt8a340_reg.h Min Li 3 siblings, 1 reply; 11+ messages in thread From: Min Li @ 2024-01-04 16:36 UTC (permalink / raw) To: richardcochran, lee; +Cc: linux-kernel, netdev, Min Li From: Min Li <min.li.xe@renesas.com> Query MAX_FREQ_OFFSET register to set the proper limit. Signed-off-by: Min Li <min.li.xe@renesas.com> --- drivers/ptp/ptp_clockmatrix.c | 43 +++++++++++++++++++++++++------- drivers/ptp/ptp_clockmatrix.h | 1 + include/linux/mfd/idt8a340_reg.h | 1 + 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c index 21f3a2c179f5..cd7b3110f8e4 100644 --- a/drivers/ptp/ptp_clockmatrix.c +++ b/drivers/ptp/ptp_clockmatrix.c @@ -1038,7 +1038,7 @@ static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta) s64 now; if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) { - err = channel->do_phase_pull_in(channel, delta, 0); + err = channel->do_phase_pull_in(channel, delta, channel->caps.max_adj); } else { idtcm->calculate_overhead_flag = 1; @@ -1594,7 +1594,7 @@ static int do_phase_pull_in_sw(struct idtcm_channel *channel, if (abs(delta_ns) < PHASE_PULL_IN_MIN_THRESHOLD_NS) return 0; - if (max_ffo_ppb == 0) + if (max_ffo_ppb == 0 || max_ffo_ppb > PHASE_PULL_IN_MAX_PPB) max_ffo_ppb = PHASE_PULL_IN_MAX_PPB; /* For most cases, keep phase pull-in duration 1 second */ @@ -1880,7 +1880,7 @@ static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta) mutex_lock(idtcm->lock); if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) { - err = channel->do_phase_pull_in(channel, delta, 0); + err = channel->do_phase_pull_in(channel, delta, channel->caps.max_adj); } else { if (delta >= 0) { ts = ns_to_timespec64(delta); @@ -1927,9 +1927,6 @@ static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) if (channel->phase_pull_in == true) return 0; - if (scaled_ppm == channel->current_freq_scaled_ppm) - return 0; - mutex_lock(idtcm->lock); err = _idtcm_adjfine(channel, scaled_ppm); mutex_unlock(idtcm->lock); @@ -2054,7 +2051,7 @@ static struct ptp_pin_desc pin_config[MAX_TOD][MAX_REF_CLK]; static const struct ptp_clock_info idtcm_caps = { .owner = THIS_MODULE, - .max_adj = 244000, + .max_adj = MAX_FFO_PPB, .n_per_out = 12, .n_ext_ts = MAX_TOD, .n_pins = MAX_REF_CLK, @@ -2071,7 +2068,7 @@ static const struct ptp_clock_info idtcm_caps = { static const struct ptp_clock_info idtcm_caps_deprecated = { .owner = THIS_MODULE, - .max_adj = 244000, + .max_adj = MAX_FFO_PPB, .n_per_out = 12, .n_ext_ts = MAX_TOD, .n_pins = MAX_REF_CLK, @@ -2242,6 +2239,25 @@ static int configure_channel_tod(struct idtcm_channel *channel, u32 index) return 0; } +static int initialize_max_adj(struct idtcm_channel *channel) +{ + struct idtcm *idtcm = channel->idtcm; + u8 ffo_ppm; + int err; + + err = idtcm_read(idtcm, channel->dpll_n, DPLL_MAX_FREQ_OFFSET, + &ffo_ppm, sizeof(ffo_ppm)); + if (err) + return err; + + if (ffo_ppm && ffo_ppm <= (MAX_FFO_PPB / 1000)) + channel->caps.max_adj = ffo_ppm * 1000; + else + channel->caps.max_adj = MAX_FFO_PPB; + + return 0; +} + static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) { struct idtcm_channel *channel; @@ -2285,6 +2301,10 @@ static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) ppd->chan = index; } + err = initialize_max_adj(channel); + if (err) + return err; + err = initialize_dco_operating_mode(channel); if (err) return err; @@ -2437,8 +2457,13 @@ static int idtcm_probe(struct platform_device *pdev) err = idtcm_load_firmware(idtcm, &pdev->dev); - if (err) + if (err) { + if (err == -ENOENT) { + mutex_unlock(idtcm->lock); + return -EPROBE_DEFER; + } dev_warn(idtcm->dev, "loading firmware failed with %d", err); + } wait_for_chip_ready(idtcm); diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h index ad39dc6decdf..31d90b1bf025 100644 --- a/drivers/ptp/ptp_clockmatrix.h +++ b/drivers/ptp/ptp_clockmatrix.h @@ -19,6 +19,7 @@ #define MAX_REF_CLK (16) #define MAX_ABS_WRITE_PHASE_NANOSECONDS (107374182L) +#define MAX_FFO_PPB (244000) #define TOD_MASK_ADDR (0xFFA5) #define DEFAULT_TOD_MASK (0x04) diff --git a/include/linux/mfd/idt8a340_reg.h b/include/linux/mfd/idt8a340_reg.h index b680a0eb5f68..13b36f4858b3 100644 --- a/include/linux/mfd/idt8a340_reg.h +++ b/include/linux/mfd/idt8a340_reg.h @@ -192,6 +192,7 @@ #define DPLL_CTRL_REG_0 0x0002 #define DPLL_CTRL_REG_1 0x0003 #define DPLL_CTRL_REG_2 0x0004 +#define DPLL_MAX_FREQ_OFFSET 0x0025 #define DPLL_WF_TIMER 0x002c #define DPLL_WP_TIMER 0x002e #define DPLL_TOD_SYNC_CFG 0x0031 -- 2.39.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH net-next v7 4/5] ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO] 2024-01-04 16:36 ` [PATCH net-next v7 4/5] ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO] Min Li @ 2024-01-11 10:47 ` Lee Jones 0 siblings, 0 replies; 11+ messages in thread From: Lee Jones @ 2024-01-11 10:47 UTC (permalink / raw) To: Min Li; +Cc: richardcochran, linux-kernel, netdev, Min Li On Thu, 04 Jan 2024, Min Li wrote: > From: Min Li <min.li.xe@renesas.com> > > Query MAX_FREQ_OFFSET register to set the proper limit. > > Signed-off-by: Min Li <min.li.xe@renesas.com> > --- > drivers/ptp/ptp_clockmatrix.c | 43 +++++++++++++++++++++++++------- > drivers/ptp/ptp_clockmatrix.h | 1 + > include/linux/mfd/idt8a340_reg.h | 1 + Acked-by: Lee Jones <lee@kernel.org> > 3 files changed, 36 insertions(+), 9 deletions(-) [...] -- Lee Jones [李琼斯] ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH net-next v7 5/5] ptp: clockmatrix: move register and firmware related definition to idt8a340_reg.h [not found] <20240104163641.15893-1-lnimi@hotmail.com> ` (2 preceding siblings ...) 2024-01-04 16:36 ` [PATCH net-next v7 4/5] ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO] Min Li @ 2024-01-04 16:36 ` Min Li 2024-01-11 10:48 ` Lee Jones 3 siblings, 1 reply; 11+ messages in thread From: Min Li @ 2024-01-04 16:36 UTC (permalink / raw) To: richardcochran, lee; +Cc: linux-kernel, netdev, Min Li From: Min Li <min.li.xe@renesas.com> This change is needed by rsmu driver, which will be submitted separately from mfd tree. Signed-off-by: Min Li <min.li.xe@renesas.com> --- drivers/ptp/ptp_clockmatrix.h | 33 --------- include/linux/mfd/idt8a340_reg.h | 121 +++++++++++++++++++++++++++++-- 2 files changed, 113 insertions(+), 41 deletions(-) diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h index 31d90b1bf025..f041c7999ddc 100644 --- a/drivers/ptp/ptp_clockmatrix.h +++ b/drivers/ptp/ptp_clockmatrix.h @@ -21,32 +21,6 @@ #define MAX_ABS_WRITE_PHASE_NANOSECONDS (107374182L) #define MAX_FFO_PPB (244000) -#define TOD_MASK_ADDR (0xFFA5) -#define DEFAULT_TOD_MASK (0x04) - -#define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8)) -#define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8)) - -#define TOD0_PTP_PLL_ADDR (0xFFA8) -#define TOD1_PTP_PLL_ADDR (0xFFA9) -#define TOD2_PTP_PLL_ADDR (0xFFAA) -#define TOD3_PTP_PLL_ADDR (0xFFAB) - -#define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0) -#define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2) -#define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4) -#define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6) - -#define DEFAULT_OUTPUT_MASK_PLL0 (0x003) -#define DEFAULT_OUTPUT_MASK_PLL1 (0x00c) -#define DEFAULT_OUTPUT_MASK_PLL2 (0x030) -#define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0) - -#define DEFAULT_TOD0_PTP_PLL (0) -#define DEFAULT_TOD1_PTP_PLL (1) -#define DEFAULT_TOD2_PTP_PLL (2) -#define DEFAULT_TOD3_PTP_PLL (3) - #define PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED (150000) #define PHASE_PULL_IN_THRESHOLD_NS (15000) #define TOD_WRITE_OVERHEAD_COUNT_MAX (2) @@ -121,11 +95,4 @@ struct idtcm { ktime_t start_time; }; -struct idtcm_fwrc { - u8 hiaddr; - u8 loaddr; - u8 value; - u8 reserved; -} __packed; - #endif /* PTP_IDTCLOCKMATRIX_H */ diff --git a/include/linux/mfd/idt8a340_reg.h b/include/linux/mfd/idt8a340_reg.h index 13b36f4858b3..5aeb0820f876 100644 --- a/include/linux/mfd/idt8a340_reg.h +++ b/include/linux/mfd/idt8a340_reg.h @@ -116,16 +116,41 @@ #define OTP_SCSR_CONFIG_SELECT 0x0022 #define STATUS 0x2010c03c -#define DPLL0_STATUS 0x0018 -#define DPLL1_STATUS 0x0019 -#define DPLL2_STATUS 0x001a -#define DPLL3_STATUS 0x001b -#define DPLL4_STATUS 0x001c -#define DPLL5_STATUS 0x001d -#define DPLL6_STATUS 0x001e -#define DPLL7_STATUS 0x001f +#define IN0_MON_STATUS 0x0008 +#define IN1_MON_STATUS 0x0009 +#define IN2_MON_STATUS 0x000a +#define IN3_MON_STATUS 0x000b +#define IN4_MON_STATUS 0x000c +#define IN5_MON_STATUS 0x000d +#define IN6_MON_STATUS 0x000e +#define IN7_MON_STATUS 0x000f +#define IN8_MON_STATUS 0x0010 +#define IN9_MON_STATUS 0x0011 +#define IN10_MON_STATUS 0x0012 +#define IN11_MON_STATUS 0x0013 +#define IN12_MON_STATUS 0x0014 +#define IN13_MON_STATUS 0x0015 +#define IN14_MON_STATUS 0x0016 +#define IN15_MON_STATUS 0x0017 +#define DPLL0_STATUS 0x0018 +#define DPLL1_STATUS 0x0019 +#define DPLL2_STATUS 0x001a +#define DPLL3_STATUS 0x001b +#define DPLL4_STATUS 0x001c +#define DPLL5_STATUS 0x001d +#define DPLL6_STATUS 0x001e +#define DPLL7_STATUS 0x001f #define DPLL_SYS_STATUS 0x0020 #define DPLL_SYS_APLL_STATUS 0x0021 +#define DPLL0_REF_STATUS 0x0022 +#define DPLL1_REF_STATUS 0x0023 +#define DPLL2_REF_STATUS 0x0024 +#define DPLL3_REF_STATUS 0x0025 +#define DPLL4_REF_STATUS 0x0026 +#define DPLL5_REF_STATUS 0x0027 +#define DPLL6_REF_STATUS 0x0028 +#define DPLL7_REF_STATUS 0x0029 +#define DPLL_SYS_REF_STATUS 0x002a #define DPLL0_FILTER_STATUS 0x0044 #define DPLL1_FILTER_STATUS 0x004c #define DPLL2_FILTER_STATUS 0x0054 @@ -192,6 +217,25 @@ #define DPLL_CTRL_REG_0 0x0002 #define DPLL_CTRL_REG_1 0x0003 #define DPLL_CTRL_REG_2 0x0004 +#define DPLL_REF_PRIORITY_0 0x000f +#define DPLL_REF_PRIORITY_1 0x0010 +#define DPLL_REF_PRIORITY_2 0x0011 +#define DPLL_REF_PRIORITY_3 0x0012 +#define DPLL_REF_PRIORITY_4 0x0013 +#define DPLL_REF_PRIORITY_5 0x0014 +#define DPLL_REF_PRIORITY_6 0x0015 +#define DPLL_REF_PRIORITY_7 0x0016 +#define DPLL_REF_PRIORITY_8 0x0017 +#define DPLL_REF_PRIORITY_9 0x0018 +#define DPLL_REF_PRIORITY_10 0x0019 +#define DPLL_REF_PRIORITY_11 0x001a +#define DPLL_REF_PRIORITY_12 0x001b +#define DPLL_REF_PRIORITY_13 0x001c +#define DPLL_REF_PRIORITY_14 0x001d +#define DPLL_REF_PRIORITY_15 0x001e +#define DPLL_REF_PRIORITY_16 0x001f +#define DPLL_REF_PRIORITY_17 0x0020 +#define DPLL_REF_PRIORITY_18 0x0021 #define DPLL_MAX_FREQ_OFFSET 0x0025 #define DPLL_WF_TIMER 0x002c #define DPLL_WP_TIMER 0x002e @@ -450,6 +494,10 @@ #define OUTPUT_TDC_1 0x2010cd08 #define OUTPUT_TDC_2 0x2010cd10 #define OUTPUT_TDC_3 0x2010cd18 + +#define OUTPUT_TDC_CTRL_4 0x0006 +#define OUTPUT_TDC_CTRL_4_V520 0x0007 + #define INPUT_TDC 0x2010cd20 #define SCRATCH 0x2010cf50 @@ -668,6 +716,28 @@ #define DPLL_STATE_MASK (0xf) #define DPLL_STATE_SHIFT (0x0) +/* Bit definitions for the DPLL0_REF_STAT register */ +#define DPLL_REF_STATUS_MASK (0x1f) + +/* Bit definitions for the DPLL register */ +#define DPLL_REF_PRIORITY_ENABLE_SHIFT (0) +#define DPLL_REF_PRIORITY_REF_SHIFT (1) +#define DPLL_REF_PRIORITY_GROUP_NUMBER_SHIFT (6) + +/* Bit definitions for the IN0_MON_STATUS register */ +#define IN_MON_STATUS_LOS_SHIFT (0) +#define IN_MON_STATUS_NO_ACT_SHIFT (1) +#define IN_MON_STATUS_FFO_LIMIT_SHIFT (2) + +#define DEFAULT_PRIORITY_GROUP (0) +#define MAX_PRIORITY_GROUP (3) + +#define MAX_REF_PRIORITIES (19) + +#define MAX_ELECTRICAL_REFERENCES (16) + +#define NO_REFERENCE (0x1f) + /* * Return register address based on passed in firmware version */ @@ -778,4 +848,39 @@ enum scsr_tod_write_type_sel { SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2, SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS, }; + +/* firmware interface */ +struct idtcm_fwrc { + u8 hiaddr; + u8 loaddr; + u8 value; + u8 reserved; +} __packed; + +#define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8)) +#define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8)) + +#define TOD_MASK_ADDR (0xFFA5) +#define DEFAULT_TOD_MASK (0x04) + +#define TOD0_PTP_PLL_ADDR (0xFFA8) +#define TOD1_PTP_PLL_ADDR (0xFFA9) +#define TOD2_PTP_PLL_ADDR (0xFFAA) +#define TOD3_PTP_PLL_ADDR (0xFFAB) + +#define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0) +#define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2) +#define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4) +#define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6) + +#define DEFAULT_OUTPUT_MASK_PLL0 (0x003) +#define DEFAULT_OUTPUT_MASK_PLL1 (0x00c) +#define DEFAULT_OUTPUT_MASK_PLL2 (0x030) +#define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0) + +#define DEFAULT_TOD0_PTP_PLL (0) +#define DEFAULT_TOD1_PTP_PLL (1) +#define DEFAULT_TOD2_PTP_PLL (2) +#define DEFAULT_TOD3_PTP_PLL (3) + #endif -- 2.39.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH net-next v7 5/5] ptp: clockmatrix: move register and firmware related definition to idt8a340_reg.h 2024-01-04 16:36 ` [PATCH net-next v7 5/5] ptp: clockmatrix: move register and firmware related definition to idt8a340_reg.h Min Li @ 2024-01-11 10:48 ` Lee Jones 0 siblings, 0 replies; 11+ messages in thread From: Lee Jones @ 2024-01-11 10:48 UTC (permalink / raw) To: Min Li; +Cc: richardcochran, linux-kernel, netdev, Min Li On Thu, 04 Jan 2024, Min Li wrote: > From: Min Li <min.li.xe@renesas.com> > > This change is needed by rsmu driver, which will be submitted separately > from mfd tree. > > Signed-off-by: Min Li <min.li.xe@renesas.com> > --- > drivers/ptp/ptp_clockmatrix.h | 33 --------- > include/linux/mfd/idt8a340_reg.h | 121 +++++++++++++++++++++++++++++-- Acked-by: Lee Jones <lee@kernel.org> > 2 files changed, 113 insertions(+), 41 deletions(-) [...] -- Lee Jones [李琼斯] ^ permalink raw reply [flat|nested] 11+ messages in thread
[parent not found: <20240501160324.27514-1-lnimi@hotmail.com>]
* [PATCH net-next v7 4/5] ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO] [not found] <20240501160324.27514-1-lnimi@hotmail.com> @ 2024-05-01 16:03 ` Min Li 2024-05-02 6:54 ` Horatiu Vultur 0 siblings, 1 reply; 11+ messages in thread From: Min Li @ 2024-05-01 16:03 UTC (permalink / raw) To: richardcochran, lee; +Cc: linux-kernel, netdev, Min Li From: Min Li <min.li.xe@renesas.com> Query MAX_FREQ_OFFSET register to set the proper limit. Signed-off-by: Min Li <min.li.xe@renesas.com> --- drivers/ptp/ptp_clockmatrix.c | 43 +++++++++++++++++++++++++------- drivers/ptp/ptp_clockmatrix.h | 1 + include/linux/mfd/idt8a340_reg.h | 1 + 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c index 21f3a2c179f5..cd7b3110f8e4 100644 --- a/drivers/ptp/ptp_clockmatrix.c +++ b/drivers/ptp/ptp_clockmatrix.c @@ -1038,7 +1038,7 @@ static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta) s64 now; if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) { - err = channel->do_phase_pull_in(channel, delta, 0); + err = channel->do_phase_pull_in(channel, delta, channel->caps.max_adj); } else { idtcm->calculate_overhead_flag = 1; @@ -1594,7 +1594,7 @@ static int do_phase_pull_in_sw(struct idtcm_channel *channel, if (abs(delta_ns) < PHASE_PULL_IN_MIN_THRESHOLD_NS) return 0; - if (max_ffo_ppb == 0) + if (max_ffo_ppb == 0 || max_ffo_ppb > PHASE_PULL_IN_MAX_PPB) max_ffo_ppb = PHASE_PULL_IN_MAX_PPB; /* For most cases, keep phase pull-in duration 1 second */ @@ -1880,7 +1880,7 @@ static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta) mutex_lock(idtcm->lock); if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) { - err = channel->do_phase_pull_in(channel, delta, 0); + err = channel->do_phase_pull_in(channel, delta, channel->caps.max_adj); } else { if (delta >= 0) { ts = ns_to_timespec64(delta); @@ -1927,9 +1927,6 @@ static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) if (channel->phase_pull_in == true) return 0; - if (scaled_ppm == channel->current_freq_scaled_ppm) - return 0; - mutex_lock(idtcm->lock); err = _idtcm_adjfine(channel, scaled_ppm); mutex_unlock(idtcm->lock); @@ -2054,7 +2051,7 @@ static struct ptp_pin_desc pin_config[MAX_TOD][MAX_REF_CLK]; static const struct ptp_clock_info idtcm_caps = { .owner = THIS_MODULE, - .max_adj = 244000, + .max_adj = MAX_FFO_PPB, .n_per_out = 12, .n_ext_ts = MAX_TOD, .n_pins = MAX_REF_CLK, @@ -2071,7 +2068,7 @@ static const struct ptp_clock_info idtcm_caps = { static const struct ptp_clock_info idtcm_caps_deprecated = { .owner = THIS_MODULE, - .max_adj = 244000, + .max_adj = MAX_FFO_PPB, .n_per_out = 12, .n_ext_ts = MAX_TOD, .n_pins = MAX_REF_CLK, @@ -2242,6 +2239,25 @@ static int configure_channel_tod(struct idtcm_channel *channel, u32 index) return 0; } +static int initialize_max_adj(struct idtcm_channel *channel) +{ + struct idtcm *idtcm = channel->idtcm; + u8 ffo_ppm; + int err; + + err = idtcm_read(idtcm, channel->dpll_n, DPLL_MAX_FREQ_OFFSET, + &ffo_ppm, sizeof(ffo_ppm)); + if (err) + return err; + + if (ffo_ppm && ffo_ppm <= (MAX_FFO_PPB / 1000)) + channel->caps.max_adj = ffo_ppm * 1000; + else + channel->caps.max_adj = MAX_FFO_PPB; + + return 0; +} + static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) { struct idtcm_channel *channel; @@ -2285,6 +2301,10 @@ static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) ppd->chan = index; } + err = initialize_max_adj(channel); + if (err) + return err; + err = initialize_dco_operating_mode(channel); if (err) return err; @@ -2437,8 +2457,13 @@ static int idtcm_probe(struct platform_device *pdev) err = idtcm_load_firmware(idtcm, &pdev->dev); - if (err) + if (err) { + if (err == -ENOENT) { + mutex_unlock(idtcm->lock); + return -EPROBE_DEFER; + } dev_warn(idtcm->dev, "loading firmware failed with %d", err); + } wait_for_chip_ready(idtcm); diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h index ad39dc6decdf..31d90b1bf025 100644 --- a/drivers/ptp/ptp_clockmatrix.h +++ b/drivers/ptp/ptp_clockmatrix.h @@ -19,6 +19,7 @@ #define MAX_REF_CLK (16) #define MAX_ABS_WRITE_PHASE_NANOSECONDS (107374182L) +#define MAX_FFO_PPB (244000) #define TOD_MASK_ADDR (0xFFA5) #define DEFAULT_TOD_MASK (0x04) diff --git a/include/linux/mfd/idt8a340_reg.h b/include/linux/mfd/idt8a340_reg.h index b680a0eb5f68..13b36f4858b3 100644 --- a/include/linux/mfd/idt8a340_reg.h +++ b/include/linux/mfd/idt8a340_reg.h @@ -192,6 +192,7 @@ #define DPLL_CTRL_REG_0 0x0002 #define DPLL_CTRL_REG_1 0x0003 #define DPLL_CTRL_REG_2 0x0004 +#define DPLL_MAX_FREQ_OFFSET 0x0025 #define DPLL_WF_TIMER 0x002c #define DPLL_WP_TIMER 0x002e #define DPLL_TOD_SYNC_CFG 0x0031 -- 2.39.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH net-next v7 4/5] ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO] 2024-05-01 16:03 ` [PATCH net-next v7 4/5] ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO] Min Li @ 2024-05-02 6:54 ` Horatiu Vultur 0 siblings, 0 replies; 11+ messages in thread From: Horatiu Vultur @ 2024-05-02 6:54 UTC (permalink / raw) To: Min Li; +Cc: richardcochran, lee, linux-kernel, netdev, Min Li The 05/01/2024 12:03, Min Li wrote: Hi Min Li, Maybe the entire patch should target net instead of net-next. As this is fixing an issue. > @@ -2285,6 +2301,10 @@ static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) > ppd->chan = index; > } > > + err = initialize_max_adj(channel); > + if (err) > + return err; > + > err = initialize_dco_operating_mode(channel); > if (err) > return err; > @@ -2437,8 +2457,13 @@ static int idtcm_probe(struct platform_device *pdev) > > err = idtcm_load_firmware(idtcm, &pdev->dev); > > - if (err) > + if (err) { > + if (err == -ENOENT) { > + mutex_unlock(idtcm->lock); > + return -EPROBE_DEFER; > + } > dev_warn(idtcm->dev, "loading firmware failed with %d", err); > + } > > wait_for_chip_ready(idtcm); > Also this change should be in a separate patch as this doesn't have anything to do with caps.max_adj but it is releasing the lock in case firmware fails to be loaded. -- /Horatiu ^ permalink raw reply [flat|nested] 11+ messages in thread
[parent not found: <20240318173213.28475-1-lnimi@hotmail.com>]
* [PATCH net-next v7 4/5] ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO] [not found] <20240318173213.28475-1-lnimi@hotmail.com> @ 2024-03-18 17:32 ` Min Li 0 siblings, 0 replies; 11+ messages in thread From: Min Li @ 2024-03-18 17:32 UTC (permalink / raw) To: richardcochran, lee; +Cc: linux-kernel, netdev, Min Li From: Min Li <min.li.xe@renesas.com> Query MAX_FREQ_OFFSET register to set the proper limit. Signed-off-by: Min Li <min.li.xe@renesas.com> --- drivers/ptp/ptp_clockmatrix.c | 43 +++++++++++++++++++++++++------- drivers/ptp/ptp_clockmatrix.h | 1 + include/linux/mfd/idt8a340_reg.h | 1 + 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c index 21f3a2c179f5..cd7b3110f8e4 100644 --- a/drivers/ptp/ptp_clockmatrix.c +++ b/drivers/ptp/ptp_clockmatrix.c @@ -1038,7 +1038,7 @@ static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta) s64 now; if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) { - err = channel->do_phase_pull_in(channel, delta, 0); + err = channel->do_phase_pull_in(channel, delta, channel->caps.max_adj); } else { idtcm->calculate_overhead_flag = 1; @@ -1594,7 +1594,7 @@ static int do_phase_pull_in_sw(struct idtcm_channel *channel, if (abs(delta_ns) < PHASE_PULL_IN_MIN_THRESHOLD_NS) return 0; - if (max_ffo_ppb == 0) + if (max_ffo_ppb == 0 || max_ffo_ppb > PHASE_PULL_IN_MAX_PPB) max_ffo_ppb = PHASE_PULL_IN_MAX_PPB; /* For most cases, keep phase pull-in duration 1 second */ @@ -1880,7 +1880,7 @@ static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta) mutex_lock(idtcm->lock); if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) { - err = channel->do_phase_pull_in(channel, delta, 0); + err = channel->do_phase_pull_in(channel, delta, channel->caps.max_adj); } else { if (delta >= 0) { ts = ns_to_timespec64(delta); @@ -1927,9 +1927,6 @@ static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) if (channel->phase_pull_in == true) return 0; - if (scaled_ppm == channel->current_freq_scaled_ppm) - return 0; - mutex_lock(idtcm->lock); err = _idtcm_adjfine(channel, scaled_ppm); mutex_unlock(idtcm->lock); @@ -2054,7 +2051,7 @@ static struct ptp_pin_desc pin_config[MAX_TOD][MAX_REF_CLK]; static const struct ptp_clock_info idtcm_caps = { .owner = THIS_MODULE, - .max_adj = 244000, + .max_adj = MAX_FFO_PPB, .n_per_out = 12, .n_ext_ts = MAX_TOD, .n_pins = MAX_REF_CLK, @@ -2071,7 +2068,7 @@ static const struct ptp_clock_info idtcm_caps = { static const struct ptp_clock_info idtcm_caps_deprecated = { .owner = THIS_MODULE, - .max_adj = 244000, + .max_adj = MAX_FFO_PPB, .n_per_out = 12, .n_ext_ts = MAX_TOD, .n_pins = MAX_REF_CLK, @@ -2242,6 +2239,25 @@ static int configure_channel_tod(struct idtcm_channel *channel, u32 index) return 0; } +static int initialize_max_adj(struct idtcm_channel *channel) +{ + struct idtcm *idtcm = channel->idtcm; + u8 ffo_ppm; + int err; + + err = idtcm_read(idtcm, channel->dpll_n, DPLL_MAX_FREQ_OFFSET, + &ffo_ppm, sizeof(ffo_ppm)); + if (err) + return err; + + if (ffo_ppm && ffo_ppm <= (MAX_FFO_PPB / 1000)) + channel->caps.max_adj = ffo_ppm * 1000; + else + channel->caps.max_adj = MAX_FFO_PPB; + + return 0; +} + static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) { struct idtcm_channel *channel; @@ -2285,6 +2301,10 @@ static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) ppd->chan = index; } + err = initialize_max_adj(channel); + if (err) + return err; + err = initialize_dco_operating_mode(channel); if (err) return err; @@ -2437,8 +2457,13 @@ static int idtcm_probe(struct platform_device *pdev) err = idtcm_load_firmware(idtcm, &pdev->dev); - if (err) + if (err) { + if (err == -ENOENT) { + mutex_unlock(idtcm->lock); + return -EPROBE_DEFER; + } dev_warn(idtcm->dev, "loading firmware failed with %d", err); + } wait_for_chip_ready(idtcm); diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h index ad39dc6decdf..31d90b1bf025 100644 --- a/drivers/ptp/ptp_clockmatrix.h +++ b/drivers/ptp/ptp_clockmatrix.h @@ -19,6 +19,7 @@ #define MAX_REF_CLK (16) #define MAX_ABS_WRITE_PHASE_NANOSECONDS (107374182L) +#define MAX_FFO_PPB (244000) #define TOD_MASK_ADDR (0xFFA5) #define DEFAULT_TOD_MASK (0x04) diff --git a/include/linux/mfd/idt8a340_reg.h b/include/linux/mfd/idt8a340_reg.h index b680a0eb5f68..13b36f4858b3 100644 --- a/include/linux/mfd/idt8a340_reg.h +++ b/include/linux/mfd/idt8a340_reg.h @@ -192,6 +192,7 @@ #define DPLL_CTRL_REG_0 0x0002 #define DPLL_CTRL_REG_1 0x0003 #define DPLL_CTRL_REG_2 0x0004 +#define DPLL_MAX_FREQ_OFFSET 0x0025 #define DPLL_WF_TIMER 0x002c #define DPLL_WP_TIMER 0x002e #define DPLL_TOD_SYNC_CFG 0x0031 -- 2.39.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
[parent not found: <20240314153707.31551-1-lnimi@hotmail.com>]
* [PATCH net-next v7 4/5] ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO] [not found] <20240314153707.31551-1-lnimi@hotmail.com> @ 2024-03-14 15:37 ` Min Li 0 siblings, 0 replies; 11+ messages in thread From: Min Li @ 2024-03-14 15:37 UTC (permalink / raw) To: richardcochran, lee; +Cc: linux-kernel, netdev, Min Li From: Min Li <min.li.xe@renesas.com> Query MAX_FREQ_OFFSET register to set the proper limit. Signed-off-by: Min Li <min.li.xe@renesas.com> --- drivers/ptp/ptp_clockmatrix.c | 43 +++++++++++++++++++++++++------- drivers/ptp/ptp_clockmatrix.h | 1 + include/linux/mfd/idt8a340_reg.h | 1 + 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c index 21f3a2c179f5..cd7b3110f8e4 100644 --- a/drivers/ptp/ptp_clockmatrix.c +++ b/drivers/ptp/ptp_clockmatrix.c @@ -1038,7 +1038,7 @@ static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta) s64 now; if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) { - err = channel->do_phase_pull_in(channel, delta, 0); + err = channel->do_phase_pull_in(channel, delta, channel->caps.max_adj); } else { idtcm->calculate_overhead_flag = 1; @@ -1594,7 +1594,7 @@ static int do_phase_pull_in_sw(struct idtcm_channel *channel, if (abs(delta_ns) < PHASE_PULL_IN_MIN_THRESHOLD_NS) return 0; - if (max_ffo_ppb == 0) + if (max_ffo_ppb == 0 || max_ffo_ppb > PHASE_PULL_IN_MAX_PPB) max_ffo_ppb = PHASE_PULL_IN_MAX_PPB; /* For most cases, keep phase pull-in duration 1 second */ @@ -1880,7 +1880,7 @@ static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta) mutex_lock(idtcm->lock); if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) { - err = channel->do_phase_pull_in(channel, delta, 0); + err = channel->do_phase_pull_in(channel, delta, channel->caps.max_adj); } else { if (delta >= 0) { ts = ns_to_timespec64(delta); @@ -1927,9 +1927,6 @@ static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) if (channel->phase_pull_in == true) return 0; - if (scaled_ppm == channel->current_freq_scaled_ppm) - return 0; - mutex_lock(idtcm->lock); err = _idtcm_adjfine(channel, scaled_ppm); mutex_unlock(idtcm->lock); @@ -2054,7 +2051,7 @@ static struct ptp_pin_desc pin_config[MAX_TOD][MAX_REF_CLK]; static const struct ptp_clock_info idtcm_caps = { .owner = THIS_MODULE, - .max_adj = 244000, + .max_adj = MAX_FFO_PPB, .n_per_out = 12, .n_ext_ts = MAX_TOD, .n_pins = MAX_REF_CLK, @@ -2071,7 +2068,7 @@ static const struct ptp_clock_info idtcm_caps = { static const struct ptp_clock_info idtcm_caps_deprecated = { .owner = THIS_MODULE, - .max_adj = 244000, + .max_adj = MAX_FFO_PPB, .n_per_out = 12, .n_ext_ts = MAX_TOD, .n_pins = MAX_REF_CLK, @@ -2242,6 +2239,25 @@ static int configure_channel_tod(struct idtcm_channel *channel, u32 index) return 0; } +static int initialize_max_adj(struct idtcm_channel *channel) +{ + struct idtcm *idtcm = channel->idtcm; + u8 ffo_ppm; + int err; + + err = idtcm_read(idtcm, channel->dpll_n, DPLL_MAX_FREQ_OFFSET, + &ffo_ppm, sizeof(ffo_ppm)); + if (err) + return err; + + if (ffo_ppm && ffo_ppm <= (MAX_FFO_PPB / 1000)) + channel->caps.max_adj = ffo_ppm * 1000; + else + channel->caps.max_adj = MAX_FFO_PPB; + + return 0; +} + static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) { struct idtcm_channel *channel; @@ -2285,6 +2301,10 @@ static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) ppd->chan = index; } + err = initialize_max_adj(channel); + if (err) + return err; + err = initialize_dco_operating_mode(channel); if (err) return err; @@ -2437,8 +2457,13 @@ static int idtcm_probe(struct platform_device *pdev) err = idtcm_load_firmware(idtcm, &pdev->dev); - if (err) + if (err) { + if (err == -ENOENT) { + mutex_unlock(idtcm->lock); + return -EPROBE_DEFER; + } dev_warn(idtcm->dev, "loading firmware failed with %d", err); + } wait_for_chip_ready(idtcm); diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h index ad39dc6decdf..31d90b1bf025 100644 --- a/drivers/ptp/ptp_clockmatrix.h +++ b/drivers/ptp/ptp_clockmatrix.h @@ -19,6 +19,7 @@ #define MAX_REF_CLK (16) #define MAX_ABS_WRITE_PHASE_NANOSECONDS (107374182L) +#define MAX_FFO_PPB (244000) #define TOD_MASK_ADDR (0xFFA5) #define DEFAULT_TOD_MASK (0x04) diff --git a/include/linux/mfd/idt8a340_reg.h b/include/linux/mfd/idt8a340_reg.h index b680a0eb5f68..13b36f4858b3 100644 --- a/include/linux/mfd/idt8a340_reg.h +++ b/include/linux/mfd/idt8a340_reg.h @@ -192,6 +192,7 @@ #define DPLL_CTRL_REG_0 0x0002 #define DPLL_CTRL_REG_1 0x0003 #define DPLL_CTRL_REG_2 0x0004 +#define DPLL_MAX_FREQ_OFFSET 0x0025 #define DPLL_WF_TIMER 0x002c #define DPLL_WP_TIMER 0x002e #define DPLL_TOD_SYNC_CFG 0x0031 -- 2.39.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
[parent not found: <20231214152415.14785-1-lnimi@hotmail.com>]
* [PATCH net-next v7 4/5] ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO] [not found] <20231214152415.14785-1-lnimi@hotmail.com> @ 2023-12-14 15:24 ` Min Li 0 siblings, 0 replies; 11+ messages in thread From: Min Li @ 2023-12-14 15:24 UTC (permalink / raw) To: richardcochran, lee; +Cc: linux-kernel, netdev, Min Li From: Min Li <min.li.xe@renesas.com> Query MAX_FREQ_OFFSET register to set the proper limit. Signed-off-by: Min Li <min.li.xe@renesas.com> --- drivers/ptp/ptp_clockmatrix.c | 43 +++++++++++++++++++++++++------- drivers/ptp/ptp_clockmatrix.h | 1 + include/linux/mfd/idt8a340_reg.h | 1 + 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c index 21f3a2c179f5..cd7b3110f8e4 100644 --- a/drivers/ptp/ptp_clockmatrix.c +++ b/drivers/ptp/ptp_clockmatrix.c @@ -1038,7 +1038,7 @@ static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta) s64 now; if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) { - err = channel->do_phase_pull_in(channel, delta, 0); + err = channel->do_phase_pull_in(channel, delta, channel->caps.max_adj); } else { idtcm->calculate_overhead_flag = 1; @@ -1594,7 +1594,7 @@ static int do_phase_pull_in_sw(struct idtcm_channel *channel, if (abs(delta_ns) < PHASE_PULL_IN_MIN_THRESHOLD_NS) return 0; - if (max_ffo_ppb == 0) + if (max_ffo_ppb == 0 || max_ffo_ppb > PHASE_PULL_IN_MAX_PPB) max_ffo_ppb = PHASE_PULL_IN_MAX_PPB; /* For most cases, keep phase pull-in duration 1 second */ @@ -1880,7 +1880,7 @@ static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta) mutex_lock(idtcm->lock); if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) { - err = channel->do_phase_pull_in(channel, delta, 0); + err = channel->do_phase_pull_in(channel, delta, channel->caps.max_adj); } else { if (delta >= 0) { ts = ns_to_timespec64(delta); @@ -1927,9 +1927,6 @@ static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) if (channel->phase_pull_in == true) return 0; - if (scaled_ppm == channel->current_freq_scaled_ppm) - return 0; - mutex_lock(idtcm->lock); err = _idtcm_adjfine(channel, scaled_ppm); mutex_unlock(idtcm->lock); @@ -2054,7 +2051,7 @@ static struct ptp_pin_desc pin_config[MAX_TOD][MAX_REF_CLK]; static const struct ptp_clock_info idtcm_caps = { .owner = THIS_MODULE, - .max_adj = 244000, + .max_adj = MAX_FFO_PPB, .n_per_out = 12, .n_ext_ts = MAX_TOD, .n_pins = MAX_REF_CLK, @@ -2071,7 +2068,7 @@ static const struct ptp_clock_info idtcm_caps = { static const struct ptp_clock_info idtcm_caps_deprecated = { .owner = THIS_MODULE, - .max_adj = 244000, + .max_adj = MAX_FFO_PPB, .n_per_out = 12, .n_ext_ts = MAX_TOD, .n_pins = MAX_REF_CLK, @@ -2242,6 +2239,25 @@ static int configure_channel_tod(struct idtcm_channel *channel, u32 index) return 0; } +static int initialize_max_adj(struct idtcm_channel *channel) +{ + struct idtcm *idtcm = channel->idtcm; + u8 ffo_ppm; + int err; + + err = idtcm_read(idtcm, channel->dpll_n, DPLL_MAX_FREQ_OFFSET, + &ffo_ppm, sizeof(ffo_ppm)); + if (err) + return err; + + if (ffo_ppm && ffo_ppm <= (MAX_FFO_PPB / 1000)) + channel->caps.max_adj = ffo_ppm * 1000; + else + channel->caps.max_adj = MAX_FFO_PPB; + + return 0; +} + static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) { struct idtcm_channel *channel; @@ -2285,6 +2301,10 @@ static int idtcm_enable_channel(struct idtcm *idtcm, u32 index) ppd->chan = index; } + err = initialize_max_adj(channel); + if (err) + return err; + err = initialize_dco_operating_mode(channel); if (err) return err; @@ -2437,8 +2457,13 @@ static int idtcm_probe(struct platform_device *pdev) err = idtcm_load_firmware(idtcm, &pdev->dev); - if (err) + if (err) { + if (err == -ENOENT) { + mutex_unlock(idtcm->lock); + return -EPROBE_DEFER; + } dev_warn(idtcm->dev, "loading firmware failed with %d", err); + } wait_for_chip_ready(idtcm); diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h index ad39dc6decdf..31d90b1bf025 100644 --- a/drivers/ptp/ptp_clockmatrix.h +++ b/drivers/ptp/ptp_clockmatrix.h @@ -19,6 +19,7 @@ #define MAX_REF_CLK (16) #define MAX_ABS_WRITE_PHASE_NANOSECONDS (107374182L) +#define MAX_FFO_PPB (244000) #define TOD_MASK_ADDR (0xFFA5) #define DEFAULT_TOD_MASK (0x04) diff --git a/include/linux/mfd/idt8a340_reg.h b/include/linux/mfd/idt8a340_reg.h index b680a0eb5f68..13b36f4858b3 100644 --- a/include/linux/mfd/idt8a340_reg.h +++ b/include/linux/mfd/idt8a340_reg.h @@ -192,6 +192,7 @@ #define DPLL_CTRL_REG_0 0x0002 #define DPLL_CTRL_REG_1 0x0003 #define DPLL_CTRL_REG_2 0x0004 +#define DPLL_MAX_FREQ_OFFSET 0x0025 #define DPLL_WF_TIMER 0x002c #define DPLL_WP_TIMER 0x002e #define DPLL_TOD_SYNC_CFG 0x0031 -- 2.39.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2024-05-02 6:55 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- [not found] <20240104163641.15893-1-lnimi@hotmail.com> 2024-01-04 16:36 ` [PATCH net-next v7 2/5] ptp: clockmatrix: set write phase timer to 0 when not in PCW mode Min Li 2024-01-04 16:36 ` [PATCH net-next v7 3/5] ptp: clockmatrix: dco input-to-output delay is 20 FOD cycles + 8ns Min Li 2024-01-04 16:36 ` [PATCH net-next v7 4/5] ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO] Min Li 2024-01-11 10:47 ` Lee Jones 2024-01-04 16:36 ` [PATCH net-next v7 5/5] ptp: clockmatrix: move register and firmware related definition to idt8a340_reg.h Min Li 2024-01-11 10:48 ` Lee Jones [not found] <20240501160324.27514-1-lnimi@hotmail.com> 2024-05-01 16:03 ` [PATCH net-next v7 4/5] ptp: clockmatrix: Fix caps.max_adj to reflect DPLL_MAX_FREQ_OFFSET[MAX_FFO] Min Li 2024-05-02 6:54 ` Horatiu Vultur [not found] <20240318173213.28475-1-lnimi@hotmail.com> 2024-03-18 17:32 ` Min Li [not found] <20240314153707.31551-1-lnimi@hotmail.com> 2024-03-14 15:37 ` Min Li [not found] <20231214152415.14785-1-lnimi@hotmail.com> 2023-12-14 15:24 ` Min Li
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