From: Tal Gilboa <talgi@mellanox.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: Tariq Toukan <tariqt@mellanox.com>,
Jacob Keller <jacob.e.keller@intel.com>,
Ariel Elior <ariel.elior@cavium.com>,
Ganesh Goudar <ganeshgr@chelsio.com>,
Jeff Kirsher <jeffrey.t.kirsher@intel.com>,
everest-linux-l2@cavium.com, intel-wired-lan@lists.osuosl.org,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: Re: [PATCH v5 03/14] PCI: Add pcie_bandwidth_capable() to compute max supported link bandwidth
Date: Mon, 2 Apr 2018 10:34:58 +0300 [thread overview]
Message-ID: <50346f44-de3f-b226-69ad-6de45e94e261@mellanox.com> (raw)
In-Reply-To: <20180402004049.GA131023@bhelgaas-glaptop.roam.corp.google.com>
On 4/2/2018 3:40 AM, Bjorn Helgaas wrote:
> On Sun, Apr 01, 2018 at 11:38:53PM +0300, Tal Gilboa wrote:
>> On 3/31/2018 12:05 AM, Bjorn Helgaas wrote:
>>> From: Tal Gilboa <talgi@mellanox.com>
>>>
>>> Add pcie_bandwidth_capable() to compute the max link bandwidth supported by
>>> a device, based on the max link speed and width, adjusted by the encoding
>>> overhead.
>>>
>>> The maximum bandwidth of the link is computed as:
>>>
>>> max_link_speed * max_link_width * (1 - encoding_overhead)
>>>
>>> The encoding overhead is about 20% for 2.5 and 5.0 GT/s links using 8b/10b
>>> encoding, and about 1.5% for 8 GT/s or higher speed links using 128b/130b
>>> encoding.
>>>
>>> Signed-off-by: Tal Gilboa <talgi@mellanox.com>
>>> [bhelgaas: adjust for pcie_get_speed_cap() and pcie_get_width_cap()
>>> signatures, don't export outside drivers/pci]
>>> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>>> Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
>>> ---
>>> drivers/pci/pci.c | 21 +++++++++++++++++++++
>>> drivers/pci/pci.h | 9 +++++++++
>>> 2 files changed, 30 insertions(+)
>>>
>>> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
>>> index 43075be79388..9ce89e254197 100644
>>> --- a/drivers/pci/pci.c
>>> +++ b/drivers/pci/pci.c
>>> @@ -5208,6 +5208,27 @@ enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
>>> return PCIE_LNK_WIDTH_UNKNOWN;
>>> }
>>> +/**
>>> + * pcie_bandwidth_capable - calculates a PCI device's link bandwidth capability
>>> + * @dev: PCI device
>>> + * @speed: storage for link speed
>>> + * @width: storage for link width
>>> + *
>>> + * Calculate a PCI device's link bandwidth by querying for its link speed
>>> + * and width, multiplying them, and applying encoding overhead.
>>> + */
>>> +u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
>>> + enum pcie_link_width *width)
>>> +{
>>> + *speed = pcie_get_speed_cap(dev);
>>> + *width = pcie_get_width_cap(dev);
>>> +
>>> + if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
>>> + return 0;
>>> +
>>> + return *width * PCIE_SPEED2MBS_ENC(*speed);
>>> +}
>>> +
>>> /**
>>> * pci_select_bars - Make BAR mask from the type of resource
>>> * @dev: the PCI device for which BAR mask is made
>>> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
>>> index 66738f1050c0..2a50172b9803 100644
>>> --- a/drivers/pci/pci.h
>>> +++ b/drivers/pci/pci.h
>>> @@ -261,8 +261,17 @@ void pci_disable_bridge_window(struct pci_dev *dev);
>>> (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
>>> "Unknown speed")
>>> +/* PCIe speed to Mb/s with encoding overhead: 20% for gen2, ~1.5% for gen3 */
>>> +#define PCIE_SPEED2MBS_ENC(speed) \
>>
>> Missing gen4.
>
> I made it "gen3+". I think that's accurate, isn't it? The spec
> doesn't seem to actually use "gen3" as a specific term, but sec 4.2.2
> says rates of 8 GT/s or higher (which I think includes gen3 and gen4)
> use 128b/130b encoding.
>
I meant that PCIE_SPEED_16_0GT will return 0 from this macro since it
wasn't added. Need to return 15754.
next prev parent reply other threads:[~2018-04-02 7:34 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-30 21:04 [PATCH v5 00/14] Report PCI device link status Bjorn Helgaas
2018-03-30 21:04 ` [PATCH v5 01/14] PCI: Add pcie_get_speed_cap() to find max supported link speed Bjorn Helgaas
2018-03-30 21:04 ` [PATCH v5 02/14] PCI: Add pcie_get_width_cap() to find max supported link width Bjorn Helgaas
2018-03-30 21:05 ` [PATCH v5 03/14] PCI: Add pcie_bandwidth_capable() to compute max supported link bandwidth Bjorn Helgaas
2018-04-01 20:38 ` Tal Gilboa
2018-04-02 0:40 ` Bjorn Helgaas
2018-04-02 7:34 ` Tal Gilboa [this message]
2018-04-02 14:05 ` Bjorn Helgaas
2018-04-02 14:34 ` Tal Gilboa
2018-04-02 16:00 ` Keller, Jacob E
2018-04-02 19:37 ` Bjorn Helgaas
2018-04-03 0:30 ` Jacob Keller
2018-04-03 14:05 ` Bjorn Helgaas
2018-04-03 16:54 ` Keller, Jacob E
2018-03-30 21:05 ` [PATCH v5 04/14] PCI: Add pcie_bandwidth_available() to compute bandwidth available to device Bjorn Helgaas
2018-04-01 20:41 ` Tal Gilboa
2018-04-02 0:41 ` Bjorn Helgaas
2018-03-30 21:05 ` [PATCH v5 05/14] PCI: Add pcie_print_link_status() to log link speed and whether it's limited Bjorn Helgaas
2018-04-02 16:25 ` Keller, Jacob E
2018-04-02 19:58 ` Bjorn Helgaas
2018-04-02 20:25 ` Keller, Jacob E
2018-04-02 21:09 ` Tal Gilboa
2018-04-13 4:32 ` Jakub Kicinski
2018-04-13 14:06 ` Bjorn Helgaas
2018-04-13 15:34 ` Keller, Jacob E
2018-03-30 21:05 ` [PATCH v5 06/14] net/mlx4_core: Report PCIe link properties with pcie_print_link_status() Bjorn Helgaas
2018-03-30 21:05 ` [PATCH v5 07/14] net/mlx5: " Bjorn Helgaas
2018-03-30 21:05 ` [PATCH v5 08/14] net/mlx5e: Use pcie_bandwidth_available() to compute bandwidth Bjorn Helgaas
2018-03-30 21:05 ` [PATCH v5 09/14] bnx2x: Report PCIe link properties with pcie_print_link_status() Bjorn Helgaas
2018-03-30 21:05 ` [PATCH v5 10/14] bnxt_en: " Bjorn Helgaas
2018-03-30 21:06 ` [PATCH v5 11/14] cxgb4: " Bjorn Helgaas
2018-03-30 21:06 ` [PATCH v5 12/14] fm10k: " Bjorn Helgaas
2018-04-02 15:56 ` Keller, Jacob E
2018-04-02 20:31 ` Bjorn Helgaas
2018-04-02 20:36 ` Keller, Jacob E
2018-03-30 21:06 ` [PATCH v5 13/14] ixgbe: " Bjorn Helgaas
2018-03-30 21:06 ` [PATCH v5 14/14] PCI: Remove unused pcie_get_minimum_link() Bjorn Helgaas
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