[PATCH v2 0/4] Add support for Allwinner D1 CAN controllers

[PATCH v2 0/4] Add support for Allwinner D1 CAN controllers

[John Watts]

This patch series adds support for the Allwinner D1 CAN controllers.
It requires adding a new device tree compatible and driver support to
work around some hardware quirks.

This has been tested on the Mango Pi MQ Dual running a T113 and a Lichee
Panel 86 running a D1.

Changes in v2:
- Re-ordered patches to work with bisecting
- Fixed device tree label underscores
- Fixed email headers

John Watts (4):
  dt-bindings: net: can: Add support for Allwinner D1 CAN controller
  riscv: dts: allwinner: d1: Add CAN controller nodes
  can: sun4i_can: Add acceptance register quirk
  can: sun4i_can: Add support for the Allwinner D1

 .../net/can/allwinner,sun4i-a10-can.yaml      |  6 ++--
 .../boot/dts/allwinner/sunxi-d1s-t113.dtsi    | 30 +++++++++++++++++++
 drivers/net/can/Kconfig                       |  4 +--
 drivers/net/can/sun4i_can.c                   | 22 ++++++++++++--
 4 files changed, 55 insertions(+), 7 deletions(-)

-- 
2.41.0

[PATCH v2 1/4] dt-bindings: net: can: Add support for Allwinner D1 CAN controller

[John Watts]

The Allwinner D1 has two CAN controllers, both a variant of the R40
controller. Unfortunately the registers for the D1 controllers are
moved around enough to be incompatible and require a new compatible.

Introduce the "allwinner,sun20i-d1-can" compatible to support this.

Signed-off-by: John Watts <contact@jookia.org>
---
 .../bindings/net/can/allwinner,sun4i-a10-can.yaml           | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/can/allwinner,sun4i-a10-can.yaml b/Documentation/devicetree/bindings/net/can/allwinner,sun4i-a10-can.yaml
index 9c494957a07a..e42ea28d6ab4 100644
--- a/Documentation/devicetree/bindings/net/can/allwinner,sun4i-a10-can.yaml
+++ b/Documentation/devicetree/bindings/net/can/allwinner,sun4i-a10-can.yaml
@@ -21,6 +21,7 @@ properties:
           - const: allwinner,sun4i-a10-can
       - const: allwinner,sun4i-a10-can
       - const: allwinner,sun8i-r40-can
+      - const: allwinner,sun20i-d1-can
 
   reg:
     maxItems: 1
@@ -37,8 +38,9 @@ properties:
 if:
   properties:
     compatible:
-      contains:
-        const: allwinner,sun8i-r40-can
+      enum:
+        - allwinner,sun8i-r40-can
+        - allwinner,sun20i-d1-can
 
 then:
   required:
-- 
2.41.0

[PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes

[John Watts]

The Allwinner D1, T113 provide two CAN controllers that are variants
of the R40 controller.

I have tested support for these controllers on two boards:

- A Lichee Panel RV 86 Panel running a D1 chip
- A Mango Pi MQ Dual running a T113-s3 chip

Both of these fully support both CAN controllers.

Signed-off-by: John Watts <contact@jookia.org>
---
 .../boot/dts/allwinner/sunxi-d1s-t113.dtsi    | 30 +++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index 1bb1e5cae602..4086c0cc0f9d 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -131,6 +131,18 @@ uart3_pb_pins: uart3-pb-pins {
 				pins = "PB6", "PB7";
 				function = "uart3";
 			};
+
+			/omit-if-no-ref/
+			can0_pins: can0-pins {
+				pins = "PB2", "PB3";
+				function = "can0";
+			};
+
+			/omit-if-no-ref/
+			can1_pins: can1-pins {
+				pins = "PB4", "PB5";
+				function = "can1";
+			};
 		};
 
 		ccu: clock-controller@2001000 {
@@ -879,5 +891,23 @@ rtc: rtc@7090000 {
 			clock-names = "bus", "hosc", "ahb";
 			#clock-cells = <1>;
 		};
+
+		can0: can@2504000 {
+			compatible = "allwinner,sun20i-d1-can";
+			reg = <0x02504000 0x400>;
+			interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_CAN0>;
+			resets = <&ccu RST_BUS_CAN0>;
+			status = "disabled";
+		};
+
+		can1: can@2504400 {
+			compatible = "allwinner,sun20i-d1-can";
+			reg = <0x02504400 0x400>;
+			interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_CAN1>;
+			resets = <&ccu RST_BUS_CAN1>;
+			status = "disabled";
+		};
 	};
 };
-- 
2.41.0

[PATCH v2 3/4] can: sun4i_can: Add acceptance register quirk

[John Watts]

The Allwinner D1's CAN controllers have the ACPC and ACPM registers
moved down. Compensate for this by adding an offset quirk for the
acceptance registers.

Signed-off-by: John Watts <contact@jookia.org>
---
 drivers/net/can/sun4i_can.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/net/can/sun4i_can.c b/drivers/net/can/sun4i_can.c
index 0827830bbf28..1f90fe6dbb8b 100644
--- a/drivers/net/can/sun4i_can.c
+++ b/drivers/net/can/sun4i_can.c
@@ -205,9 +205,11 @@
  * struct sun4ican_quirks - Differences between SoC variants.
  *
  * @has_reset: SoC needs reset deasserted.
+ * @acp_offset: Offset of ACPC and ACPM registers
  */
 struct sun4ican_quirks {
 	bool has_reset;
+	int acp_offset;
 };
 
 struct sun4ican_priv {
@@ -216,6 +218,7 @@ struct sun4ican_priv {
 	struct clk *clk;
 	struct reset_control *reset;
 	spinlock_t cmdreg_lock;	/* lock for concurrent cmd register writes */
+	int acp_offset;
 };
 
 static const struct can_bittiming_const sun4ican_bittiming_const = {
@@ -338,8 +341,8 @@ static int sun4i_can_start(struct net_device *dev)
 	}
 
 	/* set filters - we accept all */
-	writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR);
-	writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR);
+	writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR + priv->acp_offset);
+	writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR + priv->acp_offset);
 
 	/* clear error counters and error code capture */
 	writel(0, priv->base + SUN4I_REG_ERRC_ADDR);
@@ -768,10 +771,12 @@ static const struct ethtool_ops sun4ican_ethtool_ops = {
 
 static const struct sun4ican_quirks sun4ican_quirks_a10 = {
 	.has_reset = false,
+	.acp_offset = 0,
 };
 
 static const struct sun4ican_quirks sun4ican_quirks_r40 = {
 	.has_reset = true,
+	.acp_offset = 0,
 };
 
 static const struct of_device_id sun4ican_of_match[] = {
@@ -870,6 +875,7 @@ static int sun4ican_probe(struct platform_device *pdev)
 	priv->base = addr;
 	priv->clk = clk;
 	priv->reset = reset;
+	priv->acp_offset = quirks->acp_offset;
 	spin_lock_init(&priv->cmdreg_lock);
 
 	platform_set_drvdata(pdev, dev);
-- 
2.41.0

[PATCH v2 4/4] can: sun4i_can: Add support for the Allwinner D1

[John Watts]

The controllers present in the D1 are extremely similar to the R40
and require the same reset quirks, but An extra quirk is needed to support
receiving packets.

Signed-off-by: John Watts <contact@jookia.org>
---
 drivers/net/can/Kconfig     |  4 ++--
 drivers/net/can/sun4i_can.c | 12 +++++++++++-
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index a5c5036dfb94..e626de33e735 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -185,10 +185,10 @@ config CAN_SLCAN
 
 config CAN_SUN4I
 	tristate "Allwinner A10 CAN controller"
-	depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
+	depends on MACH_SUN4I || MACH_SUN7I || RISCV || COMPILE_TEST
 	help
 	  Say Y here if you want to use CAN controller found on Allwinner
-	  A10/A20 SoCs.
+	  A10/A20/D1 SoCs.
 
 	  To compile this driver as a module, choose M here: the module will
 	  be called sun4i_can.
diff --git a/drivers/net/can/sun4i_can.c b/drivers/net/can/sun4i_can.c
index 1f90fe6dbb8b..c508a328e38d 100644
--- a/drivers/net/can/sun4i_can.c
+++ b/drivers/net/can/sun4i_can.c
@@ -91,6 +91,8 @@
 #define SUN4I_REG_BUF12_ADDR	0x0070	/* CAN Tx/Rx Buffer 12 */
 #define SUN4I_REG_ACPC_ADDR	0x0040	/* CAN Acceptance Code 0 */
 #define SUN4I_REG_ACPM_ADDR	0x0044	/* CAN Acceptance Mask 0 */
+#define SUN4I_REG_ACPC_ADDR_D1	0x0028	/* CAN Acceptance Code 0 on the D1 */
+#define SUN4I_REG_ACPM_ADDR_D1	0x002C	/* CAN Acceptance Mask 0 on the D1 */
 #define SUN4I_REG_RBUF_RBACK_START_ADDR	0x0180	/* CAN transmit buffer start */
 #define SUN4I_REG_RBUF_RBACK_END_ADDR	0x01b0	/* CAN transmit buffer end */
 
@@ -779,6 +781,11 @@ static const struct sun4ican_quirks sun4ican_quirks_r40 = {
 	.acp_offset = 0,
 };
 
+static const struct sun4ican_quirks sun4ican_quirks_d1 = {
+	.has_reset = true,
+	.acp_offset = (SUN4I_REG_ACPC_ADDR_D1 - SUN4I_REG_ACPC_ADDR),
+};
+
 static const struct of_device_id sun4ican_of_match[] = {
 	{
 		.compatible = "allwinner,sun4i-a10-can",
@@ -789,6 +796,9 @@ static const struct of_device_id sun4ican_of_match[] = {
 	}, {
 		.compatible = "allwinner,sun8i-r40-can",
 		.data = &sun4ican_quirks_r40
+	}, {
+		.compatible = "allwinner,sun20i-d1-can",
+		.data = &sun4ican_quirks_d1
 	}, {
 		/* sentinel */
 	},
@@ -913,4 +923,4 @@ module_platform_driver(sun4i_can_driver);
 MODULE_AUTHOR("Peter Chen <xingkongcp@gmail.com>");
 MODULE_AUTHOR("Gerhard Bertelsmann <info@gerhard-bertelsmann.de>");
 MODULE_LICENSE("Dual BSD/GPL");
-MODULE_DESCRIPTION("CAN driver for Allwinner SoCs (A10/A20)");
+MODULE_DESCRIPTION("CAN driver for Allwinner SoCs (A10/A20/D1)");
-- 
2.41.0

Re: [PATCH v2 1/4] dt-bindings: net: can: Add support for Allwinner D1 CAN controller

[Krzysztof Kozlowski]

On 22/07/2023 00:15, John Watts wrote:
> The Allwinner D1 has two CAN controllers, both a variant of the R40
> controller. Unfortunately the registers for the D1 controllers are
> moved around enough to be incompatible and require a new compatible.
> 
> Introduce the "allwinner,sun20i-d1-can" compatible to support this.
> 
> Signed-off-by: John Watts <contact@jookia.org>
> ---


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes

[John Watts]

On Sat, Jul 22, 2023 at 08:15:51AM +1000, John Watts wrote:
> ...
> +			/omit-if-no-ref/
> +			can0_pins: can0-pins {
> +				pins = "PB2", "PB3";
> +				function = "can0";
> +			};
> ...
> +		can0: can@2504000 {
> +			compatible = "allwinner,sun20i-d1-can";
> +			reg = <0x02504000 0x400>;
> +			interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_CAN0>;
> +			resets = <&ccu RST_BUS_CAN0>;
> +			status = "disabled";
> +		};

Just a quick late night question to people with more knowledge than me:

These chips only have one pinctrl configuration for can0 and can1. Should the
can nodes have this pre-set instead of the board dts doing this?

I see this happening in sun4i-a10.dtsi for instance, but it also seems like it
could become a problem when it comes to re-using the dtsi for newer chip variants.

John.

Re: [PATCH v2 0/4] Add support for Allwinner D1 CAN controllers

[Marc Kleine-Budde]

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On 22.07.2023 08:15:49, John Watts wrote:
> This patch series adds support for the Allwinner D1 CAN controllers.
> It requires adding a new device tree compatible and driver support to
> work around some hardware quirks.
> 
> This has been tested on the Mango Pi MQ Dual running a T113 and a Lichee
> Panel 86 running a D1.

Applied to linux-can-next/testing.

regards,
Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde          |
Embedded Linux                   | https://www.pengutronix.de |
Vertretung Nürnberg              | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-9   |

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Re: [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes

[Jernej Škrabec]

Dne nedelja, 23. julij 2023 ob 11:18:33 CEST je John Watts napisal(a):
> On Sat, Jul 22, 2023 at 08:15:51AM +1000, John Watts wrote:
> > ...
> > +			/omit-if-no-ref/
> > +			can0_pins: can0-pins {
> > +				pins = "PB2", "PB3";
> > +				function = "can0";
> > +			};
> > ...
> > +		can0: can@2504000 {
> > +			compatible = "allwinner,sun20i-d1-can";
> > +			reg = <0x02504000 0x400>;
> > +			interrupts = <SOC_PERIPHERAL_IRQ(21) 
IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&ccu CLK_BUS_CAN0>;
> > +			resets = <&ccu RST_BUS_CAN0>;
> > +			status = "disabled";
> > +		};
> 
> Just a quick late night question to people with more knowledge than me:
> 
> These chips only have one pinctrl configuration for can0 and can1. Should
> the can nodes have this pre-set instead of the board dts doing this?

Yes, that's usually how it's done.

> 
> I see this happening in sun4i-a10.dtsi for instance, but it also seems like
> it could become a problem when it comes to re-using the dtsi for newer chip
> variants.

Properties can be either rewritten or deleted further down, so don't worry 
about that.

Best regards,
Jernej

> 
> John.

Re: [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes

[John Watts]

On Mon, Jul 31, 2023 at 12:03:59AM +0200, Jernej Škrabec wrote:
> Yes, that's usually how it's done.
> 
> > 
> > I see this happening in sun4i-a10.dtsi for instance, but it also seems like
> > it could become a problem when it comes to re-using the dtsi for newer chip
> > variants.
> 
> Properties can be either rewritten or deleted further down, so don't worry 
> about that.
> 
> Best regards,
> Jernej
> 
> > 
> > John.

Thanks for the feedback, I've sent a patch to address this.

John.

Re: [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes

[Maksim Kiselev]

Hi John, Jernej

On Sat, Jul 22, 2023 at 08:15:51AM +1000, John Watts wrote:
> ...
> @@ -131,6 +131,18 @@ uart3_pb_pins: uart3-pb-pins {
> 				pins = "PB6", "PB7";
> 				function = "uart3";
> 			};
> +
> +			/omit-if-no-ref/
> +			can0_pins: can0-pins {
> +				pins = "PB2", "PB3";
> +				function = "can0";
> +			};
> +
> +			/omit-if-no-ref/
> +			can1_pins: can1-pins {
> +				pins = "PB4", "PB5";
> +				function = "can1";
> +			};
> ...

Should we also keep a pinctrl nodes itself in alphabetical order?
I mean placing a CAN nodes before `clk_pg11_pin` node?
Looks like the other nodes sorted in this way...

Cheers,
Maksim

Re: [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes

[John Watts]

On Sat, Aug 05, 2023 at 07:40:52PM +0300, Maksim Kiselev wrote:
> Hi John, Jernej
> Should we also keep a pinctrl nodes itself in alphabetical order?
> I mean placing a CAN nodes before `clk_pg11_pin` node?
> Looks like the other nodes sorted in this way...

Good catch. Now that you mention it, the device tree nodes are sorted
by memory order too! These should be after i2c3.

It looks like I might need to do a patch to re-order those too.

> Cheers,
> Maksim

John.

Re: [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes

[Jernej Škrabec]

Dne sobota, 05. avgust 2023 ob 18:51:53 CEST je John Watts napisal(a):
> On Sat, Aug 05, 2023 at 07:40:52PM +0300, Maksim Kiselev wrote:
> > Hi John, Jernej
> > Should we also keep a pinctrl nodes itself in alphabetical order?
> > I mean placing a CAN nodes before `clk_pg11_pin` node?
> > Looks like the other nodes sorted in this way...
> 
> Good catch. Now that you mention it, the device tree nodes are sorted
> by memory order too! These should be after i2c3.
> 
> It looks like I might need to do a patch to re-order those too.

It would be better if DT patches are dropped from netdev tree and then post 
new versions.

Best regards,
Jernej

> 
> > Cheers,
> > Maksim
> 
> John.

Re: [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes

[John Watts]

On Sat, Aug 05, 2023 at 07:49:51PM +0200, Jernej Škrabec wrote:
> Dne sobota, 05. avgust 2023 ob 18:51:53 CEST je John Watts napisal(a):
> > On Sat, Aug 05, 2023 at 07:40:52PM +0300, Maksim Kiselev wrote:
> > > Hi John, Jernej
> > > Should we also keep a pinctrl nodes itself in alphabetical order?
> > > I mean placing a CAN nodes before `clk_pg11_pin` node?
> > > Looks like the other nodes sorted in this way...
> > 
> > Good catch. Now that you mention it, the device tree nodes are sorted
> > by memory order too! These should be after i2c3.
> > 
> > It looks like I might need to do a patch to re-order those too.
> 
> It would be better if DT patches are dropped from netdev tree and then post 
> new versions.
> 
> Best regards,
> Jernej

Agreed. Is there a way to request that? Or will the maintainer just read this?

John.

Re: [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes

[Jernej Škrabec]

Dne nedelja, 06. avgust 2023 ob 08:33:45 CEST je John Watts napisal(a):
> On Sat, Aug 05, 2023 at 07:49:51PM +0200, Jernej Škrabec wrote:
> > Dne sobota, 05. avgust 2023 ob 18:51:53 CEST je John Watts napisal(a):
> > > On Sat, Aug 05, 2023 at 07:40:52PM +0300, Maksim Kiselev wrote:
> > > > Hi John, Jernej
> > > > Should we also keep a pinctrl nodes itself in alphabetical order?
> > > > I mean placing a CAN nodes before `clk_pg11_pin` node?
> > > > Looks like the other nodes sorted in this way...
> > > 
> > > Good catch. Now that you mention it, the device tree nodes are sorted
> > > by memory order too! These should be after i2c3.
> > > 
> > > It looks like I might need to do a patch to re-order those too.
> > 
> > It would be better if DT patches are dropped from netdev tree and then
> > post
> > new versions.
> > 
> > Best regards,
> > Jernej
> 
> Agreed. Is there a way to request that? Or will the maintainer just read
> this?

Hopefully it will.

Best regards,
Jernej

Re: [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes

[Marc Kleine-Budde]

[-- Attachment #1: Type: text/plain, Size: 1498 bytes --]

On 06.08.2023 13:42:28, Jernej Škrabec wrote:
> Dne nedelja, 06. avgust 2023 ob 08:33:45 CEST je John Watts napisal(a):
> > On Sat, Aug 05, 2023 at 07:49:51PM +0200, Jernej Škrabec wrote:
> > > Dne sobota, 05. avgust 2023 ob 18:51:53 CEST je John Watts napisal(a):
> > > > On Sat, Aug 05, 2023 at 07:40:52PM +0300, Maksim Kiselev wrote:
> > > > > Hi John, Jernej
> > > > > Should we also keep a pinctrl nodes itself in alphabetical order?
> > > > > I mean placing a CAN nodes before `clk_pg11_pin` node?
> > > > > Looks like the other nodes sorted in this way...
> > > > 
> > > > Good catch. Now that you mention it, the device tree nodes are sorted
> > > > by memory order too! These should be after i2c3.
> > > > 
> > > > It looks like I might need to do a patch to re-order those too.
> > > 
> > > It would be better if DT patches are dropped from netdev tree and then
> > > post
> > > new versions.
> > > 
> > > Best regards,
> > > Jernej
> > 
> > Agreed. Is there a way to request that? Or will the maintainer just read
> > this?
> 
> Hopefully it will.

I'm just catching up on last week's post (I had a long off-line
weekend).

I'll revert the DT changes and send a PR to net-next.

Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde          |
Embedded Linux                   | https://www.pengutronix.de |
Vertretung Nürnberg              | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-9   |

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Re: [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes

[Marc Kleine-Budde]

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On 07.08.2023 09:16:41, Marc Kleine-Budde wrote:
> On 06.08.2023 13:42:28, Jernej Škrabec wrote:
> > Dne nedelja, 06. avgust 2023 ob 08:33:45 CEST je John Watts napisal(a):
> > > On Sat, Aug 05, 2023 at 07:49:51PM +0200, Jernej Škrabec wrote:
> > > > Dne sobota, 05. avgust 2023 ob 18:51:53 CEST je John Watts napisal(a):
> > > > > On Sat, Aug 05, 2023 at 07:40:52PM +0300, Maksim Kiselev wrote:
> > > > > > Hi John, Jernej
> > > > > > Should we also keep a pinctrl nodes itself in alphabetical order?
> > > > > > I mean placing a CAN nodes before `clk_pg11_pin` node?
> > > > > > Looks like the other nodes sorted in this way...
> > > > > 
> > > > > Good catch. Now that you mention it, the device tree nodes are sorted
> > > > > by memory order too! These should be after i2c3.
> > > > > 
> > > > > It looks like I might need to do a patch to re-order those too.
> > > > 
> > > > It would be better if DT patches are dropped from netdev tree and then
> > > > post
> > > > new versions.
> > > > 
> > > > Best regards,
> > > > Jernej
> > > 
> > > Agreed. Is there a way to request that? Or will the maintainer just read
> > > this?
> > 
> > Hopefully it will.
> 
> I'm just catching up on last week's post (I had a long off-line
> weekend).
> 
> I'll revert the DT changes and send a PR to net-next.

Here's the revert:

| https://lore.kernel.org/all/20230807-riscv-allwinner-d1-revert-can-controller-nodes-v1-1-eb3f70b435d9@pengutronix.de/

Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde          |
Embedded Linux                   | https://www.pengutronix.de |
Vertretung Nürnberg              | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-9   |

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Re: [PATCH v2 4/4] can: sun4i_can: Add support for the Allwinner D1

[Geert Uytterhoeven]

Hi John,

On Sat, Jul 22, 2023 at 12:18 AM John Watts <contact@jookia.org> wrote:
> The controllers present in the D1 are extremely similar to the R40
> and require the same reset quirks, but An extra quirk is needed to support
> receiving packets.
>
> Signed-off-by: John Watts <contact@jookia.org>

Thanks for your patch, which is now commit 8abb95250ae6af2d ("can:
sun4i_can: Add support for the Allwinner D1") in linux-can-next/master.

> --- a/drivers/net/can/Kconfig
> +++ b/drivers/net/can/Kconfig
> @@ -185,10 +185,10 @@ config CAN_SLCAN
>
>  config CAN_SUN4I
>         tristate "Allwinner A10 CAN controller"
> -       depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
> +       depends on MACH_SUN4I || MACH_SUN7I || RISCV || COMPILE_TEST

This makes this question pop up when configuring a kernel for any RISC-V
platform, not just for Allwinner RISC-V platforms.

In comparison, drivers/clk/sunxi-ng/Kconfig does have some

    depends on MACH_SUN<foo>I || RISCV || COMPILE_TEST

but these are gated by ARCH_SUNXI at the top of the file.

I'm not sure what's the best way to fix this:
  - Replace RISCV by ARCH_SUNXI?
    This would expose it on more ARM sun<foo>i platforms, making the
    MACH_SUN4I || MACH_SUN7I superfluous?
  - Replace RISCV by RISCV && ARCH_SUNXI?

Thanks for your comments!

>         help
>           Say Y here if you want to use CAN controller found on Allwinner
> -         A10/A20 SoCs.
> +         A10/A20/D1 SoCs.
>
>           To compile this driver as a module, choose M here: the module will
>           be called sun4i_can.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 4/4] can: sun4i_can: Add support for the Allwinner D1

[John Watts]

On Tue, Aug 22, 2023 at 02:30:16PM +0200, Geert Uytterhoeven wrote:
> Hi John,
> 
> This makes this question pop up when configuring a kernel for any RISC-V
> platform, not just for Allwinner RISC-V platforms.

Oh dear.

> In comparison, drivers/clk/sunxi-ng/Kconfig does have some
> 
>     depends on MACH_SUN<foo>I || RISCV || COMPILE_TEST
> 
> but these are gated by ARCH_SUNXI at the top of the file.

Ah, that is what I copied.

> I'm not sure what's the best way to fix this:
>   - Replace RISCV by ARCH_SUNXI?
>     This would expose it on more ARM sun<foo>i platforms, making the
>     MACH_SUN4I || MACH_SUN7I superfluous?
>   - Replace RISCV by RISCV && ARCH_SUNXI?

I'm not sure what the best approach here is. Just having it require ARCH_SUNXI
would make sense to me but I'm not too sure why where's so many different MACH
here in the first place.

> Thanks for your comments!
> 
> >         help
> >           Say Y here if you want to use CAN controller found on Allwinner
> > -         A10/A20 SoCs.
> > +         A10/A20/D1 SoCs.
> >
> >           To compile this driver as a module, choose M here: the module will
> >           be called sun4i_can.
> 
> Gr{oetje,eeting}s,
> 
>                         Geert

John.

Re: [PATCH v2 0/4] Add support for Allwinner D1 CAN controllers

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (fixes)
by Marc Kleine-Budde <mkl@pengutronix.de>:

On Sat, 22 Jul 2023 08:15:49 +1000 you wrote:
> This patch series adds support for the Allwinner D1 CAN controllers.
> It requires adding a new device tree compatible and driver support to
> work around some hardware quirks.
> 
> This has been tested on the Mango Pi MQ Dual running a T113 and a Lichee
> Panel 86 running a D1.
> 
> [...]

Here is the summary with links:
  - [v2,1/4] dt-bindings: net: can: Add support for Allwinner D1 CAN controller
    (no matching commit)
  - [v2,2/4] riscv: dts: allwinner: d1: Add CAN controller nodes
    https://git.kernel.org/riscv/c/6ea1ad888f59
  - [v2,3/4] can: sun4i_can: Add acceptance register quirk
    (no matching commit)
  - [v2,4/4] can: sun4i_can: Add support for the Allwinner D1
    (no matching commit)

You are awesome, thank you!
-- 
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