Re: [PATCH v1 net-next 4/4] net: stmmac: setup higher frequency clk support for EHL & TGL

From: Florian Fainelli <f.fainelli@gmail.com>
To: "Voon, Weifeng" <weifeng.voon@intel.com>, Andrew Lunn <andrew@lunn.ch>
Cc: "David S. Miller" <davem@davemloft.net>,
	Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Jose Abreu <joabreu@synopsys.com>,
	Giuseppe Cavallaro <peppe.cavallaro@st.com>,
	Alexandre Torgue <alexandre.torgue@st.com>,
	"Ong, Boon Leong" <boon.leong.ong@intel.com>
Subject: Re: [PATCH v1 net-next 4/4] net: stmmac: setup higher frequency clk support for EHL & TGL
Date: Tue, 27 Aug 2019 08:08:30 -0700	[thread overview]
Message-ID: <7da534fa-9b7e-9980-e801-3c3e0429b885@gmail.com> (raw)
In-Reply-To: <D6759987A7968C4889FDA6FA91D5CBC814758DB5@PGSMSX103.gar.corp.intel.com>


On 8/27/2019 3:38 AM, Voon, Weifeng wrote:
>>>> +#include <linux/clk-provider.h>
>>>>  #include <linux/pci.h>
>>>>  #include <linux/dmi.h>
>>>>
>>>> @@ -174,6 +175,19 @@ static int intel_mgbe_common_data(struct
>> pci_dev *pdev,
>>>>  	plat->axi->axi_blen[1] = 8;
>>>>  	plat->axi->axi_blen[2] = 16;
>>>>
>>>> +	plat->ptp_max_adj = plat->clk_ptp_rate;
>>>> +
>>>> +	/* Set system clock */
>>>> +	plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
>>>> +						   "stmmac-clk", NULL, 0,
>>>> +						   plat->clk_ptp_rate);
>>>> +
>>>> +	if (IS_ERR(plat->stmmac_clk)) {
>>>> +		dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
>>>> +		plat->stmmac_clk = NULL;
>>>
>>> Don't you need to propagate at least EPROBE_DEFER here?
>>
>> Hi Florian
>>
>> Isn't a fixed rate clock a complete fake. There is no hardware behind it.
>> So can it return EPROBE_DEFER?
>>
>>     Andrew
> 
> Yes, there is no hardware behind it. So, I don't think we need to deferred probe
> and a warning message should be sufficient. Anyhow, please point it out if I miss
> out anything.

Looks good to me, thanks both for clarifying.
-- 
Florian