Re: mv88e6321, dual cpu port

[Angelo Dureghello <angelo@kernel-space.org>]

Hi Andrew,

On 24/01/23 2:57 PM, Andrew Lunn wrote:

 > With todays mainline i would do:
 >
 > So set eth0 as DSA master port.
 >
 > Create a bridge br0 with ports 0, 1, 2.
 > Create a bridge br1 with ports 3, 4, 6.
 >
 > You don't actually make use of the br1 interface in Linux, it just
 > needs to be up. You can think of eth1 being connected to an external
 > managed switch.
 >
 > 	Andrew

i upgraded to kernel 5.15.32, tried your option above.

In my initial request i inverted port 5
and 6 but i think this shouldn't matter.

Still data passes all trough port6, even when i ping from
host PC to port4. I was expecting instead to see port5
statistics increasing.

This is the script and the scheme i need:

#!/bin/sh
#
# Configuration:
#                                       +---- port0
#              br0 eth0  <->   port 6  -+---- port1
#                                       +---- port2
#
#                                       +---- port3
#              br1 eth1  <-> --------- -+-----port4
#                                       +---- port5
#
# tested, port4 ping, data passes always from port 6
#

ip link set eth0 up
ip link set eth1 up

# bring up the slave interfaces
ip link set port0 up
ip link set port1 up
ip link set port2 up
ip link set port3 up
ip link set port4 up
ip link set port5 up

# create bridge
ip link add name br0 type bridge
ip link add name br1 type bridge

# add ports to bridge
ip link set dev port0 master br0
ip link set dev port1 master br0
ip link set dev port2 master br0

ip link set dev port3 master br1
ip link set dev port4 master br1
ip link set dev port5 master br1

# configure the bridge
ip addr add 192.0.2.1/25 dev br0
ip addr add 192.0.2.129/25 dev br1

# bring up the bridge
ip link set dev br0 up
ip link set dev br1 up

And device tree:

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii";
	/* fsl,magic-packet; */
	tx-internal-delay-ps = <2000>;
	rx-internal-delay-ps = <2000>;

	status = "okay";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		switch1: switch1@1d {
			compatible = "marvell,mv88e6085";
			reg = <0x1d>;
			interrupt-parent = <&lsio_gpio3>;
			interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
			interrupt-controller;
			#interrupt-cells = <2>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "port0";
					phy-mode = "1000base-x";
					managed = "in-band-status";
					sfp = <&sfp_0>;
				};
				port@1 {
					reg = <1>;
					label = "port1";
					phy-mode = "1000base-x";
					managed = "in-band-status";
					sfp = <&sfp_1>;
				};
				/* This is phyenet0 now */
				port@2 {
					reg = <2>;
					label = "port2";
					phy-handle = <&switchphy2>;
				};
				port@6 {
					/* wired to cpu fec1 */
					reg = <6>;
					label = "cpu";
					ethernet = <&fec1>;
					phy-mode = "rgmii";
					fixed-link {
						speed = <1000>;
						full-duplex;
					};
				};
				port@3 {
					/* phy is internal to the switch */
					reg = <3>;
					label = "port3";
					phy-handle = <&switchphy3>;
				};
				port@4 {
					/* phy is internal to the switch */
					reg = <4>;
					label = "port4";
					phy-handle = <&switchphy4>;
				};
				port@5 {
					/* wired to cpu fec2 */
					reg = <5>;
					label = "port5";
					phy-mode = "rmii";
					fixed-link {
						speed = <100>;
						full-duplex;
					};
				};
			};

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				switchphy2: switchphy@2 {
					reg = <0x2>;
				};

				switchphy3: switchphy@3 {
					reg = <0x3>;
				};

				switchphy4: switchphy@4 {
					reg = <0x4>;
				};
			};
		};
	};
};

In any hint, welcome,

Thanks a lot,
-- 
Angelo Dureghello
+++ kernelspace +++
+E: angelo AT kernel-space.org
+W: www.kernel-space.org