[PATCH] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[PATCH] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

This patch adds support for the CAN FD controller found in Renesas R-Car
SoCs. The controller operates in CAN FD mode by default. Two test modes
are available and can be enabled by the "rcar_canfd.testmode" module
parameter. Refer to Documentation/kernel-parameters.txt.

CAN FD mode supports both Classical CAN & CAN FD frame formats. The
controller supports ISO 11898-1:2015 CAN FD format only.

This controller supports two channels and the driver can enable either
or both of the channels.

Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs (one
per channel) for transmission. Rx filter rules are configured to the
minimum (one per channel) and it accepts Standard, Extended, Data &
Remote Frame combinations.

Note: There are few documentation errors in R-Car Gen3 Hardware User
Manual v0.5E with respect to CAN FD controller. They are listed below:

1. CAN FD interrupt numbers 29 & 30 are listed as per channel
interrupts. However, they are common to both channels (i.e.) they are
global and channel interrupts respectively.

2. CANFD clock is derived from PLL1. This is not documented.

3. CANFD clock is further divided by (1/2) within the CAN FD controller.
This is not documented.

4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
is mentioned 4 Tq in the manual.

5. The maximum number of message RAM area the controller can use is 3584
bytes. It is mentioned 10752 bytes in the manual.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
---
Hi All,

   This work is based on linux-can-next (tag:linux-can-next-for-4.6-20160226) with
   the following patch applied on top

   [PATCH] can: rcar_can: Add r8a7795 support

   Pinctrl & Clock related to the controller are already submitted as below:

   https://lkml.org/lkml/2016/2/25/546
   https://lkml.org/lkml/2016/2/26/452
   http://www.spinics.net/lists/arm-kernel/msg487238.html

   DT submission will be done separately based on linux-next

Thanks,
Ramesh
---
 .../devicetree/bindings/net/can/rcar_canfd.txt     |   86 +
 Documentation/kernel-parameters.txt                |    8 +
 drivers/net/can/Kconfig                            |   10 +
 drivers/net/can/Makefile                           |    1 +
 drivers/net/can/rcar_canfd.c                       | 1905 ++++++++++++++++++++
 5 files changed, 2010 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
 create mode 100644 drivers/net/can/rcar_canfd.c

diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
new file mode 100644
index 0000000..4299bd8
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
@@ -0,0 +1,86 @@
+Renesas R-Car CAN FD controller Device Tree Bindings
+----------------------------------------------------
+
+Required properties:
+- compatible: Must contain one or more of the following:
+  - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
+  - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
+
+  When compatible with the generic version, nodes must list the
+  SoC-specific version corresponding to the platform first, followed by the
+  family-specific and/or generic versions.
+
+- reg: physical base address and size of the R-Car CAN FD register map.
+- interrupts: interrupt specifier for the Global & Channel interrupts
+- clocks: phandles and clock specifiers for 3 clock inputs.
+- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
+- pinctrl-0: pin control group to be used for this controller.
+- pinctrl-names: must be "default".
+
+Required properties for "renesas,r8a7795-canfd" compatible:
+In R8A7795 SoC, canfd clock is a div6 clock and can be used by both CAN
+and CAN FD controller at the same time. It needs to be scaled to maximum
+frequency if any of these controllers use it. This is done using the
+below properties.
+
+- assigned-clocks: phandle of canfd clock.
+- assigned-clock-rates: maximum frequency of this clock.
+
+Each channel is represented as a child node. They can be enabled/disabled
+using "status" property.
+
+Example
+-------
+
+SoC common .dtsi file:
+
+		canfd: canfd@e66c0000 {
+			compatible = "renesas,r8a7795-canfd",
+				     "renesas,rcar-gen3-canfd";
+			reg = <0 0xe66c0000 0 0x8000>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 914>,
+			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
+			       <&can_clk>;
+			clock-names = "fck", "canfd", "can_clk";
+			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
+			assigned-clock-rates = <40000000>;
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			channel0 {
+				status = "disabled";
+			};
+
+			channel1 {
+				status = "disabled";
+			};
+		};
+
+Board specific .dts file:
+
+E.g. below enables Channel 1 alone in the board.
+
+&canfd {
+        pinctrl-0 = <&canfd1_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+	channel1 {
+		status = "okay";
+	};
+};
+
+E.g. below enables Channel 0 alone in the board using External clock
+as fCAN clock.
+
+&canfd {
+        pinctrl-0 = <&canfd0_pins &can_clk_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+	channel0 {
+		status = "okay";
+	};
+};
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 9a53c92..afbb5cd 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -3121,6 +3121,14 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 	ramdisk_size=	[RAM] Sizes of RAM disks in kilobytes
 			See Documentation/blockdev/ramdisk.txt.
 
+	rcar_canfd.testmode=
+			[HW] Selects the Controller test mode
+			Format: {0|1|2}
+			0	Test modes disabled (default)
+			1	Self-test internal loopback mode
+			2	Inter-channel test mode
+			Default: 0
+
 	rcu_nocbs=	[KNL]
 			In kernels built with CONFIG_RCU_NOCB_CPU=y, set
 			the specified list of CPUs to be no-callback CPUs.
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 0d40aef..0ecb4fe 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -114,6 +114,16 @@ config CAN_RCAR
 	  To compile this driver as a module, choose M here: the module will
 	  be called rcar_can.
 
+config CANFD_RCAR
+	tristate "Renesas R-Car CAN FD controller"
+	depends on ARCH_RENESAS || ARM
+	---help---
+	  Say Y here if you want to use CAN FD controller found on
+	  Renesas R-Car SoCs.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called rcar_canfd.
+
 config CAN_SUN4I
 	tristate "Allwinner A10 CAN controller"
 	depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index e3db0c8..401b150 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_CAN_JANZ_ICAN3)	+= janz-ican3.o
 obj-$(CONFIG_CAN_MSCAN)		+= mscan/
 obj-$(CONFIG_CAN_M_CAN)		+= m_can/
 obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
+obj-$(CONFIG_CANFD_RCAR)	+= rcar_canfd.o
 obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
 obj-$(CONFIG_CAN_SUN4I)		+= sun4i_can.o
 obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
diff --git a/drivers/net/can/rcar_canfd.c b/drivers/net/can/rcar_canfd.c
new file mode 100644
index 0000000..6f85e25
--- /dev/null
+++ b/drivers/net/can/rcar_canfd.c
@@ -0,0 +1,1905 @@
+/* Renesas R-Car CAN FD device driver
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/netdevice.h>
+#include <linux/platform_device.h>
+#include <linux/can/led.h>
+#include <linux/can/dev.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+
+#define RCANFD_DRV_NAME			"rcar_canfd"
+
+#define RCANFD_FIFO_DEPTH		8	/* Tx FIFO depth */
+#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
+
+#define RCANFD_NUM_CHANNELS		2
+#define RCANFD_CHANNELS_MASK		0x3	/* Two channels max */
+
+/* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
+ * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
+ * number is added to RFFIFO index.
+ */
+#define RCANFD_RFFIFO_IDX		0
+
+/* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
+ * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
+ */
+#define RCANFD_CFFIFO_IDX		0
+
+/* Global register bits */
+#define RCANFD_GINTF_CANFD		BIT(0)
+
+#define RCANFD_GCFG_TPRI		BIT(0)
+#define RCANFD_GCFG_DCE			BIT(1)
+#define RCANFD_GCFG_DCS			BIT(4)
+#define RCANFD_GCFG_CMPOC		BIT(5)
+#define RCANFD_GCFG_EEFE		BIT(6)
+
+#define RCANFD_GCTR_SLPR		BIT(2)
+#define RCANFD_GCTR_MODEMASK		(0x3)
+#define RCANFD_GCTR_GOPM		(0x0)
+#define RCANFD_GCTR_GRESET		(0x1)
+#define RCANFD_GCTR_GHLT		(0x2)
+
+#define RCANFD_GCTR_DEIE		BIT(8)
+#define RCANFD_GCTR_MEIE		BIT(9)
+#define RCANFD_GCTR_THLEIE		BIT(10)
+#define RCANFD_GCTR_CFMPOFIE		BIT(11)
+#define RCANFD_GCTR_TSRST		BIT(16)
+
+#define RCANFD_GSTS_RAMINIT		BIT(3)
+#define RCANFD_GSTS_SLP			BIT(2)
+#define RCANFD_GSTS_HLT			BIT(1)
+#define RCANFD_GSTS_RESET		BIT(0)
+
+#define RCANFD_GSTS_GNOPM		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+/* Channel register bits */
+#define RCANFD_CCTR_CSLPR		BIT(2)
+#define RCANFD_CCTR_MODEMASK		(0x3)
+#define RCANFD_CCTR_COPM		(0x0)
+#define RCANFD_CCTR_CRESET		(0x1)
+#define RCANFD_CCTR_CHLT		(0x2)
+#define RCANFD_CCTR_CTMASK		(0x3 << 25)
+#define RCANFD_CCTR_CTMS_ILB		(0x3 << 25)
+#define RCANFD_CCTR_CTME		BIT(24)
+#define RCANFD_CCTR_ERRD		BIT(23)
+#define RCANFD_CCTR_BOMMASK		(0x3 << 21)
+#define RCANFD_CCTR_BOM_ENTRY		(0x1 << 21)
+#define RCANFD_CCTR_TDCVFIE		BIT(19)
+#define RCANFD_CCTR_SOCOIE		BIT(18)
+#define RCANFD_CCTR_EOCOIE		BIT(17)
+#define RCANFD_CCTR_TAIE		BIT(16)
+#define RCANFD_CCTR_ALIE		BIT(15)
+#define RCANFD_CCTR_BLIE		BIT(14)
+#define RCANFD_CCTR_OLIE		BIT(13)
+#define RCANFD_CCTR_BORIE		BIT(12)
+#define RCANFD_CCTR_BOEIE		BIT(11)
+#define RCANFD_CCTR_EPIE		BIT(10)
+#define RCANFD_CCTR_EWIE		BIT(9)
+#define RCANFD_CCTR_BEIE		BIT(8)
+
+#define RCANFD_CSTS_COM			BIT(7)
+#define RCANFD_CSTS_REC			BIT(6)
+#define RCANFD_CSTS_TRM			BIT(5)
+#define RCANFD_CSTS_BO			BIT(4)
+#define RCANFD_CSTS_EP			BIT(3)
+#define RCANFD_CSTS_SLP			BIT(2)
+#define RCANFD_CSTS_HALT		BIT(1)
+#define RCANFD_CSTS_RESET		BIT(0)
+
+#define RCANFD_CSTS_TECCNT(x)		(((x) >> 24) & 0xff)
+#define RCANFD_CSTS_RECCNT(x)		(((x) >> 16) & 0xff)
+
+/* Bit Configuration register */
+#define RCANFD_BRP(x)			(((x) & 0x3ff) << 0)
+#define RCANFD_SJW(x)			(((x) & 0x3) << 24)
+#define RCANFD_TSEG1(x)			(((x) & 0xf) << 16)
+#define RCANFD_TSEG2(x)			(((x) & 0x7) << 20)
+
+#define RCANFD_NR_BRP(x)		(((x) & 0x3ff) << 0)
+#define RCANFD_NR_SJW(x)		(((x) & 0x1f) << 11)
+#define RCANFD_NR_TSEG1(x)		(((x) & 0x7f) << 16)
+#define RCANFD_NR_TSEG2(x)		(((x) & 0x1f) << 24)
+
+#define RCANFD_DR_BRP(x)		(((x) & 0xff) << 0)
+#define RCANFD_DR_SJW(x)		(((x) & 0x7) << 24)
+#define RCANFD_DR_TSEG1(x)		(((x) & 0xf) << 16)
+#define RCANFD_DR_TSEG2(x)		(((x) & 0x7) << 20)
+
+/* Global Error flag bits */
+#define RCANFD_GERFL_EEF1		BIT(17)
+#define RCANFD_GERFL_EEF0		BIT(16)
+#define RCANFD_GERFL_CMPOF		BIT(3)
+#define RCANFD_GERFL_THLES		BIT(2)
+#define RCANFD_GERFL_MES		BIT(1)
+#define RCANFD_GERFL_DEF		BIT(0)
+
+#define RCANFD_GERFL_ERR(x)		((x) & (RCANFD_GERFL_EEF1 |\
+						RCANFD_GERFL_EEF0 |\
+						RCANFD_GERFL_MES |\
+						RCANFD_GERFL_CMPOF))
+
+/* Channel Error flag bits */
+#define RCANFD_CERFL_ADEF		BIT(14)
+#define RCANFD_CERFL_B0EF		BIT(13)
+#define RCANFD_CERFL_B1EF		BIT(12)
+#define RCANFD_CERFL_CEF		BIT(11)
+#define RCANFD_CERFL_AEF		BIT(10)
+#define RCANFD_CERFL_FEF		BIT(9)
+#define RCANFD_CERFL_SEF		BIT(8)
+#define RCANFD_CERFL_ALEF		BIT(7)
+#define RCANFD_CERFL_BLEF		BIT(6)
+#define RCANFD_CERFL_OLEF		BIT(5)
+#define RCANFD_CERFL_BOREF		BIT(4)
+#define RCANFD_CERFL_BOEEF		BIT(3)
+#define RCANFD_CERFL_EPEF		BIT(2)
+#define RCANFD_CERFL_EWEF		BIT(1)
+#define RCANFD_CERFL_BEF		BIT(0)
+
+#define RCANFD_CERFL_ERR(x)		((x) & (0x7fff)) /* above bits 14:0 */
+
+/* CAN FD specific registers */
+#define RCANFD_DCFG_TDCE		BIT(9)
+#define RCANFD_DCFG_TDCOC		BIT(8)
+#define RCANFD_DCFG_TDCO(x)		(((x) & 0x7f) >> 16)
+
+#define RCANFD_DCSTS_TDCR(x)		(((x) >> 0) & 0x7f)
+#define RCANFD_DCSTS_SOCCNT(x)		(((x) >> 24) & 0xff)
+#define RCANFD_DCSTS_EOCCNT(x)		(((x) >> 16) & 0xff)
+
+#define RCANFD_DCSTS_TDCVF		BIT(7)
+#define RCANFD_DCSTS_EOCO		BIT(8)
+#define RCANFD_DCSTS_SOCO		BIT(9)
+
+/* Rx FIFO bits */
+#define RCANFD_RFFIFO_RFIF		BIT(3)
+#define RCANFD_RFFIFO_RFMLT		BIT(2)
+#define RCANFD_RFFIFO_RFFLL		BIT(1)
+#define RCANFD_RFFIFO_RFEMP		BIT(0)
+
+#define RCANFD_RFFIFO_RFESI		BIT(0)
+#define RCANFD_RFFIFO_RFBRS		BIT(1)
+#define RCANFD_RFFIFO_RFFDF		BIT(2)
+
+#define RCANFD_RFFIFO_RFIDE		BIT(31)
+#define RCANFD_RFFIFO_RFRTR		BIT(30)
+
+#define RCANFD_RFFIFO_RFDLC(x)		(((x) >> 28) & 0xf)
+#define RCANFD_RFFIFO_RFPTR(x)		(((x) >> 16) & 0xfff)
+#define RCANFD_RFFIFO_RFTS(x)		(((x) >> 0) & 0xff)
+
+#define RCANFD_RFFIFO_RFIM		BIT(12)
+#define RCANFD_RFFIFO_RFDC(x)		(((x) & 0x7) << 8)
+#define RCANFD_RFFIFO_RFPLS(x)		(((x) & 0x7) << 4)
+#define RCANFD_RFFIFO_RFIE		BIT(1)
+#define RCANFD_RFFIFO_RFE		BIT(0)
+
+/* Common FIFO bits */
+#define RCANFD_CMFIFO_TML(x)		(((x) & 0xf) << 20)
+#define RCANFD_CMFIFO_M(x)		(((x) & 0x3) << 16)
+#define RCANFD_CMFIFO_CFIM		BIT(12)
+#define RCANFD_CMFIFO_DC(x)		(((x) & 0x7) << 8)
+#define RCANFD_CMFIFO_PLS(x)		(((x) & 0x7) << 4)
+#define RCANFD_CMFIFO_CFTXIE		BIT(2)
+#define RCANFD_CMFIFO_CFE		BIT(0)
+
+#define RCANFD_CMFIFO_CFTXIF		BIT(4)
+#define RCANFD_CMFIFO_CFMLT		BIT(2)
+#define RCANFD_CMFIFO_CFFLL		BIT(1)
+#define RCANFD_CMFIFO_CFEMP		BIT(0)
+#define RCANFD_CMFIFO_CFMC(x)		(((x) >> 8) & 0xff)
+
+#define RCANFD_CMFIFO_CFESI		BIT(0)
+#define RCANFD_CMFIFO_CFBRS		BIT(1)
+#define RCANFD_CMFIFO_CFFDF		BIT(2)
+
+#define RCANFD_CMFIFO_CFIDE		BIT(31)
+#define RCANFD_CMFIFO_CFRTR		BIT(30)
+#define RCANFD_CMFIFO_CFID(x)		((x) & 0x1fffffff)
+
+#define RCANFD_CMFIFO_CFDLC(x)		(((x) & 0xf) << 28)
+#define RCANFD_CMFIFO_CFPTR(x)		(((x) & 0xfff) << 16)
+#define RCANFD_CMFIFO_CFTS(x)		(((x) & 0xff) << 0)
+
+/* Global Test Config register */
+#define RCANFD_GTSTCFG_C0CBCE		BIT(0)
+#define RCANFD_GTSTCFG_C1CBCE		BIT(1)
+
+#define RCANFD_GTSTCTR_ICBCTME		BIT(0)
+
+/* AFL Rx rules registers */
+#define RCANFD_AFLCFG_SETRNC0(x)	(((x) & 0xff) << 24)
+#define RCANFD_AFLCFG_SETRNC1(x)	(((x) & 0xff) << 16)
+#define RCANFD_AFLCFG_GETRNC0(x)	(((x) >> 24) & 0xff)
+#define RCANFD_AFLCFG_GETRNC1(x)	(((x) >> 16) & 0xff)
+
+#define RCANFD_AFL_PAGENUM(entry)	((entry) / 16)
+
+#define RCANFD_AFLCTR_AFLDAE		BIT(8)
+#define RCANFD_AFLCTR_AFLPN(x)		((x) & 0x1f)
+#define RCANFD_CHANNEL_NUMRULES		1	/* only one rule per channel */
+#define RCANFD_AFLID_GAFLLB		BIT(29)
+#define RCANFD_AFLPTR1_RFFIFO(x)	(1 << (x))
+
+/* Common register map offsets */
+
+/* Nominal rate registers */
+#define RCANFD_CCFG(m)			(0x0000 + (0x10 * (m)))
+#define RCANFD_CCTR(m)			(0x0004 + (0x10 * (m)))
+#define RCANFD_CSTS(m)			(0x0008 + (0x10 * (m)))
+#define RCANFD_CERFL(m)			(0x000C + (0x10 * (m)))
+
+/* Global registers */
+#define RCANFD_GCFG			(0x0084)
+#define RCANFD_GCTR			(0x0088)
+#define RCANFD_GSTS			(0x008c)
+#define RCANFD_GERFL			(0x0090)
+#define RCANFD_GTSC			(0x0094)
+#define RCANFD_GAFLECTR			(0x0098)
+#define RCANFD_GAFLCFG0			(0x009c)
+#define RCANFD_GAFLCFG1			(0x00a0)
+#define RCANFD_RMNB			(0x00a4)
+
+#define RCANFD_RMND(y)			(0x00a8 + (0x04 * (y)))
+
+/* Rx FIFO Control registers */
+#define RCANFD_RFCC(x)			(0x00b8 + (0x04 * (x)))
+#define RCANFD_RFSTS(x)			(0x00d8 + (0x04 * (x)))
+#define RCANFD_RFPCTR(x)		(0x00f8 + (0x04 * (x)))
+
+/* Common FIFO Control registers */
+#define RCANFD_CFCC(ch, idx)		(0x0118 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+#define RCANFD_CFSTS(ch, idx)		(0x0178 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+#define RCANFD_CFPCTR(ch, idx)		(0x01d8 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+
+#define RCANFD_FESTS			(0x0238)
+#define RCANFD_FFSTS			(0x023c)
+#define RCANFD_FMSTS			(0x0240)
+#define RCANFD_RFISTS			(0x0244)
+#define RCANFD_CFRISTS			(0x0248)
+#define RCANFD_CFTISTS			(0x024c)
+
+#define RCANFD_TMC(p)			(0x0250 + (0x01 * (p)))
+#define RCANFD_TMSTS(p)			(0x02d0 + (0x01 * (p)))
+
+#define RCANFD_TMTRSTS(y)		(0x0350 + (0x04 * (y)))
+#define RCANFD_TMTARSTS(y)		(0x0360 + (0x04 * (y)))
+#define RCANFD_TMTCSTS(y)		(0x0370 + (0x04 * (y)))
+#define RCANFD_TMTASTS(y)		(0x0380 + (0x04 * (y)))
+#define RCANFD_TMIEC(y)			(0x0390 + (0x04 * (y)))
+
+#define RCANFD_TXQCC(m)			(0x03a0 + (0x04 * (m)))
+#define RCANFD_TXQSTS(m)		(0x03c0 + (0x04 * (m)))
+#define RCANFD_TXQPCTR(m)		(0x03e0 + (0x04 * (m)))
+
+#define RCANFD_THLCC(m)			(0x0400 + (0x04 * (m)))
+#define RCANFD_THLSTS(m)		(0x0420 + (0x04 * (m)))
+#define RCANFD_THLPCTR(m)		(0x0440 + (0x04 * (m)))
+
+#define RCANFD_GTINTSTS0		(0x0460)
+#define RCANFD_GTINTSTS1		(0x0464)
+#define RCANFD_GTSTCFG			(0x0468)
+#define RCANFD_GTSTCTR			(0x046c)
+#define RCANFD_GLOCKK			(0x047c)
+#define RCANFD_GRMCFG			(0x04fc)
+
+/* Receive rule registers */
+#define RCANFD_GAFLID(offset, j)	((offset) + (0x10 * (j)))
+#define RCANFD_GAFLM(offset, j)		((offset) + 0x04 + (0x10 * (j)))
+#define RCANFD_GAFLP0(offset, j)	((offset) + 0x08 + (0x10 * (j)))
+#define RCANFD_GAFLP1(offset, j)	((offset) + 0x0c + (0x10 * (j)))
+
+/* CAN FD mode specific regsiter map */
+
+/* Data bitrate registers */
+#define RCANFD_F_CDFG(m)		(0x0500 + (0x20 * (m)))
+#define RCANFD_F_CFDCFG(m)		(0x0504 + (0x20 * (m)))
+#define RCANFD_F_CFDCTR(m)		(0x0508 + (0x20 * (m)))
+#define RCANFD_F_CFDSTS(m)		(0x050c + (0x20 * (m)))
+#define RCANFD_F_CFDCRC(m)		(0x0510 + (0x20 * (m)))
+
+#define RCANFD_F_GAFL_OFFSET		(0x1000)
+
+#define RCANFD_F_RMID(q)		(0x2000 + (0x10 * (q)))
+#define RCANFD_F_RMPTR(q)		(0x2004 + (0x10 * (q)))
+#define RCANFD_F_RMFDSTS(q)		(0x2008 + (0x10 * (q)))
+#define RCANFD_F_RMDF(q, b)		(0x200c + (0x04 * (b)) + (0x20 * (q)))
+
+/* Rx FIFO data registers */
+#define RCANFD_F_RFOFFSET		(0x3000)
+#define RCANFD_F_RFID(x)		(RCANFD_F_RFOFFSET + (0x80 * (x)))
+#define RCANFD_F_RFPTR(x)		(RCANFD_F_RFOFFSET + 0x04 + \
+					 (0x80 * (x)))
+#define RCANFD_F_RFFDSTS(x)		(RCANFD_F_RFOFFSET + 0x08 + \
+					 (0x80 * (x)))
+#define RCANFD_F_RFDF(x, df)		(RCANFD_F_RFOFFSET + 0x0c + \
+					 (0x80 * (x)) + (0x04 * (df)))
+
+/* Common FIFO data registers */
+#define RCANFD_F_CFOFFSET		(0x3400)
+#define RCANFD_F_CFID(ch, idx)		(RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
+					 (0x80 * (idx)))
+#define RCANFD_F_CFPTR(ch, idx)		(RCANFD_F_CFOFFSET + 0x04 + \
+					 (0x180 * (ch)) + (0x80 * (idx)))
+#define RCANFD_F_CFFDCSTS(ch, idx)	(RCANFD_F_CFOFFSET + 0x08 + \
+					 (0x180 * (ch)) + (0x80 * (idx)))
+#define RCANFD_F_CFDF(ch, idx, df)	(RCANFD_F_CFOFFSET + 0x0c + \
+					 (0x180 * (ch)) + (0x80 * (idx)) + \
+					 (0x04 * (df)))
+
+#define RCANFD_F_TMID(p)		(0x4000 + (0x20 * (p)))
+#define RCANFD_F_TMPTR(p)		(0x4004 + (0x20 * (p)))
+#define RCANFD_F_TMFDCTR(p)		(0x4008 + (0x20 * (p)))
+#define RCANFD_F_TMDF(p, b)		(0x400c + (0x20 * (p)) + (0x04 * (b)))
+
+#define RCANFD_F_THLACC(m)		(0x6000 + (0x04 * (m)))
+#define RCANFD_F_RPGACC(r)		(0x6400 + (0x04 * (r)))
+
+struct rcar_canfd_global;
+
+/* Channel priv data */
+struct rcar_canfd_channel {
+	struct can_priv can;			/* Must be the first member */
+	struct net_device *ndev;
+	struct rcar_canfd_global *gpriv;	/* Controller reference */
+	void __iomem *base;			/* Register base address */
+#ifdef CONFIG_DEBUG_FS
+	struct dentry *dev_root;
+#endif /* CONFIG_DEBUG_FS */
+	struct napi_struct napi;
+	u8  tx_len[RCANFD_FIFO_DEPTH];		/* For net stats */
+	u32 tx_head;				/* Incremented on xmit */
+	u32 tx_tail;				/* Incremented on xmit done */
+	u32 channel;				/* Channel number */
+};
+
+/* Global priv data */
+struct rcar_canfd_global {
+	struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
+	void __iomem *base;		/* Register base address */
+	struct platform_device *pdev;	/* Respective platform device */
+	struct clk *clkp;		/* Peripheral clock */
+	struct clk *can_clk;		/* fCAN clock */
+	int clock_select;		/* CANFD or Ext clock */
+	unsigned long channels_mask;	/* Enabled channels mask */
+	u32 freq;			/* fCAN clock frequency in Hz */
+};
+
+/* CAN FD mode nominal rate constants */
+static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
+	.name = RCANFD_DRV_NAME,
+	.tseg1_min = 2,
+	.tseg1_max = 128,
+	.tseg2_min = 2,
+	.tseg2_max = 32,
+	.sjw_max = 32,
+	.brp_min = 1,
+	.brp_max = 1024,
+	.brp_inc = 1,
+};
+
+/* CAN FD mode data rate constants */
+static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
+	.name = RCANFD_DRV_NAME,
+	.tseg1_min = 2,
+	.tseg1_max = 16,
+	.tseg2_min = 2,
+	.tseg2_max = 8,
+	.sjw_max = 8,
+	.brp_min = 1,
+	.brp_max = 256,
+	.brp_inc = 1,
+};
+
+/* Test modes */
+enum {
+	RCANFD_TESTMODE_NONE = 0,
+	RCANFD_TESTMODE_INTERNAL_LOOPBACK,
+	RCANFD_TESTMODE_INTERCHANNEL,
+};
+
+static int testmode = RCANFD_TESTMODE_NONE;
+module_param(testmode, int, 0644);
+
+/* fCAN clock select register settings */
+enum {
+	RCANFD_CANFDCLK = 0,	/* CANFD clock */
+	RCANFD_EXTCLK,		/* Externally input clock */
+};
+
+/* Helper functions */
+static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
+{
+	u32 data = readl(reg);
+
+	data &= ~mask;
+	data |= (val & mask);
+	writel(data, reg);
+}
+
+#define rcar_canfd_read(priv, offset)			\
+	readl(priv->base + (offset))
+#define rcar_canfd_write(priv, offset, val)		\
+	writel(val, priv->base + (offset))
+#define rcar_canfd_set_bit(priv, reg, val)		\
+	rcar_canfd_update(val, val, priv->base + (reg))
+#define rcar_canfd_clear_bit(priv, reg, val)		\
+	rcar_canfd_update(val, 0, priv->base + (reg))
+#define rcar_canfd_update_bit(priv, reg, mask, val)	\
+	rcar_canfd_update(mask, val, priv->base + (reg))
+
+static void rcar_canfd_get_data(struct canfd_frame *cf,
+				struct rcar_canfd_channel *priv, u32 off)
+{
+	u32 i, lwords;
+
+	lwords = cf->len / sizeof(u32);
+	if (cf->len % sizeof(u32))
+		lwords++;
+	for (i = 0; i < lwords; i++)
+		*((u32 *)cf->data + i) =
+			rcar_canfd_read(priv, off + (i * sizeof(u32)));
+}
+
+static void rcar_canfd_put_data(struct canfd_frame *cf,
+				struct rcar_canfd_channel *priv, u32 off)
+{
+	u32 i, j, lwords, leftover;
+	u32 data = 0;
+
+	lwords = cf->len / sizeof(u32);
+	leftover = cf->len % sizeof(u32);
+	for (i = 0; i < lwords; i++)
+		rcar_canfd_write(priv, off + (i * sizeof(u32)),
+				 *((u32 *)cf->data + i));
+
+	if (leftover) {
+		u8 *p = (u8 *)((u32 *)cf->data + i);
+
+		for (j = 0; j < leftover; j++)
+			data |= p[j] << (j * 8);
+		rcar_canfd_write(priv, off + (i * sizeof(u32)), data);
+	}
+}
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+
+static int rcar_canfd_showregs(struct seq_file *s, void *data)
+{
+	struct rcar_canfd_channel *priv = s->private;
+	u32 ch = priv->channel;
+	u32 rf = ch + RCANFD_RFFIFO_IDX;
+	u32 cf = RCANFD_CFFIFO_IDX;
+	u32 val, offset, i;
+
+	if (testmode)
+		seq_printf(s, "RCANFD : testmode = %d\n", testmode);
+	seq_printf(s, "RCANFD register dump: channel %u\n", ch);
+	seq_printf(s, "%-40s: %x\n", "g: cfg",
+		   rcar_canfd_read(priv, RCANFD_GCFG));
+	seq_printf(s, "%-40s: %x\n", "g: ctr",
+		   rcar_canfd_read(priv, RCANFD_GCTR));
+	seq_printf(s, "%-40s: %x\n", "g: sts",
+		   rcar_canfd_read(priv, RCANFD_GSTS));
+	seq_printf(s, "%-40s: %x\n", "afl: ectr",
+		   rcar_canfd_read(priv, RCANFD_GAFLECTR));
+	seq_printf(s, "%-40s: %x\n", "afl: cfg0",
+		   rcar_canfd_read(priv, RCANFD_GAFLCFG0));
+	seq_printf(s, "%-40s: %x\n", "afl: cfg1",
+		   rcar_canfd_read(priv, RCANFD_GAFLCFG1));
+
+	offset = RCANFD_F_GAFL_OFFSET;
+	val = rcar_canfd_read(priv, RCANFD_GAFLCFG0);
+	if (ch == 0) /* Channel */
+		i = 0;	/* Start with 0th rule always */
+	else
+		i = RCANFD_AFLCFG_GETRNC0(val);
+
+	seq_printf(s, "%-40s: %x\n", "afl: id",
+		   rcar_canfd_read(priv, RCANFD_GAFLID(offset, i)));
+	seq_printf(s, "%-40s: %x\n", "afl: mask",
+		   rcar_canfd_read(priv, RCANFD_GAFLM(offset, i)));
+	seq_printf(s, "%-40s: %x\n", "afl: ptr0",
+		   rcar_canfd_read(priv, RCANFD_GAFLP0(offset, i)));
+	seq_printf(s, "%-40s: %x\n", "afl: ptr1",
+		   rcar_canfd_read(priv, RCANFD_GAFLP1(offset, i)));
+
+	seq_puts(s, "RCANFD Global and Channel error flags:\n");
+	val = rcar_canfd_read(priv, RCANFD_GERFL);
+	seq_printf(s, "%-40s: %x\n", "g: erfl", val);
+	if (val & RCANFD_GERFL_DEF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "dlc error");
+	if (val & RCANFD_GERFL_MES)
+		seq_printf(s, "%-40s: %s\n", " --> ", "fifo msg lost");
+	if (val & RCANFD_GERFL_THLES)
+		seq_printf(s, "%-40s: %s\n", " --> ", "tx history lost");
+	if (val & RCANFD_GERFL_CMPOF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "payload overflow");
+	if (val & RCANFD_GERFL_EEF0)
+		seq_printf(s, "%-40s: %s\n", " --> ", "ecc ch0 error");
+	if (val & RCANFD_GERFL_EEF1)
+		seq_printf(s, "%-40s: %s\n", " --> ", "ecc ch1 error");
+	val = rcar_canfd_read(priv, RCANFD_CERFL(ch));
+	seq_printf(s, "%-40s: %x\n", "nr: erfl", val);
+	if (val & RCANFD_CERFL_ADEF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "ack delimiter error");
+	if (val & RCANFD_CERFL_B0EF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "dominant bit error");
+	if (val & RCANFD_CERFL_B1EF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "recessive bit error");
+	if (val & RCANFD_CERFL_CEF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "crc error");
+	if (val & RCANFD_CERFL_AEF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "ack error");
+	if (val & RCANFD_CERFL_FEF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "form error");
+	if (val & RCANFD_CERFL_SEF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "stuff error");
+	if (val & RCANFD_CERFL_ALEF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "arb lost");
+	if (val & RCANFD_CERFL_BLEF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "bus lock");
+	if (val & RCANFD_CERFL_OLEF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "overload");
+	if (val & RCANFD_CERFL_BOREF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "bus off recov");
+	if (val & RCANFD_CERFL_BOEEF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "bus off entry");
+	if (val & RCANFD_CERFL_EPEF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "error passive");
+	if (val & RCANFD_CERFL_EWEF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "error warning");
+	if (val & RCANFD_CERFL_BEF)
+		seq_printf(s, "%-40s: %s\n", " --> ", "bus error");
+	seq_puts(s, "RCANFD Normal Control & Status Register:\n");
+	seq_printf(s, "%-40s: %x\n", "nr: ncfg",
+		   rcar_canfd_read(priv, RCANFD_CCFG(ch)));
+	seq_printf(s, "%-40s: %x\n", "nr: ctr",
+		   rcar_canfd_read(priv, RCANFD_CCTR(ch)));
+	val = rcar_canfd_read(priv, RCANFD_CSTS(ch));
+	seq_printf(s, "%-40s: %x\n", "nr: sts", val);
+	if (RCANFD_CSTS_TECCNT(val))
+		seq_printf(s, "%-40s: %x\n", " teccnt ",
+			   RCANFD_CSTS_TECCNT(val));
+	if (RCANFD_CSTS_RECCNT(val))
+		seq_printf(s, "%-40s: %x\n", " reccnt ",
+			   RCANFD_CSTS_RECCNT(val));
+	if (val & RCANFD_CSTS_BO)
+		seq_printf(s, "%-40s: %s\n", " --> ", "bus off status");
+	if (val & RCANFD_CSTS_EP)
+		seq_printf(s, "%-40s: %s\n", " --> ", "error passive status");
+	seq_puts(s, "RCANFD Data Status Register:\n");
+	seq_printf(s, "%-40s: %x\n", "dr: dcfg",
+		   rcar_canfd_read(priv, RCANFD_F_CDFG(ch)));
+	seq_printf(s, "%-40s: %x\n", "dr: fdcfg",
+		   rcar_canfd_read(priv, RCANFD_F_CFDCFG(ch)));
+	seq_printf(s, "%-40s: %x\n", "dr: fdctr",
+		   rcar_canfd_read(priv, RCANFD_F_CFDCTR(ch)));
+	val = rcar_canfd_read(priv, RCANFD_F_CFDSTS(ch));
+	seq_printf(s, "%-40s: %x\n", "dr: sts", val);
+	if (RCANFD_DCSTS_TDCR(val))
+		seq_printf(s, "%-40s: %x\n", " tdcr ",
+			   RCANFD_DCSTS_TDCR(val));
+	if (RCANFD_DCSTS_SOCCNT(val))
+		seq_printf(s, "%-40s: %x\n", " soccnt ",
+			   RCANFD_DCSTS_SOCCNT(val));
+	if (RCANFD_DCSTS_EOCCNT(val))
+		seq_printf(s, "%-40s: %x\n", " eoccnt ",
+			   RCANFD_DCSTS_EOCCNT(val));
+	if (val & RCANFD_DCSTS_EOCO)
+		seq_printf(s, "%-40s: %s\n", " --> ",
+			   "error occurrence overflow");
+	if (val & RCANFD_DCSTS_TDCVF)
+		seq_printf(s, "%-40s: %s\n", " --> ",
+			   "transmit delay correction violation");
+	seq_puts(s, "RCANFD FIFO Registers:\n");
+	seq_printf(s, "%-40s: %x\n", "rxfc: cc",
+		   rcar_canfd_read(priv, RCANFD_RFCC(rf)));
+	seq_printf(s, "%-40s: %x\n", "rxfc: bsts",
+		   rcar_canfd_read(priv, RCANFD_RFSTS(rf)));
+	seq_printf(s, "%-40s: %x\n", "rxfc: pctr",
+		   rcar_canfd_read(priv, RCANFD_RFPCTR(rf)));
+	seq_printf(s, "%-40s: %x\n", "rxfifo: sts",
+		   rcar_canfd_read(priv, RCANFD_F_RFFDSTS(rf)));
+	seq_printf(s, "%-40s: %x\n", "cmfc: cc",
+		   rcar_canfd_read(priv, RCANFD_CFCC(ch, cf)));
+	seq_printf(s, "%-40s: %x\n", "cmfc: bsts",
+		   rcar_canfd_read(priv, RCANFD_CFSTS(ch, cf)));
+	seq_printf(s, "%-40s: %x\n", "cmfc: pctr",
+		   rcar_canfd_read(priv, RCANFD_CFPCTR(ch, cf)));
+	seq_printf(s, "%-40s: %x\n", "cmfifo: sts",
+		   rcar_canfd_read(priv, RCANFD_F_CFFDCSTS(ch, cf)));
+	seq_printf(s, "%-40s: %x\n", "gtxintsts0",
+		   rcar_canfd_read(priv, RCANFD_GTINTSTS0));
+
+	seq_puts(s, "done\n");
+	return 0;
+}
+
+static int rcar_canfd_regs_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, rcar_canfd_showregs, inode->i_private);
+}
+
+static const struct file_operations rcar_canfd_regs_ops = {
+	.open = rcar_canfd_regs_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+void rcar_canfd_init_debugfs(struct rcar_canfd_channel *priv)
+{
+	struct dentry *dev_root;
+	struct net_device *ndev = priv->ndev;
+
+	dev_root = debugfs_create_dir(dev_name(&ndev->dev), NULL);
+	priv->dev_root = dev_root;
+
+	if (IS_ERR(dev_root) || !dev_root) {
+		netdev_warn(ndev,
+			    "failed to create debugfs dir for %s (ch %u)\n",
+			    dev_name(&ndev->dev), priv->channel);
+		return;
+	}
+	debugfs_create_file("dumpregs", S_IFREG | S_IRUGO, dev_root, priv,
+			    &rcar_canfd_regs_ops);
+}
+
+void rcar_canfd_remove_debugfs(struct rcar_canfd_channel *priv)
+{
+	debugfs_remove_recursive(priv->dev_root);
+}
+#else
+void rcar_canfd_init_debugfs(struct rcar_canfd_channel *priv)
+{
+}
+
+void rcar_canfd_remove_debugfs(struct rcar_canfd_channel *priv)
+{
+}
+#endif /* CONFIG_DEBUG_FS */
+
+static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
+{
+	u32 i;
+
+	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
+		can_free_echo_skb(ndev, i);
+}
+
+static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
+{
+	u32 sts, ch;
+	int err;
+
+	/* Check RAMINIT flag as CAN RAM initialization takes place
+	 * after the MCU reset
+	 */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 !(sts & RCANFD_GSTS_RAMINIT), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
+		return err;
+	}
+
+	/* Transition to Global Reset mode */
+	rcar_canfd_clear_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_SLPR);
+	rcar_canfd_update_bit(gpriv, RCANFD_GCTR,
+			      RCANFD_GCTR_MODEMASK, RCANFD_GCTR_GRESET);
+
+	/* Ensure Global reset mode */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 (sts & RCANFD_GSTS_RESET), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
+		return err;
+	}
+
+	/* Reset Global error flags */
+	rcar_canfd_write(gpriv, RCANFD_GERFL, 0x0);
+
+	/* Set the controller into FD mode */
+	rcar_canfd_set_bit(gpriv, RCANFD_GRMCFG, RCANFD_GINTF_CANFD);
+
+	/* Transition all Channels to reset mode */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_clear_bit(gpriv, RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
+
+		rcar_canfd_update_bit(gpriv, RCANFD_CCTR(ch),
+				      RCANFD_CCTR_MODEMASK,
+				      RCANFD_CCTR_CRESET);
+
+		/* Ensure Channel reset mode */
+		err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
+					 (sts & RCANFD_CSTS_RESET), 2, 500000);
+		if (err) {
+			dev_dbg(&gpriv->pdev->dev,
+				"channel %u reset failed\n", ch);
+			return err;
+		}
+	}
+	return 0;
+}
+
+static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
+{
+	u32 cfg, ch;
+
+	/* Global Configuration settings */
+	cfg = RCANFD_GCFG_EEFE;		/* ECC error flag enabled */
+
+	/* Set External Clock if selected */
+	if (gpriv->clock_select != RCANFD_CANFDCLK)
+		cfg |= RCANFD_GCFG_DCS;
+
+	/* Truncate payload to configured message size RFPLS */
+	cfg |= RCANFD_GCFG_CMPOC;
+
+	rcar_canfd_set_bit(gpriv, RCANFD_GCFG, cfg);
+
+	/* Channel configuration settings */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_set_bit(gpriv, RCANFD_CCTR(ch), RCANFD_CCTR_ERRD);
+		rcar_canfd_update_bit(gpriv, RCANFD_CCTR(ch),
+				      RCANFD_CCTR_BOMMASK,
+				      RCANFD_CCTR_BOM_ENTRY);
+	}
+}
+
+static int rcar_canfd_configure_selftest_mode(struct rcar_canfd_channel *priv)
+{
+	u32 sts, err;
+	u32 ch = priv->channel;
+
+	rcar_canfd_update_bit(priv, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_CHLT);
+
+	/* Verify channel mode change */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_HALT), 2, 500000);
+	if (err) {
+		netdev_dbg(priv->ndev, "channel halt failed\n");
+		return err;
+	}
+
+	/* Internal Selt Test mode */
+	rcar_canfd_update_bit(priv, RCANFD_CCTR(ch), RCANFD_CCTR_CTMASK,
+			      RCANFD_CCTR_CTMS_ILB);
+	rcar_canfd_set_bit(priv, RCANFD_CCTR(ch), RCANFD_CCTR_CTME);
+	return 0;
+}
+
+static int rcar_canfd_configure_interch_mode(struct rcar_canfd_global *gpriv)
+{
+	u32 sts;
+	int err;
+
+	rcar_canfd_update_bit(gpriv, RCANFD_GCTR,
+			      RCANFD_GCTR_MODEMASK, RCANFD_GCTR_GHLT);
+
+	/* Ensure Global Halt mode */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 (sts & RCANFD_GSTS_HLT), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global halt mode failed\n");
+		return err;
+	}
+
+	rcar_canfd_set_bit(gpriv, RCANFD_GTSTCFG,
+			   (RCANFD_GTSTCFG_C0CBCE | RCANFD_GTSTCFG_C1CBCE));
+	rcar_canfd_set_bit(gpriv, RCANFD_GTSTCTR, RCANFD_GTSTCTR_ICBCTME);
+
+	/* Verify inter-channel mode enabled */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GTSTCTR), sts,
+				 (sts & RCANFD_GTSTCTR_ICBCTME), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev,
+			"global inter-channel test mode failed\n");
+		return err;
+	}
+	return 0;
+}
+
+static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
+					   u32 ch)
+{
+	u32 cfg;
+	int start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	if (ch == 0) {
+		start = 0; /* Start from 0th rule */
+	} else {
+		/* Get number of existing rules and adjust */
+		cfg = rcar_canfd_read(gpriv, RCANFD_GAFLCFG0);
+		start = RCANFD_AFLCFG_GETRNC0(cfg);
+	}
+
+	/* Enable write access to entry */
+	page = RCANFD_AFL_PAGENUM(start);
+	rcar_canfd_set_bit(gpriv, RCANFD_GAFLECTR,
+			   (RCANFD_AFLCTR_AFLPN(page) | RCANFD_AFLCTR_AFLDAE));
+
+	/* Write number of rules for channel */
+	if (ch == 0)
+		rcar_canfd_set_bit(gpriv, RCANFD_GAFLCFG0,
+				   RCANFD_AFLCFG_SETRNC0(num_rules));
+	else
+		rcar_canfd_set_bit(gpriv, RCANFD_GAFLCFG0,
+				   RCANFD_AFLCFG_SETRNC1(num_rules));
+
+	/* Set the rule of that page */
+	if (testmode == RCANFD_TESTMODE_INTERNAL_LOOPBACK)
+		rcar_canfd_write(gpriv,
+				 RCANFD_GAFLID(RCANFD_F_GAFL_OFFSET, start),
+				 RCANFD_AFLID_GAFLLB);
+	else
+		/* Accept all IDs */
+		rcar_canfd_write(gpriv,
+				 RCANFD_GAFLID(RCANFD_F_GAFL_OFFSET, start), 0);
+
+	/* IDE or RTR is not considered for matching */
+	rcar_canfd_write(gpriv, RCANFD_GAFLM(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* Any data length accepted */
+	rcar_canfd_write(gpriv, RCANFD_GAFLP0(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* Place the msg in corresponding Rx FIFO entry */
+	rcar_canfd_write(gpriv, RCANFD_GAFLP1(RCANFD_F_GAFL_OFFSET, start),
+			 RCANFD_AFLPTR1_RFFIFO(ridx));
+
+	/* Disable write access to page */
+	rcar_canfd_clear_bit(gpriv, RCANFD_GAFLECTR, RCANFD_AFLCTR_AFLDAE);
+}
+
+static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	/* Rx FIFO is used for reception */
+	u32 cfg;
+	u16 rfdc, rfpls;
+
+	/* Select Rx FIFO based on channel */
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	rfdc = 2;		/* b010 - 8 messages Rx FIFO depth */
+	rfpls = 7;		/* b111 - Max 64 bytes payload */
+
+	cfg = (RCANFD_RFFIFO_RFIM | RCANFD_RFFIFO_RFDC(rfdc) |
+		RCANFD_RFFIFO_RFPLS(rfpls) | RCANFD_RFFIFO_RFIE);
+	rcar_canfd_write(gpriv, RCANFD_RFCC(ridx), cfg);
+}
+
+static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	/* Tx/Rx(Common) FIFO configured in Tx mode is
+	 * used for transmission
+	 *
+	 * Each channel has 3 Common FIFO dedicated to them.
+	 * Use the 1st (index 0) out of 3
+	 */
+	u32 cfg;
+	u16 cftml, cfm, cfdc, cfpls;
+
+	cftml = 0;		/* 0th buffer */
+	cfm = 1;		/* b01 - Transmit mode */
+	cfdc = 2;		/* b010 - 8 messages Tx FIFO depth */
+	cfpls = 7;		/* b111 - Max 64 bytes payload */
+
+	cfg = (RCANFD_CMFIFO_TML(cftml) | RCANFD_CMFIFO_M(cfm) |
+		RCANFD_CMFIFO_CFIM | RCANFD_CMFIFO_DC(cfdc) |
+		RCANFD_CMFIFO_PLS(cfpls) | RCANFD_CMFIFO_CFTXIE);
+	rcar_canfd_write(gpriv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
+
+	/* Clear FD mode specific control/status register */
+	rcar_canfd_write(gpriv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
+}
+
+static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
+{
+	u32 ctr;
+
+	/* Clear any stray error interrupt flags */
+	rcar_canfd_write(gpriv, RCANFD_GERFL, 0);
+
+	/* Global interrupts setup */
+	ctr = RCANFD_GCTR_MEIE;
+	ctr |= RCANFD_GCTR_CFMPOFIE;
+
+	rcar_canfd_set_bit(gpriv, RCANFD_GCTR, ctr);
+}
+
+static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
+						 *gpriv)
+{
+	/* Disable all interrupts */
+	rcar_canfd_write(gpriv, RCANFD_GCTR, 0);
+
+	/* Clear any stray error interrupt flags */
+	rcar_canfd_write(gpriv, RCANFD_GERFL, 0);
+}
+
+static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
+						 *priv)
+{
+	u32 ctr, ch = priv->channel;
+
+	/* Clear any stray error flags */
+	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
+
+	/* Channel interrupts setup */
+	ctr = (RCANFD_CCTR_TAIE |
+	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
+	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
+	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
+	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
+	rcar_canfd_set_bit(priv, RCANFD_CCTR(ch), ctr);
+}
+
+static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
+						  *priv)
+{
+	u32 ctr, ch = priv->channel;
+
+	ctr = (RCANFD_CCTR_TAIE |
+	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
+	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
+	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
+	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
+	rcar_canfd_clear_bit(priv, RCANFD_CCTR(ch), ctr);
+
+	/* Clear any stray error flags */
+	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
+}
+
+static void rcar_canfd_global_error(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 ch = priv->channel;
+	u32 gerfl, sts;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	gerfl = rcar_canfd_read(priv, RCANFD_GERFL);
+	if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
+		netdev_dbg(ndev, "Ch0: ECC Error flag\n");
+		stats->tx_dropped++;
+	}
+	if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
+		netdev_dbg(ndev, "Ch1: ECC Error flag\n");
+		stats->tx_dropped++;
+	}
+	if (gerfl & RCANFD_GERFL_MES) {
+		sts = rcar_canfd_read(priv,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		if (sts & RCANFD_CMFIFO_CFMLT) {
+			netdev_dbg(ndev, "Tx Message Lost flag\n");
+			stats->tx_dropped++;
+			rcar_canfd_write(priv,
+					 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
+					 sts & ~RCANFD_CMFIFO_CFMLT);
+		}
+
+		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
+		if (sts & RCANFD_RFFIFO_RFMLT) {
+			netdev_dbg(ndev, "Rx Message Lost flag\n");
+			stats->rx_dropped++;
+			rcar_canfd_write(priv, RCANFD_RFSTS(ridx),
+					 sts & ~RCANFD_RFFIFO_RFMLT);
+		}
+	}
+	if (gerfl & RCANFD_GERFL_CMPOF) {
+		/* Message Lost flag will be set for respective channel
+		 * when this condition happens with counters and flags
+		 * already updated.
+		 */
+		netdev_dbg(ndev, "global payload overflow interrupt\n");
+	}
+
+	/* Clear all global error interrupts. Only affected channels bits
+	 * get cleared
+	 */
+	rcar_canfd_write(priv, RCANFD_GERFL, 0);
+}
+
+static void rcar_canfd_error(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	struct can_frame *cf;
+	struct sk_buff *skb;
+	u32 cerfl, csts;
+	u32 txerr = 0, rxerr = 0;
+	u32 ch = priv->channel;
+
+	/* Propagate the error condition to the CAN stack */
+	skb = alloc_can_err_skb(ndev, &cf);
+	if (!skb) {
+		stats->rx_dropped++;
+		return;
+	}
+
+	/* Channel error interrupt */
+	cerfl = rcar_canfd_read(priv, RCANFD_CERFL(ch));
+	csts = rcar_canfd_read(priv, RCANFD_CSTS(ch));
+	txerr = RCANFD_CSTS_TECCNT(csts);
+	rxerr = RCANFD_CSTS_RECCNT(csts);
+
+	netdev_dbg(ndev, "ch erfl %x sts %x txerr %u rxerr %u\n",
+		   cerfl, csts, txerr, rxerr);
+
+	if (cerfl & RCANFD_CERFL_BEF) {
+		netdev_dbg(ndev, "Bus error\n");
+		cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
+		cf->data[2] = CAN_ERR_PROT_UNSPEC;
+		priv->can.can_stats.bus_error++;
+	}
+	if (cerfl & RCANFD_CERFL_ADEF) {
+		netdev_dbg(ndev, "ACK Delimiter Error\n");
+		stats->tx_errors++;
+		cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
+	}
+	if (cerfl & RCANFD_CERFL_B0EF) {
+		netdev_dbg(ndev, "Bit Error (dominant)\n");
+		stats->tx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_BIT0;
+	}
+	if (cerfl & RCANFD_CERFL_B1EF) {
+		netdev_dbg(ndev, "Bit Error (recessive)\n");
+		stats->tx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_BIT1;
+	}
+	if (cerfl & RCANFD_CERFL_CEF) {
+		netdev_dbg(ndev, "CRC Error\n");
+		stats->rx_errors++;
+		cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
+	}
+	if (cerfl & RCANFD_CERFL_AEF) {
+		netdev_dbg(ndev, "ACK Error\n");
+		stats->tx_errors++;
+		cf->can_id |= CAN_ERR_ACK;
+		cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
+	}
+	if (cerfl & RCANFD_CERFL_FEF) {
+		netdev_dbg(ndev, "Form Error\n");
+		stats->rx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_FORM;
+	}
+	if (cerfl & RCANFD_CERFL_SEF) {
+		netdev_dbg(ndev, "Stuff Error\n");
+		stats->rx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_STUFF;
+	}
+	if (cerfl & RCANFD_CERFL_ALEF) {
+		netdev_dbg(ndev, "Arbitration lost Error\n");
+		priv->can.can_stats.arbitration_lost++;
+		cf->can_id |= CAN_ERR_LOSTARB;
+		cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
+	}
+	if (cerfl & RCANFD_CERFL_BLEF) {
+		netdev_dbg(ndev, "Bus Lock Error\n");
+		stats->rx_errors++;
+		cf->can_id |= CAN_ERR_BUSERROR;
+	}
+	if (cerfl & RCANFD_CERFL_EWEF) {
+		netdev_dbg(ndev, "Error warning interrupt\n");
+		priv->can.state = CAN_STATE_ERROR_WARNING;
+		priv->can.can_stats.error_warning++;
+		cf->can_id |= CAN_ERR_CRTL;
+		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
+			CAN_ERR_CRTL_RX_WARNING;
+		cf->data[6] = txerr;
+		cf->data[7] = rxerr;
+	}
+	if (cerfl & RCANFD_CERFL_EPEF) {
+		netdev_dbg(ndev, "Error passive interrupt\n");
+		priv->can.state = CAN_STATE_ERROR_PASSIVE;
+		priv->can.can_stats.error_passive++;
+		cf->can_id |= CAN_ERR_CRTL;
+		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
+			CAN_ERR_CRTL_RX_PASSIVE;
+		cf->data[6] = txerr;
+		cf->data[7] = rxerr;
+	}
+	if (cerfl & RCANFD_CERFL_BOEEF) {
+		netdev_dbg(ndev, "Bus-off entry interrupt\n");
+		rcar_canfd_tx_failure_cleanup(ndev);
+		priv->can.state = CAN_STATE_BUS_OFF;
+		priv->can.can_stats.bus_off++;
+		can_bus_off(ndev);
+		cf->can_id |= CAN_ERR_BUSOFF;
+	}
+	if (cerfl & RCANFD_CERFL_OLEF) {
+		netdev_dbg(ndev,
+			   "Overload Frame Transmission error interrupt\n");
+		stats->tx_errors++;
+		cf->can_id |= CAN_ERR_PROT;
+		cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
+	}
+
+	/* Clear all channel error interrupts */
+	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
+	stats->rx_packets++;
+	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
+}
+
+static void rcar_canfd_tx_done(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 sts;
+	u32 ch = priv->channel;
+
+	while (1) {
+		u8 unsent;
+
+		sts = rcar_canfd_read(priv,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		unsent = RCANFD_CMFIFO_CFMC(sts);
+
+		if (priv->tx_head - priv->tx_tail <= unsent)
+			break;
+
+		stats->tx_packets++;
+		stats->tx_bytes += priv->tx_len[priv->tx_tail %
+						RCANFD_FIFO_DEPTH];
+		priv->tx_len[priv->tx_tail % RCANFD_FIFO_DEPTH] = 0;
+		can_get_echo_skb(ndev, priv->tx_tail % RCANFD_FIFO_DEPTH);
+		priv->tx_tail++;
+		netif_wake_queue(ndev);
+	}
+
+	/* Clear interrupt */
+	rcar_canfd_write(priv, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
+			 sts & ~RCANFD_CMFIFO_CFTXIF);
+	can_led_event(ndev, CAN_LED_EVENT_TX);
+}
+
+static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
+{
+	struct rcar_canfd_global *gpriv = dev_id;
+	struct net_device *ndev;
+	struct rcar_canfd_channel *priv;
+	u32 sts, gerfl;
+	u32 ch, ridx;
+
+	/* Global error interrupts still indicate a condition specific
+	 * to a channel. RxFIFO interrupt is a global interrupt.
+	 */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		ndev = priv->ndev;
+		ridx = ch + RCANFD_RFFIFO_IDX;
+
+		/* Global error interrupts */
+		gerfl = rcar_canfd_read(priv, RCANFD_GERFL);
+		if (RCANFD_GERFL_ERR(gerfl))
+			rcar_canfd_global_error(ndev);
+
+		/* Handle Rx interrupts */
+		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
+		if (sts & RCANFD_RFFIFO_RFIF) {
+			if (napi_schedule_prep(&priv->napi)) {
+				/* Disable Rx FIFO interrupts */
+				rcar_canfd_clear_bit(priv,
+						     RCANFD_RFCC(ridx),
+						     RCANFD_RFFIFO_RFIE);
+				__napi_schedule(&priv->napi);
+			}
+		}
+	}
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
+{
+	struct rcar_canfd_global *gpriv = dev_id;
+	struct net_device *ndev;
+	struct rcar_canfd_channel *priv;
+	u32 sts, cerfl, ch;
+
+	/* Common FIFO is a per channel resource */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		ndev = priv->ndev;
+
+		/* Channel error interrupts */
+		cerfl = rcar_canfd_read(priv, RCANFD_CERFL(ch));
+		if (RCANFD_CERFL_ERR(cerfl))
+			rcar_canfd_error(ndev);
+
+		/* Handle Tx interrupts */
+		sts = rcar_canfd_read(priv,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		if (sts & RCANFD_CMFIFO_CFTXIF)
+			rcar_canfd_tx_done(ndev);
+	}
+	return IRQ_HANDLED;
+}
+
+static void rcar_canfd_set_bittiming(struct net_device *dev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(dev);
+	const struct can_bittiming *bt = &priv->can.bittiming;
+	const struct can_bittiming *dbt = &priv->can.data_bittiming;
+	u16 brp, sjw, tseg1, tseg2;
+	u32 cfg;
+	u32 ch = priv->channel;
+
+	/* Nominal bit timing settings */
+	brp = bt->brp - 1;
+	sjw = bt->sjw - 1;
+	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
+	tseg2 = bt->phase_seg2 - 1;
+
+	cfg = (RCANFD_NR_TSEG1(tseg1) | RCANFD_NR_BRP(brp) |
+	       RCANFD_NR_SJW(sjw) | RCANFD_NR_TSEG2(tseg2));
+
+	rcar_canfd_write(priv, RCANFD_CCFG(ch), cfg);
+	netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
+		   brp, sjw, tseg1, tseg2);
+
+	/* Data bit timing settings */
+	brp = dbt->brp - 1;
+	sjw = dbt->sjw - 1;
+	tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
+	tseg2 = dbt->phase_seg2 - 1;
+
+	cfg = (RCANFD_DR_TSEG1(tseg1) | RCANFD_DR_BRP(brp) |
+	       RCANFD_DR_SJW(sjw) | RCANFD_DR_TSEG2(tseg2));
+
+	rcar_canfd_write(priv, RCANFD_F_CDFG(ch), cfg);
+	netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
+		   brp, sjw, tseg1, tseg2);
+}
+
+static int rcar_canfd_start(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	int err = -EOPNOTSUPP;
+	u32 sts, ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	/* Ensure channel starts in FD mode */
+	if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
+		netdev_err(ndev, "enable can fd mode for channel %d\n", ch);
+		goto fail_mode;
+	}
+
+	rcar_canfd_set_bittiming(ndev);
+
+	rcar_canfd_enable_channel_interrupts(priv);
+
+	if (testmode == RCANFD_TESTMODE_INTERNAL_LOOPBACK) {
+		/* Enable self test mode */
+		err = rcar_canfd_configure_selftest_mode(priv);
+		if (err) {
+			netdev_err(ndev,
+				   "channel %u self-test mode failed\n", ch);
+			goto fail_mode_change;
+		}
+	}
+
+	/* Set channel to Operational mode */
+	rcar_canfd_update_bit(priv, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_COPM);
+
+	/* Verify channel mode change */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_COM), 2, 500000);
+	if (err) {
+		netdev_err(ndev, "channel %u communication state failed\n", ch);
+		goto fail_mode_change;
+	}
+
+	/* Enable Common & Rx FIFO */
+	rcar_canfd_set_bit(priv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
+			   RCANFD_CMFIFO_CFE);
+	rcar_canfd_set_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFE);
+
+	priv->can.state = CAN_STATE_ERROR_ACTIVE;
+	return 0;
+
+fail_mode_change:
+	rcar_canfd_disable_channel_interrupts(priv);
+fail_mode:
+	return err;
+}
+
+static int rcar_canfd_open(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct rcar_canfd_global *gpriv = priv->gpriv;
+	int err;
+
+	/* Peripheral clock is already enabled in probe */
+	err = clk_prepare_enable(gpriv->can_clk);
+	if (err) {
+		netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
+		goto out_clock;
+	}
+
+	err = open_candev(ndev);
+	if (err) {
+		netdev_err(ndev, "open_candev() failed, error %d\n", err);
+		goto out_can_clock;
+	}
+
+	napi_enable(&priv->napi);
+	err = rcar_canfd_start(ndev);
+	if (err)
+		goto out_close;
+	netif_start_queue(ndev);
+	can_led_event(ndev, CAN_LED_EVENT_OPEN);
+	return 0;
+out_close:
+	napi_disable(&priv->napi);
+	close_candev(ndev);
+out_can_clock:
+	clk_disable_unprepare(gpriv->can_clk);
+out_clock:
+	return err;
+}
+
+static void rcar_canfd_stop(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	int err;
+	u32 sts, ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	/* Transition to channel reset mode  */
+	rcar_canfd_update_bit(priv, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_CRESET);
+
+	/* Check Channel reset mode */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_RESET), 2, 500000);
+	if (err)
+		netdev_err(ndev, "channel %u reset failed\n", ch);
+
+	rcar_canfd_disable_channel_interrupts(priv);
+
+	/* Disable Common & Rx FIFO */
+	rcar_canfd_clear_bit(priv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
+			     RCANFD_CMFIFO_CFE);
+	rcar_canfd_clear_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFE);
+
+	/* Set the state as STOPPED */
+	priv->can.state = CAN_STATE_STOPPED;
+}
+
+static int rcar_canfd_close(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct rcar_canfd_global *gpriv = priv->gpriv;
+
+	netif_stop_queue(ndev);
+	rcar_canfd_stop(ndev);
+	napi_disable(&priv->napi);
+	clk_disable_unprepare(gpriv->can_clk);
+	close_candev(ndev);
+	can_led_event(ndev, CAN_LED_EVENT_STOP);
+	return 0;
+}
+
+static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
+					 struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
+	u32 sts, id, ptr;
+	u32 ch = priv->channel;
+
+	if (can_dropped_invalid_skb(ndev, skb))
+		return NETDEV_TX_OK;
+
+	if (cf->can_id & CAN_EFF_FLAG) {
+		id = cf->can_id & CAN_EFF_MASK;
+		id |= RCANFD_CMFIFO_CFIDE;
+	} else {
+		id = cf->can_id & CAN_SFF_MASK;
+	}
+
+	if (cf->can_id & CAN_RTR_FLAG)
+		id |= RCANFD_CMFIFO_CFRTR;
+
+	rcar_canfd_write(priv, RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX),
+			 id);
+	ptr = RCANFD_CMFIFO_CFDLC(can_len2dlc(cf->len));
+	rcar_canfd_write(priv, RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX),
+			 ptr);
+
+	rcar_canfd_put_data(cf, priv,
+			    RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
+
+	priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
+	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
+	priv->tx_head++;
+
+	sts = rcar_canfd_read(priv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX));
+	if (can_is_canfd_skb(skb)) {
+		/* CAN FD frame format */
+		sts |= RCANFD_CMFIFO_CFFDF;
+		if (cf->flags & CANFD_BRS)
+			sts |= RCANFD_CMFIFO_CFBRS;
+		else
+			sts &= ~RCANFD_CMFIFO_CFBRS;
+	} else {
+		sts &= ~RCANFD_CMFIFO_CFFDF;
+	}
+	rcar_canfd_write(priv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), sts);
+
+	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
+	 * pointer for the Common FIFO
+	 */
+	rcar_canfd_write(priv, RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
+
+	/* Stop the queue if we've filled all FIFO entries */
+	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
+		netif_stop_queue(ndev);
+	return NETDEV_TX_OK;
+}
+
+static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
+{
+	struct net_device_stats *stats = &priv->ndev->stats;
+	struct canfd_frame *cf;
+	struct sk_buff *skb;
+	u32 sts = 0, id, ptr;
+	u32 ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	id = rcar_canfd_read(priv, RCANFD_F_RFID(ridx));
+	ptr = rcar_canfd_read(priv, RCANFD_F_RFPTR(ridx));
+
+	sts = rcar_canfd_read(priv, RCANFD_F_RFFDSTS(ridx));
+	if (sts & RCANFD_RFFIFO_RFFDF)
+		skb = alloc_canfd_skb(priv->ndev, &cf);
+	else
+		skb = alloc_can_skb(priv->ndev,
+				    (struct can_frame **)&cf);
+
+	if (!skb) {
+		stats->rx_dropped++;
+		return;
+	}
+
+	if (sts & RCANFD_RFFIFO_RFFDF)
+		cf->len = can_dlc2len(RCANFD_RFFIFO_RFDLC(ptr));
+	else
+		cf->len = get_can_dlc(RCANFD_RFFIFO_RFDLC(ptr));
+
+	if (sts & RCANFD_RFFIFO_RFESI) {
+		cf->flags |= CANFD_ESI;
+		netdev_dbg(priv->ndev, "ESI Error\n");
+	}
+
+	if (id & RCANFD_RFFIFO_RFIDE)
+		cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+	else
+		cf->can_id = id & CAN_SFF_MASK;
+
+	if (!(sts & RCANFD_RFFIFO_RFFDF) && (id & RCANFD_RFFIFO_RFRTR)) {
+		cf->can_id |= CAN_RTR_FLAG;
+	} else {
+		if (sts & RCANFD_RFFIFO_RFBRS)
+			cf->flags |= CANFD_BRS;
+
+		rcar_canfd_get_data(cf, priv, RCANFD_F_RFDF(ridx, 0));
+	}
+
+	/* Write 0xff to RFPC to increment the CPU-side
+	 * pointer of the Rx FIFO
+	 */
+	rcar_canfd_write(priv, RCANFD_RFPCTR(ridx), 0xff);
+
+	can_led_event(priv->ndev, CAN_LED_EVENT_RX);
+
+	stats->rx_bytes += cf->len;
+	stats->rx_packets++;
+	netif_receive_skb(skb);
+}
+
+static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
+{
+	struct rcar_canfd_channel *priv =
+		container_of(napi, struct rcar_canfd_channel, napi);
+	int num_pkts;
+	u32 sts;
+	u32 ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
+		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
+		/* Clear interrupt bit */
+		if (sts & RCANFD_RFFIFO_RFIF)
+			rcar_canfd_write(priv, RCANFD_RFSTS(ridx),
+					 sts & ~RCANFD_RFFIFO_RFIF);
+
+		/* Check FIFO empty condition */
+		if (sts & RCANFD_RFFIFO_RFEMP)
+			break;
+
+		rcar_canfd_rx_pkt(priv);
+	}
+
+	/* All packets processed */
+	if (num_pkts < quota) {
+		napi_complete(napi);
+		/* Enable Rx FIFO interrupts */
+		rcar_canfd_set_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFIE);
+	}
+	return num_pkts;
+}
+
+static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
+{
+	int err;
+
+	switch (mode) {
+	case CAN_MODE_START:
+		err = rcar_canfd_start(ndev);
+		if (err)
+			return err;
+		netif_wake_queue(ndev);
+		return 0;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int rcar_canfd_get_berr_counter(const struct net_device *dev,
+				       struct can_berr_counter *bec)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(dev);
+	u32 val, ch = priv->channel;
+
+	/* Peripheral clock is already enabled in probe */
+	val = rcar_canfd_read(priv, RCANFD_CSTS(ch));
+	bec->txerr = RCANFD_CSTS_TECCNT(val);
+	bec->rxerr = RCANFD_CSTS_RECCNT(val);
+	return 0;
+}
+
+static const struct net_device_ops rcar_canfd_netdev_ops = {
+	.ndo_open = rcar_canfd_open,
+	.ndo_stop = rcar_canfd_close,
+	.ndo_start_xmit = rcar_canfd_start_xmit,
+	.ndo_change_mtu = can_change_mtu,
+};
+
+static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	struct platform_device *pdev = gpriv->pdev;
+	struct rcar_canfd_channel *priv;
+	struct net_device *ndev;
+	int err = -ENODEV;
+
+	ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
+	if (!ndev) {
+		dev_err(&pdev->dev, "alloc_candev() failed\n");
+		err = -ENOMEM;
+		goto fail;
+	}
+	priv = netdev_priv(ndev);
+
+	ndev->netdev_ops = &rcar_canfd_netdev_ops;
+	ndev->flags |= IFF_ECHO;
+	priv->ndev = ndev;
+	priv->base = gpriv->base;
+	priv->channel = ch;
+	priv->can.clock.freq = gpriv->freq;
+	dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
+
+	priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
+	priv->can.data_bittiming_const =
+		&rcar_canfd_data_bittiming_const;
+
+	/* Controller starts in CAN FD mode, which supports classical CAN and
+	 * CAN FD frames. For classical CAN frames only configurations, data
+	 * bitrate should be configured the same as nominal bitrate.
+	 */
+	priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
+		CAN_CTRLMODE_FD;
+
+	priv->can.do_set_mode = rcar_canfd_do_set_mode;
+	priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
+	priv->gpriv = gpriv;
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+
+	netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
+		       RCANFD_NAPI_WEIGHT);
+	err = register_candev(ndev);
+	if (err) {
+		dev_err(&pdev->dev,
+			"register_candev() failed, error %d\n", err);
+		goto fail_candev;
+	}
+
+	rcar_canfd_init_debugfs(priv);
+	devm_can_led_init(ndev);
+	gpriv->ch[priv->channel] = priv;
+	dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
+	return 0;
+
+fail_candev:
+	netif_napi_del(&priv->napi);
+	free_candev(ndev);
+fail:
+	return err;
+}
+
+static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	struct rcar_canfd_channel *priv = gpriv->ch[ch];
+
+	if (priv) {
+		unregister_candev(priv->ndev);
+		netif_napi_del(&priv->napi);
+		free_candev(priv->ndev);
+	}
+}
+
+static int rcar_canfd_probe(struct platform_device *pdev)
+{
+	struct resource *mem;
+	void __iomem *addr;
+	u32 sts, ch;
+	struct rcar_canfd_global *gpriv;
+	struct device_node *of_child;
+	unsigned long channels_mask = 0;
+	int err, ch_irq, g_irq;
+
+	of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
+	if (of_child && of_device_is_available(of_child))
+		channels_mask |= BIT(0);	/* Channel 0 */
+
+	of_child = of_get_child_by_name(pdev->dev.of_node, "channel1");
+	if (of_child && of_device_is_available(of_child))
+		channels_mask |= BIT(1);	/* Channel 1 */
+
+	ch_irq = platform_get_irq(pdev, 0);
+	if (ch_irq < 0) {
+		dev_err(&pdev->dev, "no Channel IRQ resource\n");
+		err = ch_irq;
+		goto fail_dev;
+	}
+
+	g_irq = platform_get_irq(pdev, 1);
+	if (g_irq < 0) {
+		dev_err(&pdev->dev, "no Global IRQ resource\n");
+		err = g_irq;
+		goto fail_dev;
+	}
+
+	/* Global controller context */
+	gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
+	if (!gpriv) {
+		err = -ENOMEM;
+		goto fail_dev;
+	}
+	gpriv->pdev = pdev;
+	gpriv->channels_mask = channels_mask;
+
+	/* Peripheral clock */
+	gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
+	if (IS_ERR(gpriv->clkp)) {
+		err = PTR_ERR(gpriv->clkp);
+		dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
+			err);
+		goto fail_dev;
+	}
+
+	/* fCAN clock: Pick External clock. If not available fallback to
+	 * CANFD clock
+	 */
+	gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
+	if (IS_ERR(gpriv->can_clk)) {
+		gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
+		if (IS_ERR(gpriv->can_clk)) {
+			err = PTR_ERR(gpriv->can_clk);
+			dev_err(&pdev->dev,
+				"cannot get canfd clock, error %d\n", err);
+			goto fail_dev;
+		}
+		gpriv->clock_select = RCANFD_CANFDCLK;
+
+	} else {
+		gpriv->clock_select = RCANFD_EXTCLK;
+	}
+	gpriv->freq = clk_get_rate(gpriv->can_clk);
+
+	if (gpriv->clock_select == RCANFD_CANFDCLK)
+		/* CANFD clock is further divided by (1/2) within the IP */
+		gpriv->freq /= 2;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	addr = devm_ioremap_resource(&pdev->dev, mem);
+	if (IS_ERR(addr)) {
+		err = PTR_ERR(addr);
+		goto fail_dev;
+	}
+	gpriv->base = addr;
+
+	/* Request IRQ that's common for both channels */
+	err = devm_request_irq(&pdev->dev, ch_irq,
+			       rcar_canfd_channel_interrupt, 0,
+			       "canfd.chn", gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+			ch_irq, err);
+		goto fail_dev;
+	}
+	err = devm_request_irq(&pdev->dev, g_irq,
+			       rcar_canfd_global_interrupt, 0,
+			       "canfd.gbl", gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+			g_irq, err);
+		goto fail_dev;
+	}
+
+	/* Enable peripheral clock for register access */
+	err = clk_prepare_enable(gpriv->clkp);
+	if (err) {
+		dev_err(&pdev->dev,
+			"failed to enable peripheral clock, error %d\n", err);
+		goto fail_dev;
+	}
+
+	err = rcar_canfd_reset_controller(gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "reset controller failed\n");
+		goto fail_clk;
+	}
+
+	/* Controller in Global reset & Channel reset mode */
+	rcar_canfd_configure_controller(gpriv);
+
+	/* Configure per channel attributes */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		/* Configure Channel's Rx fifo */
+		rcar_canfd_configure_rx(gpriv, ch);
+
+		/* Configure Channel's Tx (Common) fifo */
+		rcar_canfd_configure_tx(gpriv, ch);
+
+		/* Configure receive rules */
+		rcar_canfd_configure_afl_rules(gpriv, ch);
+	}
+
+	/* Configure inter-channel test mode when both channels enabled */
+	if ((testmode == RCANFD_TESTMODE_INTERCHANNEL) &&
+	    (gpriv->channels_mask == RCANFD_CHANNELS_MASK)) {
+		err = rcar_canfd_configure_interch_mode(gpriv);
+		if (err)
+			goto fail_clk;
+	}
+
+	/* Configure common interrupts */
+	rcar_canfd_enable_global_interrupts(gpriv);
+
+	/* Start Global operation mode */
+	rcar_canfd_update_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_MODEMASK,
+			      RCANFD_GCTR_GOPM);
+
+	/* Verify mode change */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
+	if (err) {
+		dev_err(&pdev->dev, "global operational mode failed\n");
+		goto fail_mode;
+	}
+
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		err = rcar_canfd_channel_probe(gpriv, ch);
+		if (err)
+			goto fail_channel;
+	}
+
+	platform_set_drvdata(pdev, gpriv);
+	if (testmode)
+		dev_info(&pdev->dev, "in %s test mode\n",
+			 (testmode == RCANFD_TESTMODE_INTERNAL_LOOPBACK) ?
+			 "internal loopback" : "inter-channel");
+
+	dev_info(&pdev->dev, "global operational state (clk %d)\n",
+		 gpriv->clock_select);
+	return 0;
+
+fail_channel:
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+		rcar_canfd_channel_remove(gpriv, ch);
+fail_mode:
+	rcar_canfd_disable_global_interrupts(gpriv);
+fail_clk:
+	clk_disable_unprepare(gpriv->clkp);
+fail_dev:
+	return err;
+}
+
+static int rcar_canfd_remove(struct platform_device *pdev)
+{
+	struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
+	struct rcar_canfd_channel *priv;
+	u32 ch;
+
+	rcar_canfd_reset_controller(gpriv);
+	rcar_canfd_disable_global_interrupts(gpriv);
+
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		if (priv) {
+			rcar_canfd_disable_channel_interrupts(priv);
+			rcar_canfd_remove_debugfs(priv);
+			unregister_candev(priv->ndev);
+			netif_napi_del(&priv->napi);
+			free_candev(priv->ndev);
+		}
+	}
+
+	/* Enter global sleep mode */
+	rcar_canfd_set_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_SLPR);
+	clk_disable_unprepare(gpriv->clkp);
+	return 0;
+}
+
+static int __maybe_unused rcar_canfd_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int __maybe_unused rcar_canfd_resume(struct device *dev)
+{
+	return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
+			 rcar_canfd_resume);
+
+static const struct of_device_id rcar_canfd_of_table[] __maybe_unused = {
+	{ .compatible = "renesas,rcar-gen3-canfd" },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
+
+static struct platform_driver rcar_canfd_driver = {
+	.driver = {
+		.name = RCANFD_DRV_NAME,
+		.of_match_table = of_match_ptr(rcar_canfd_of_table),
+		.pm = &rcar_canfd_pm_ops,
+	},
+	.probe = rcar_canfd_probe,
+	.remove = rcar_canfd_remove,
+};
+
+module_platform_driver(rcar_canfd_driver);
+
+MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
+MODULE_ALIAS("platform:" RCANFD_DRV_NAME);
-- 
1.9.1

Re: [PATCH] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Marc Kleine-Budde]

[-- Attachment #1: Type: text/plain, Size: 2177 bytes --]

On 03/01/2016 10:34 AM, Ramesh Shanmugasundaram wrote:
> This patch adds support for the CAN FD controller found in Renesas R-Car
> SoCs. The controller operates in CAN FD mode by default. Two test modes
> are available and can be enabled by the "rcar_canfd.testmode" module
> parameter. Refer to Documentation/kernel-parameters.txt.

Is the channel loopback mode configurable per channel? If so, please
remove the module parameter and make use of CAN_CTRLMODE_LOOPBACK to
configure it.

> CAN FD mode supports both Classical CAN & CAN FD frame formats. The
> controller supports ISO 11898-1:2015 CAN FD format only.
> 
> This controller supports two channels and the driver can enable either
> or both of the channels.
> 
> Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs (one
> per channel) for transmission. Rx filter rules are configured to the
> minimum (one per channel) and it accepts Standard, Extended, Data &
> Remote Frame combinations.

I see no locking for the tx-path.

> Note: There are few documentation errors in R-Car Gen3 Hardware User
> Manual v0.5E with respect to CAN FD controller. They are listed below:
> 
> 1. CAN FD interrupt numbers 29 & 30 are listed as per channel
> interrupts. However, they are common to both channels (i.e.) they are
> global and channel interrupts respectively.
> 
> 2. CANFD clock is derived from PLL1. This is not documented.
> 
> 3. CANFD clock is further divided by (1/2) within the CAN FD controller.
> This is not documented.
> 
> 4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
> is mentioned 4 Tq in the manual.
> 
> 5. The maximum number of message RAM area the controller can use is 3584
> bytes. It is mentioned 10752 bytes in the manual.
> 
> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram-+3GIUL1IS+U@public.gmane.orgsas.com>

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
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Re: [PATCH] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Oliver Hartkopp]

On 03/01/2016 10:34 AM, Ramesh Shanmugasundaram wrote:
> This patch adds support for the CAN FD controller found in Renesas R-Car
> SoCs. The controller operates in CAN FD mode by default. Two test modes
> are available and can be enabled by the "rcar_canfd.testmode" module
> parameter. Refer to Documentation/kernel-parameters.txt.

(..)

> +#ifdef CONFIG_DEBUG_FS
> +#include <linux/debugfs.h>
> +
> +static int rcar_canfd_showregs(struct seq_file *s, void *data)
> +{
> +	struct rcar_canfd_channel *priv = s->private;
> +	u32 ch = priv->channel;
> +	u32 rf = ch + RCANFD_RFFIFO_IDX;
> +	u32 cf = RCANFD_CFFIFO_IDX;
> +	u32 val, offset, i;
> +
> +	if (testmode)
> +		seq_printf(s, "RCANFD : testmode = %d\n", testmode);
> +	seq_printf(s, "RCANFD register dump: channel %u\n", ch);
> +	seq_printf(s, "%-40s: %x\n", "g: cfg",
> +		   rcar_canfd_read(priv, RCANFD_GCFG));

Why do you think you would need this kind of register dumps in debugfs?

This could be interesting for development purposes - but in production drivers
this is pretty unusual and needless.

I would sugest to remove either the testmode (already suggested by Marc) and
this register dump stuff.

Regards,
Oliver

RE: [PATCH] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Marc,

Thanks for the review.

> On 03/01/2016 10:34 AM, Ramesh Shanmugasundaram wrote:
> > This patch adds support for the CAN FD controller found in Renesas
> > R-Car SoCs. The controller operates in CAN FD mode by default. Two
> > test modes are available and can be enabled by the
> > "rcar_canfd.testmode" module parameter. Refer to Documentation/kernel-
> parameters.txt.
> 
> Is the channel loopback mode configurable per channel? If so, please
> remove the module parameter and make use of CAN_CTRLMODE_LOOPBACK to
> configure it.

The loopback setting is not truly a per channel attribute. It requires touching Rx rules which can be done only when the controller's global state is reset (during probe). CAN_CTRLMODE_LOOPBACK config option is possible only through .ndo_open of that channel but the global controller state needs to be operational by this time. As it is a global attribute & for the above reason, I choose the module option.

> 
> > CAN FD mode supports both Classical CAN & CAN FD frame formats. The
> > controller supports ISO 11898-1:2015 CAN FD format only.
> >
> > This controller supports two channels and the driver can enable either
> > or both of the channels.
> >
> > Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs
> > (one per channel) for transmission. Rx filter rules are configured to
> > the minimum (one per channel) and it accepts Standard, Extended, Data
> > & Remote Frame combinations.
> 
> I see no locking for the tx-path.
 
I am not sure why locking is needed in tx-path? 
However, looking at it again, I should move the incrementing of head after the "sts" handing to be apt. What do you think?

Thanks,
Ramesh

RE: [PATCH] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Oliver,

Thanks for the review.

> On 03/01/2016 10:34 AM, Ramesh Shanmugasundaram wrote:
> > This patch adds support for the CAN FD controller found in Renesas
> > R-Car SoCs. The controller operates in CAN FD mode by default. Two
> > test modes are available and can be enabled by the
> > "rcar_canfd.testmode" module parameter. Refer to Documentation/kernel-
> parameters.txt.
> 
> (..)
> 
> > +#ifdef CONFIG_DEBUG_FS
> > +#include <linux/debugfs.h>
> > +
> > +static int rcar_canfd_showregs(struct seq_file *s, void *data) {
> > +	struct rcar_canfd_channel *priv = s->private;
> > +	u32 ch = priv->channel;
> > +	u32 rf = ch + RCANFD_RFFIFO_IDX;
> > +	u32 cf = RCANFD_CFFIFO_IDX;
> > +	u32 val, offset, i;
> > +
> > +	if (testmode)
> > +		seq_printf(s, "RCANFD : testmode = %d\n", testmode);
> > +	seq_printf(s, "RCANFD register dump: channel %u\n", ch);
> > +	seq_printf(s, "%-40s: %x\n", "g: cfg",
> > +		   rcar_canfd_read(priv, RCANFD_GCFG));
> 
> Why do you think you would need this kind of register dumps in debugfs?
> 
> This could be interesting for development purposes - but in production
> drivers this is pretty unusual and needless.

I thought it would be useful when we add more features to the driver (e.g. Gateway mode).
 
> 
> I would sugest to remove either the testmode (already suggested by Marc)
> and this register dump stuff.

OK. I'll remove both.

Thanks,
Ramesh

Re: [PATCH] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Marc Kleine-Budde]

[-- Attachment #1: Type: text/plain, Size: 2010 bytes --]

On 03/02/2016 09:41 AM, Ramesh Shanmugasundaram wrote:
>> Is the channel loopback mode configurable per channel? If so, please
>> remove the module parameter and make use of CAN_CTRLMODE_LOOPBACK to
>> configure it.
> 
> The loopback setting is not truly a per channel attribute. It
> requires touching Rx rules which can be done only when the
> controller's global state is reset (during probe).
> CAN_CTRLMODE_LOOPBACK config option is possible only through
> .ndo_open of that channel but the global controller state needs to be
> operational by this time. As it is a global attribute & for the above
> reason, I choose the module option.

I see, ok then.

>>> CAN FD mode supports both Classical CAN & CAN FD frame formats. The
>>> controller supports ISO 11898-1:2015 CAN FD format only.
>>>
>>> This controller supports two channels and the driver can enable either
>>> or both of the channels.
>>>
>>> Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs
>>> (one per channel) for transmission. Rx filter rules are configured to
>>> the minimum (one per channel) and it accepts Standard, Extended, Data
>>> & Remote Frame combinations.
>>
>> I see no locking for the tx-path.
>  
> I am not sure why locking is needed in tx-path? 

If the tx-path is shared between both channels you need locking as the
networking subsystem may send one frame to each controller at the same time.

> However, looking at it again, I should move the incrementing of head
> after the "sts" handing to be apt. What do you think?

With one producer (one SW instance) and one consumer (the HW) you can
write lockless code (if the HW allows it), but with two producers it's
not possible.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
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RE: [PATCH] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Marc,

> On 03/02/2016 09:41 AM, Ramesh Shanmugasundaram wrote:
> >> Is the channel loopback mode configurable per channel? If so, please
> >> remove the module parameter and make use of CAN_CTRLMODE_LOOPBACK to
> >> configure it.
> >
> > The loopback setting is not truly a per channel attribute. It requires
> > touching Rx rules which can be done only when the controller's global
> > state is reset (during probe).
> > CAN_CTRLMODE_LOOPBACK config option is possible only through .ndo_open
> > of that channel but the global controller state needs to be
> > operational by this time. As it is a global attribute & for the above
> > reason, I choose the module option.
> 
> I see, ok then.
> 
> >>> CAN FD mode supports both Classical CAN & CAN FD frame formats. The
> >>> controller supports ISO 11898-1:2015 CAN FD format only.
> >>>
> >>> This controller supports two channels and the driver can enable
> >>> either or both of the channels.
> >>>
> >>> Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs
> >>> (one per channel) for transmission. Rx filter rules are configured
> >>> to the minimum (one per channel) and it accepts Standard, Extended,
> >>> Data & Remote Frame combinations.
> >>
> >> I see no locking for the tx-path.
> >
> > I am not sure why locking is needed in tx-path?
> 
> If the tx-path is shared between both channels you need locking as the
> networking subsystem may send one frame to each controller at the same
> time.

Yes. Tx completion interrupt is shared by both channels but the Tx FIFO, echo skbs, head, tail are maintained on a per channel basis. 
Yes, net subsystem can send one frame to each channel at the same time and the tx completion interrupt handler will traverse each channel & update per channel context accordingly.

> > However, looking at it again, I should move the incrementing of head
> > after the "sts" handing to be apt. What do you think?
> 
> With one producer (one SW instance) and one consumer (the HW) you can
> write lockless code (if the HW allows it), but with two producers it's not
> possible.

For a channel represented as netdev, there is still one producer (one SW instance) isn't it? net acquires lock before calling xmit. The consumer is tx completion interrupt handler which updates per channel attributes only.

Sorry if I am annoying. I have tested this with two channels transmitting & receiving at the same time and it works fine. If I am missing lock, I would like to understand it thoroughly before making the change.

Thanks for the help,
Ramesh.

Re: [PATCH] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Marc Kleine-Budde]

[-- Attachment #1: Type: text/plain, Size: 1993 bytes --]

On 03/02/2016 11:08 AM, Ramesh Shanmugasundaram wrote:
>>>> I see no locking for the tx-path.
>>>
>>> I am not sure why locking is needed in tx-path?
>>
>> If the tx-path is shared between both channels you need locking as the
>> networking subsystem may send one frame to each controller at the same
>> time.
> 
> Yes. Tx completion interrupt is shared by both channels but the Tx
> FIFO, echo skbs, head, tail are maintained on a per channel basis. 
> Yes, net subsystem can send one frame to each channel at the same
> time and the tx completion interrupt handler will traverse each
> channel & update per channel context accordingly.

Ok. Which instruction starts the transmit? Please add a comment to the
code. You stop the tx_queue after this, so your code is racy, as the
interrupt might happen in between.

>>> However, looking at it again, I should move the incrementing of head
>>> after the "sts" handing to be apt. What do you think?
>>
>> With one producer (one SW instance) and one consumer (the HW) you can
>> write lockless code (if the HW allows it), but with two producers it's not
>> possible.
> 
> For a channel represented as netdev, there is still one producer (one
> SW instance) isn't it? net acquires lock before calling xmit. The
> consumer is tx completion interrupt handler which updates per channel
> attributes only.

Ok - I haven't looked at the code in depth yet. Now it's clear, that
just the tx interrupt is shared.

> Sorry if I am annoying. I have tested this with two channels
> transmitting & receiving at the same time and it works fine. If I am
> missing lock, I would like to understand it thoroughly before making
> the change.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
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RE: [PATCH] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Marc,

Sorry for the late response.

> On 03/02/2016 11:08 AM, Ramesh Shanmugasundaram wrote:
> >>>> I see no locking for the tx-path.
> >>>
> >>> I am not sure why locking is needed in tx-path?
> >>
> >> If the tx-path is shared between both channels you need locking as
> >> the networking subsystem may send one frame to each controller at the
> >> same time.
> >
> > Yes. Tx completion interrupt is shared by both channels but the Tx
> > FIFO, echo skbs, head, tail are maintained on a per channel basis.
> > Yes, net subsystem can send one frame to each channel at the same time
> > and the tx completion interrupt handler will traverse each channel &
> > update per channel context accordingly.
> 
> Ok. Which instruction starts the transmit? Please add a comment to the
> code.

Please see

---<snip>---

+	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
+	 * pointer for the Common FIFO
+	 */
+	rcar_canfd_write(priv, RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);

---<snip>---

> You stop the tx_queue after this, so your code is racy, as the
> interrupt might happen in between.

It is a very good point. Thank you. 
I managed to reproduce this issue once with 50Kbps rate and ignoring -ENOBUFS in user space. It also exposed another subtle issue in the echo skb management where the tx_done loop pushes the skb before the actual ACK for that index happens. Fixed both issues.
As you mentioned, I have introduced a lock to protect this critical section. I'll send the updates in the next v2 patch.

Thanks,
Ramesh

[PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

This patch adds support for the CAN FD controller found in Renesas R-Car
SoCs. The controller operates in CAN FD mode by default.

CAN FD mode supports both Classical CAN & CAN FD frame formats. The
controller supports ISO 11898-1:2015 CAN FD format only.

This controller supports two channels and the driver can enable either
or both of the channels.

Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs (one
per channel) for transmission. Rx filter rules are configured to the
minimum (one per channel) and it accepts Standard, Extended, Data &
Remote Frame combinations.

Note: There are few documentation errors in R-Car Gen3 Hardware User
Manual v0.5E with respect to CAN FD controller. They are listed below:

1. CAN FD interrupt numbers 29 & 30 are listed as per channel
interrupts. However, they are common to both channels (i.e.) they are
global and channel interrupts respectively.

2. CANFD clock is derived from PLL1. This is not documented.

3. CANFD clock is further divided by (1/2) within the CAN FD controller.
This is not documented.

4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
is mentioned 4 Tq in the manual.

5. The maximum number of message RAM area the controller can use is 3584
bytes. It is specified 10752 bytes in the manual.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
---
Changes since v1:
	* Removed testmodes & debugfs code (suggested by Oliver H)
	* Fixed tx path race issue by introducing lock (suggested by Marc K)
	* Removed __maybe_unused attribute of rcar_canfd_of_table

Thanks,
Ramesh
---
 .../devicetree/bindings/net/can/rcar_canfd.txt     |   86 ++
 drivers/net/can/Kconfig                            |   10 +
 drivers/net/can/Makefile                           |    1 +
 drivers/net/can/rcar_canfd.c                       | 1624 ++++++++++++++++++++
 4 files changed, 1721 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
 create mode 100644 drivers/net/can/rcar_canfd.c

diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
new file mode 100644
index 0000000..4299bd8
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
@@ -0,0 +1,86 @@
+Renesas R-Car CAN FD controller Device Tree Bindings
+----------------------------------------------------
+
+Required properties:
+- compatible: Must contain one or more of the following:
+  - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
+  - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
+
+  When compatible with the generic version, nodes must list the
+  SoC-specific version corresponding to the platform first, followed by the
+  family-specific and/or generic versions.
+
+- reg: physical base address and size of the R-Car CAN FD register map.
+- interrupts: interrupt specifier for the Global & Channel interrupts
+- clocks: phandles and clock specifiers for 3 clock inputs.
+- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
+- pinctrl-0: pin control group to be used for this controller.
+- pinctrl-names: must be "default".
+
+Required properties for "renesas,r8a7795-canfd" compatible:
+In R8A7795 SoC, canfd clock is a div6 clock and can be used by both CAN
+and CAN FD controller at the same time. It needs to be scaled to maximum
+frequency if any of these controllers use it. This is done using the
+below properties.
+
+- assigned-clocks: phandle of canfd clock.
+- assigned-clock-rates: maximum frequency of this clock.
+
+Each channel is represented as a child node. They can be enabled/disabled
+using "status" property.
+
+Example
+-------
+
+SoC common .dtsi file:
+
+		canfd: canfd@e66c0000 {
+			compatible = "renesas,r8a7795-canfd",
+				     "renesas,rcar-gen3-canfd";
+			reg = <0 0xe66c0000 0 0x8000>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 914>,
+			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
+			       <&can_clk>;
+			clock-names = "fck", "canfd", "can_clk";
+			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
+			assigned-clock-rates = <40000000>;
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			channel0 {
+				status = "disabled";
+			};
+
+			channel1 {
+				status = "disabled";
+			};
+		};
+
+Board specific .dts file:
+
+E.g. below enables Channel 1 alone in the board.
+
+&canfd {
+        pinctrl-0 = <&canfd1_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+	channel1 {
+		status = "okay";
+	};
+};
+
+E.g. below enables Channel 0 alone in the board using External clock
+as fCAN clock.
+
+&canfd {
+        pinctrl-0 = <&canfd0_pins &can_clk_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+	channel0 {
+		status = "okay";
+	};
+};
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 0d40aef..0ecb4fe 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -114,6 +114,16 @@ config CAN_RCAR
 	  To compile this driver as a module, choose M here: the module will
 	  be called rcar_can.
 
+config CANFD_RCAR
+	tristate "Renesas R-Car CAN FD controller"
+	depends on ARCH_RENESAS || ARM
+	---help---
+	  Say Y here if you want to use CAN FD controller found on
+	  Renesas R-Car SoCs.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called rcar_canfd.
+
 config CAN_SUN4I
 	tristate "Allwinner A10 CAN controller"
 	depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index e3db0c8..401b150 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_CAN_JANZ_ICAN3)	+= janz-ican3.o
 obj-$(CONFIG_CAN_MSCAN)		+= mscan/
 obj-$(CONFIG_CAN_M_CAN)		+= m_can/
 obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
+obj-$(CONFIG_CANFD_RCAR)	+= rcar_canfd.o
 obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
 obj-$(CONFIG_CAN_SUN4I)		+= sun4i_can.o
 obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
diff --git a/drivers/net/can/rcar_canfd.c b/drivers/net/can/rcar_canfd.c
new file mode 100644
index 0000000..56e089d
--- /dev/null
+++ b/drivers/net/can/rcar_canfd.c
@@ -0,0 +1,1624 @@
+/* Renesas R-Car CAN FD device driver
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/netdevice.h>
+#include <linux/platform_device.h>
+#include <linux/can/led.h>
+#include <linux/can/dev.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+
+#define RCANFD_DRV_NAME			"rcar_canfd"
+
+#define RCANFD_FIFO_DEPTH		8	/* Tx FIFO depth */
+#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
+
+#define RCANFD_NUM_CHANNELS		2
+#define RCANFD_CHANNELS_MASK		0x3	/* Two channels max */
+
+/* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
+ * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
+ * number is added to RFFIFO index.
+ */
+#define RCANFD_RFFIFO_IDX		0
+
+/* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
+ * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
+ */
+#define RCANFD_CFFIFO_IDX		0
+
+/* Global register bits */
+#define RCANFD_GINTF_CANFD		BIT(0)
+
+#define RCANFD_GCFG_TPRI		BIT(0)
+#define RCANFD_GCFG_DCE			BIT(1)
+#define RCANFD_GCFG_DCS			BIT(4)
+#define RCANFD_GCFG_CMPOC		BIT(5)
+#define RCANFD_GCFG_EEFE		BIT(6)
+
+#define RCANFD_GCTR_SLPR		BIT(2)
+#define RCANFD_GCTR_MODEMASK		(0x3)
+#define RCANFD_GCTR_GOPM		(0x0)
+#define RCANFD_GCTR_GRESET		(0x1)
+#define RCANFD_GCTR_GHLT		(0x2)
+
+#define RCANFD_GCTR_DEIE		BIT(8)
+#define RCANFD_GCTR_MEIE		BIT(9)
+#define RCANFD_GCTR_THLEIE		BIT(10)
+#define RCANFD_GCTR_CFMPOFIE		BIT(11)
+#define RCANFD_GCTR_TSRST		BIT(16)
+
+#define RCANFD_GSTS_RAMINIT		BIT(3)
+#define RCANFD_GSTS_SLP			BIT(2)
+#define RCANFD_GSTS_HLT			BIT(1)
+#define RCANFD_GSTS_RESET		BIT(0)
+
+#define RCANFD_GSTS_GNOPM		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+/* Channel register bits */
+#define RCANFD_CCTR_CSLPR		BIT(2)
+#define RCANFD_CCTR_MODEMASK		(0x3)
+#define RCANFD_CCTR_COPM		(0x0)
+#define RCANFD_CCTR_CRESET		(0x1)
+#define RCANFD_CCTR_CHLT		(0x2)
+#define RCANFD_CCTR_CTMASK		(0x3 << 25)
+#define RCANFD_CCTR_CTMS_ILB		(0x3 << 25)
+#define RCANFD_CCTR_CTME		BIT(24)
+#define RCANFD_CCTR_ERRD		BIT(23)
+#define RCANFD_CCTR_BOMMASK		(0x3 << 21)
+#define RCANFD_CCTR_BOM_ENTRY		(0x1 << 21)
+#define RCANFD_CCTR_TDCVFIE		BIT(19)
+#define RCANFD_CCTR_SOCOIE		BIT(18)
+#define RCANFD_CCTR_EOCOIE		BIT(17)
+#define RCANFD_CCTR_TAIE		BIT(16)
+#define RCANFD_CCTR_ALIE		BIT(15)
+#define RCANFD_CCTR_BLIE		BIT(14)
+#define RCANFD_CCTR_OLIE		BIT(13)
+#define RCANFD_CCTR_BORIE		BIT(12)
+#define RCANFD_CCTR_BOEIE		BIT(11)
+#define RCANFD_CCTR_EPIE		BIT(10)
+#define RCANFD_CCTR_EWIE		BIT(9)
+#define RCANFD_CCTR_BEIE		BIT(8)
+
+#define RCANFD_CSTS_COM			BIT(7)
+#define RCANFD_CSTS_REC			BIT(6)
+#define RCANFD_CSTS_TRM			BIT(5)
+#define RCANFD_CSTS_BO			BIT(4)
+#define RCANFD_CSTS_EP			BIT(3)
+#define RCANFD_CSTS_SLP			BIT(2)
+#define RCANFD_CSTS_HALT		BIT(1)
+#define RCANFD_CSTS_RESET		BIT(0)
+
+#define RCANFD_CSTS_TECCNT(x)		(((x) >> 24) & 0xff)
+#define RCANFD_CSTS_RECCNT(x)		(((x) >> 16) & 0xff)
+
+/* Bit Configuration register */
+#define RCANFD_BRP(x)			(((x) & 0x3ff) << 0)
+#define RCANFD_SJW(x)			(((x) & 0x3) << 24)
+#define RCANFD_TSEG1(x)			(((x) & 0xf) << 16)
+#define RCANFD_TSEG2(x)			(((x) & 0x7) << 20)
+
+#define RCANFD_NR_BRP(x)		(((x) & 0x3ff) << 0)
+#define RCANFD_NR_SJW(x)		(((x) & 0x1f) << 11)
+#define RCANFD_NR_TSEG1(x)		(((x) & 0x7f) << 16)
+#define RCANFD_NR_TSEG2(x)		(((x) & 0x1f) << 24)
+
+#define RCANFD_DR_BRP(x)		(((x) & 0xff) << 0)
+#define RCANFD_DR_SJW(x)		(((x) & 0x7) << 24)
+#define RCANFD_DR_TSEG1(x)		(((x) & 0xf) << 16)
+#define RCANFD_DR_TSEG2(x)		(((x) & 0x7) << 20)
+
+/* Global Error flag bits */
+#define RCANFD_GERFL_EEF1		BIT(17)
+#define RCANFD_GERFL_EEF0		BIT(16)
+#define RCANFD_GERFL_CMPOF		BIT(3)
+#define RCANFD_GERFL_THLES		BIT(2)
+#define RCANFD_GERFL_MES		BIT(1)
+#define RCANFD_GERFL_DEF		BIT(0)
+
+#define RCANFD_GERFL_ERR(x)		((x) & (RCANFD_GERFL_EEF1 |\
+						RCANFD_GERFL_EEF0 |\
+						RCANFD_GERFL_MES |\
+						RCANFD_GERFL_CMPOF))
+
+/* Channel Error flag bits */
+#define RCANFD_CERFL_ADEF		BIT(14)
+#define RCANFD_CERFL_B0EF		BIT(13)
+#define RCANFD_CERFL_B1EF		BIT(12)
+#define RCANFD_CERFL_CEF		BIT(11)
+#define RCANFD_CERFL_AEF		BIT(10)
+#define RCANFD_CERFL_FEF		BIT(9)
+#define RCANFD_CERFL_SEF		BIT(8)
+#define RCANFD_CERFL_ALEF		BIT(7)
+#define RCANFD_CERFL_BLEF		BIT(6)
+#define RCANFD_CERFL_OLEF		BIT(5)
+#define RCANFD_CERFL_BOREF		BIT(4)
+#define RCANFD_CERFL_BOEEF		BIT(3)
+#define RCANFD_CERFL_EPEF		BIT(2)
+#define RCANFD_CERFL_EWEF		BIT(1)
+#define RCANFD_CERFL_BEF		BIT(0)
+
+#define RCANFD_CERFL_ERR(x)		((x) & (0x7fff)) /* above bits 14:0 */
+
+/* CAN FD specific registers */
+#define RCANFD_DCFG_TDCE		BIT(9)
+#define RCANFD_DCFG_TDCOC		BIT(8)
+#define RCANFD_DCFG_TDCO(x)		(((x) & 0x7f) >> 16)
+
+#define RCANFD_DCSTS_TDCR(x)		(((x) >> 0) & 0x7f)
+#define RCANFD_DCSTS_SOCCNT(x)		(((x) >> 24) & 0xff)
+#define RCANFD_DCSTS_EOCCNT(x)		(((x) >> 16) & 0xff)
+
+#define RCANFD_DCSTS_TDCVF		BIT(7)
+#define RCANFD_DCSTS_EOCO		BIT(8)
+#define RCANFD_DCSTS_SOCO		BIT(9)
+
+/* Rx FIFO bits */
+#define RCANFD_RFFIFO_RFIF		BIT(3)
+#define RCANFD_RFFIFO_RFMLT		BIT(2)
+#define RCANFD_RFFIFO_RFFLL		BIT(1)
+#define RCANFD_RFFIFO_RFEMP		BIT(0)
+
+#define RCANFD_RFFIFO_RFESI		BIT(0)
+#define RCANFD_RFFIFO_RFBRS		BIT(1)
+#define RCANFD_RFFIFO_RFFDF		BIT(2)
+
+#define RCANFD_RFFIFO_RFIDE		BIT(31)
+#define RCANFD_RFFIFO_RFRTR		BIT(30)
+
+#define RCANFD_RFFIFO_RFDLC(x)		(((x) >> 28) & 0xf)
+#define RCANFD_RFFIFO_RFPTR(x)		(((x) >> 16) & 0xfff)
+#define RCANFD_RFFIFO_RFTS(x)		(((x) >> 0) & 0xff)
+
+#define RCANFD_RFFIFO_RFIM		BIT(12)
+#define RCANFD_RFFIFO_RFDC(x)		(((x) & 0x7) << 8)
+#define RCANFD_RFFIFO_RFPLS(x)		(((x) & 0x7) << 4)
+#define RCANFD_RFFIFO_RFIE		BIT(1)
+#define RCANFD_RFFIFO_RFE		BIT(0)
+
+/* Common FIFO bits */
+#define RCANFD_CMFIFO_TML(x)		(((x) & 0xf) << 20)
+#define RCANFD_CMFIFO_M(x)		(((x) & 0x3) << 16)
+#define RCANFD_CMFIFO_CFIM		BIT(12)
+#define RCANFD_CMFIFO_DC(x)		(((x) & 0x7) << 8)
+#define RCANFD_CMFIFO_PLS(x)		(((x) & 0x7) << 4)
+#define RCANFD_CMFIFO_CFTXIE		BIT(2)
+#define RCANFD_CMFIFO_CFE		BIT(0)
+
+#define RCANFD_CMFIFO_CFTXIF		BIT(4)
+#define RCANFD_CMFIFO_CFMLT		BIT(2)
+#define RCANFD_CMFIFO_CFFLL		BIT(1)
+#define RCANFD_CMFIFO_CFEMP		BIT(0)
+#define RCANFD_CMFIFO_CFMC(x)		(((x) >> 8) & 0xff)
+
+#define RCANFD_CMFIFO_CFESI		BIT(0)
+#define RCANFD_CMFIFO_CFBRS		BIT(1)
+#define RCANFD_CMFIFO_CFFDF		BIT(2)
+
+#define RCANFD_CMFIFO_CFIDE		BIT(31)
+#define RCANFD_CMFIFO_CFRTR		BIT(30)
+#define RCANFD_CMFIFO_CFID(x)		((x) & 0x1fffffff)
+
+#define RCANFD_CMFIFO_CFDLC(x)		(((x) & 0xf) << 28)
+#define RCANFD_CMFIFO_CFPTR(x)		(((x) & 0xfff) << 16)
+#define RCANFD_CMFIFO_CFTS(x)		(((x) & 0xff) << 0)
+
+/* Global Test Config register */
+#define RCANFD_GTSTCFG_C0CBCE		BIT(0)
+#define RCANFD_GTSTCFG_C1CBCE		BIT(1)
+
+#define RCANFD_GTSTCTR_ICBCTME		BIT(0)
+
+/* AFL Rx rules registers */
+#define RCANFD_AFLCFG_SETRNC0(x)	(((x) & 0xff) << 24)
+#define RCANFD_AFLCFG_SETRNC1(x)	(((x) & 0xff) << 16)
+#define RCANFD_AFLCFG_GETRNC0(x)	(((x) >> 24) & 0xff)
+#define RCANFD_AFLCFG_GETRNC1(x)	(((x) >> 16) & 0xff)
+
+#define RCANFD_AFL_PAGENUM(entry)	((entry) / 16)
+
+#define RCANFD_AFLCTR_AFLDAE		BIT(8)
+#define RCANFD_AFLCTR_AFLPN(x)		((x) & 0x1f)
+#define RCANFD_CHANNEL_NUMRULES		1	/* only one rule per channel */
+#define RCANFD_AFLID_GAFLLB		BIT(29)
+#define RCANFD_AFLPTR1_RFFIFO(x)	(1 << (x))
+
+/* Common register map offsets */
+
+/* Nominal rate registers */
+#define RCANFD_CCFG(m)			(0x0000 + (0x10 * (m)))
+#define RCANFD_CCTR(m)			(0x0004 + (0x10 * (m)))
+#define RCANFD_CSTS(m)			(0x0008 + (0x10 * (m)))
+#define RCANFD_CERFL(m)			(0x000C + (0x10 * (m)))
+
+/* Global registers */
+#define RCANFD_GCFG			(0x0084)
+#define RCANFD_GCTR			(0x0088)
+#define RCANFD_GSTS			(0x008c)
+#define RCANFD_GERFL			(0x0090)
+#define RCANFD_GTSC			(0x0094)
+#define RCANFD_GAFLECTR			(0x0098)
+#define RCANFD_GAFLCFG0			(0x009c)
+#define RCANFD_GAFLCFG1			(0x00a0)
+#define RCANFD_RMNB			(0x00a4)
+
+#define RCANFD_RMND(y)			(0x00a8 + (0x04 * (y)))
+
+/* Rx FIFO Control registers */
+#define RCANFD_RFCC(x)			(0x00b8 + (0x04 * (x)))
+#define RCANFD_RFSTS(x)			(0x00d8 + (0x04 * (x)))
+#define RCANFD_RFPCTR(x)		(0x00f8 + (0x04 * (x)))
+
+/* Common FIFO Control registers */
+#define RCANFD_CFCC(ch, idx)		(0x0118 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+#define RCANFD_CFSTS(ch, idx)		(0x0178 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+#define RCANFD_CFPCTR(ch, idx)		(0x01d8 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+
+#define RCANFD_FESTS			(0x0238)
+#define RCANFD_FFSTS			(0x023c)
+#define RCANFD_FMSTS			(0x0240)
+#define RCANFD_RFISTS			(0x0244)
+#define RCANFD_CFRISTS			(0x0248)
+#define RCANFD_CFTISTS			(0x024c)
+
+#define RCANFD_TMC(p)			(0x0250 + (0x01 * (p)))
+#define RCANFD_TMSTS(p)			(0x02d0 + (0x01 * (p)))
+
+#define RCANFD_TMTRSTS(y)		(0x0350 + (0x04 * (y)))
+#define RCANFD_TMTARSTS(y)		(0x0360 + (0x04 * (y)))
+#define RCANFD_TMTCSTS(y)		(0x0370 + (0x04 * (y)))
+#define RCANFD_TMTASTS(y)		(0x0380 + (0x04 * (y)))
+#define RCANFD_TMIEC(y)			(0x0390 + (0x04 * (y)))
+
+#define RCANFD_TXQCC(m)			(0x03a0 + (0x04 * (m)))
+#define RCANFD_TXQSTS(m)		(0x03c0 + (0x04 * (m)))
+#define RCANFD_TXQPCTR(m)		(0x03e0 + (0x04 * (m)))
+
+#define RCANFD_THLCC(m)			(0x0400 + (0x04 * (m)))
+#define RCANFD_THLSTS(m)		(0x0420 + (0x04 * (m)))
+#define RCANFD_THLPCTR(m)		(0x0440 + (0x04 * (m)))
+
+#define RCANFD_GTINTSTS0		(0x0460)
+#define RCANFD_GTINTSTS1		(0x0464)
+#define RCANFD_GTSTCFG			(0x0468)
+#define RCANFD_GTSTCTR			(0x046c)
+#define RCANFD_GLOCKK			(0x047c)
+#define RCANFD_GRMCFG			(0x04fc)
+
+/* Receive rule registers */
+#define RCANFD_GAFLID(offset, j)	((offset) + (0x10 * (j)))
+#define RCANFD_GAFLM(offset, j)		((offset) + 0x04 + (0x10 * (j)))
+#define RCANFD_GAFLP0(offset, j)	((offset) + 0x08 + (0x10 * (j)))
+#define RCANFD_GAFLP1(offset, j)	((offset) + 0x0c + (0x10 * (j)))
+
+/* CAN FD mode specific regsiter map */
+
+/* Data bitrate registers */
+#define RCANFD_F_CDFG(m)		(0x0500 + (0x20 * (m)))
+#define RCANFD_F_CFDCFG(m)		(0x0504 + (0x20 * (m)))
+#define RCANFD_F_CFDCTR(m)		(0x0508 + (0x20 * (m)))
+#define RCANFD_F_CFDSTS(m)		(0x050c + (0x20 * (m)))
+#define RCANFD_F_CFDCRC(m)		(0x0510 + (0x20 * (m)))
+
+#define RCANFD_F_GAFL_OFFSET		(0x1000)
+
+#define RCANFD_F_RMID(q)		(0x2000 + (0x10 * (q)))
+#define RCANFD_F_RMPTR(q)		(0x2004 + (0x10 * (q)))
+#define RCANFD_F_RMFDSTS(q)		(0x2008 + (0x10 * (q)))
+#define RCANFD_F_RMDF(q, b)		(0x200c + (0x04 * (b)) + (0x20 * (q)))
+
+/* Rx FIFO data registers */
+#define RCANFD_F_RFOFFSET		(0x3000)
+#define RCANFD_F_RFID(x)		(RCANFD_F_RFOFFSET + (0x80 * (x)))
+#define RCANFD_F_RFPTR(x)		(RCANFD_F_RFOFFSET + 0x04 + \
+					 (0x80 * (x)))
+#define RCANFD_F_RFFDSTS(x)		(RCANFD_F_RFOFFSET + 0x08 + \
+					 (0x80 * (x)))
+#define RCANFD_F_RFDF(x, df)		(RCANFD_F_RFOFFSET + 0x0c + \
+					 (0x80 * (x)) + (0x04 * (df)))
+
+/* Common FIFO data registers */
+#define RCANFD_F_CFOFFSET		(0x3400)
+#define RCANFD_F_CFID(ch, idx)		(RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
+					 (0x80 * (idx)))
+#define RCANFD_F_CFPTR(ch, idx)		(RCANFD_F_CFOFFSET + 0x04 + \
+					 (0x180 * (ch)) + (0x80 * (idx)))
+#define RCANFD_F_CFFDCSTS(ch, idx)	(RCANFD_F_CFOFFSET + 0x08 + \
+					 (0x180 * (ch)) + (0x80 * (idx)))
+#define RCANFD_F_CFDF(ch, idx, df)	(RCANFD_F_CFOFFSET + 0x0c + \
+					 (0x180 * (ch)) + (0x80 * (idx)) + \
+					 (0x04 * (df)))
+
+#define RCANFD_F_TMID(p)		(0x4000 + (0x20 * (p)))
+#define RCANFD_F_TMPTR(p)		(0x4004 + (0x20 * (p)))
+#define RCANFD_F_TMFDCTR(p)		(0x4008 + (0x20 * (p)))
+#define RCANFD_F_TMDF(p, b)		(0x400c + (0x20 * (p)) + (0x04 * (b)))
+
+#define RCANFD_F_THLACC(m)		(0x6000 + (0x04 * (m)))
+#define RCANFD_F_RPGACC(r)		(0x6400 + (0x04 * (r)))
+
+struct rcar_canfd_global;
+
+/* Channel priv data */
+struct rcar_canfd_channel {
+	struct can_priv can;			/* Must be the first member */
+	struct net_device *ndev;
+	struct rcar_canfd_global *gpriv;	/* Controller reference */
+	void __iomem *base;			/* Register base address */
+#ifdef CONFIG_DEBUG_FS
+	struct dentry *dev_root;
+#endif /* CONFIG_DEBUG_FS */
+	struct napi_struct napi;
+	u8  tx_len[RCANFD_FIFO_DEPTH];		/* For net stats */
+	u32 tx_head;				/* Incremented on xmit */
+	u32 tx_tail;				/* Incremented on xmit done */
+	u32 channel;				/* Channel number */
+	spinlock_t tx_lock;			/* To protect tx path */
+};
+
+/* Global priv data */
+struct rcar_canfd_global {
+	struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
+	void __iomem *base;		/* Register base address */
+	struct platform_device *pdev;	/* Respective platform device */
+	struct clk *clkp;		/* Peripheral clock */
+	struct clk *can_clk;		/* fCAN clock */
+	int clock_select;		/* CANFD or Ext clock */
+	unsigned long channels_mask;	/* Enabled channels mask */
+	u32 freq;			/* fCAN clock frequency in Hz */
+};
+
+/* CAN FD mode nominal rate constants */
+static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
+	.name = RCANFD_DRV_NAME,
+	.tseg1_min = 2,
+	.tseg1_max = 128,
+	.tseg2_min = 2,
+	.tseg2_max = 32,
+	.sjw_max = 32,
+	.brp_min = 1,
+	.brp_max = 1024,
+	.brp_inc = 1,
+};
+
+/* CAN FD mode data rate constants */
+static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
+	.name = RCANFD_DRV_NAME,
+	.tseg1_min = 2,
+	.tseg1_max = 16,
+	.tseg2_min = 2,
+	.tseg2_max = 8,
+	.sjw_max = 8,
+	.brp_min = 1,
+	.brp_max = 256,
+	.brp_inc = 1,
+};
+
+/* fCAN clock select register settings */
+enum {
+	RCANFD_CANFDCLK = 0,	/* CANFD clock */
+	RCANFD_EXTCLK,		/* Externally input clock */
+};
+
+/* Helper functions */
+static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
+{
+	u32 data = readl(reg);
+
+	data &= ~mask;
+	data |= (val & mask);
+	writel(data, reg);
+}
+
+#define rcar_canfd_read(priv, offset)			\
+	readl(priv->base + (offset))
+#define rcar_canfd_write(priv, offset, val)		\
+	writel(val, priv->base + (offset))
+#define rcar_canfd_set_bit(priv, reg, val)		\
+	rcar_canfd_update(val, val, priv->base + (reg))
+#define rcar_canfd_clear_bit(priv, reg, val)		\
+	rcar_canfd_update(val, 0, priv->base + (reg))
+#define rcar_canfd_update_bit(priv, reg, mask, val)	\
+	rcar_canfd_update(mask, val, priv->base + (reg))
+
+static void rcar_canfd_get_data(struct canfd_frame *cf,
+				struct rcar_canfd_channel *priv, u32 off)
+{
+	u32 i, lwords;
+
+	lwords = cf->len / sizeof(u32);
+	if (cf->len % sizeof(u32))
+		lwords++;
+	for (i = 0; i < lwords; i++)
+		*((u32 *)cf->data + i) =
+			rcar_canfd_read(priv, off + (i * sizeof(u32)));
+}
+
+static void rcar_canfd_put_data(struct canfd_frame *cf,
+				struct rcar_canfd_channel *priv, u32 off)
+{
+	u32 i, j, lwords, leftover;
+	u32 data = 0;
+
+	lwords = cf->len / sizeof(u32);
+	leftover = cf->len % sizeof(u32);
+	for (i = 0; i < lwords; i++)
+		rcar_canfd_write(priv, off + (i * sizeof(u32)),
+				 *((u32 *)cf->data + i));
+
+	if (leftover) {
+		u8 *p = (u8 *)((u32 *)cf->data + i);
+
+		for (j = 0; j < leftover; j++)
+			data |= p[j] << (j * 8);
+		rcar_canfd_write(priv, off + (i * sizeof(u32)), data);
+	}
+}
+
+static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
+{
+	u32 i;
+
+	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
+		can_free_echo_skb(ndev, i);
+}
+
+static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
+{
+	u32 sts, ch;
+	int err;
+
+	/* Check RAMINIT flag as CAN RAM initialization takes place
+	 * after the MCU reset
+	 */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 !(sts & RCANFD_GSTS_RAMINIT), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
+		return err;
+	}
+
+	/* Transition to Global Reset mode */
+	rcar_canfd_clear_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_SLPR);
+	rcar_canfd_update_bit(gpriv, RCANFD_GCTR,
+			      RCANFD_GCTR_MODEMASK, RCANFD_GCTR_GRESET);
+
+	/* Ensure Global reset mode */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 (sts & RCANFD_GSTS_RESET), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
+		return err;
+	}
+
+	/* Reset Global error flags */
+	rcar_canfd_write(gpriv, RCANFD_GERFL, 0x0);
+
+	/* Set the controller into FD mode */
+	rcar_canfd_set_bit(gpriv, RCANFD_GRMCFG, RCANFD_GINTF_CANFD);
+
+	/* Transition all Channels to reset mode */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_clear_bit(gpriv, RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
+
+		rcar_canfd_update_bit(gpriv, RCANFD_CCTR(ch),
+				      RCANFD_CCTR_MODEMASK,
+				      RCANFD_CCTR_CRESET);
+
+		/* Ensure Channel reset mode */
+		err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
+					 (sts & RCANFD_CSTS_RESET), 2, 500000);
+		if (err) {
+			dev_dbg(&gpriv->pdev->dev,
+				"channel %u reset failed\n", ch);
+			return err;
+		}
+	}
+	return 0;
+}
+
+static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
+{
+	u32 cfg, ch;
+
+	/* Global Configuration settings */
+	cfg = RCANFD_GCFG_EEFE;		/* ECC error flag enabled */
+
+	/* Set External Clock if selected */
+	if (gpriv->clock_select != RCANFD_CANFDCLK)
+		cfg |= RCANFD_GCFG_DCS;
+
+	/* Truncate payload to configured message size RFPLS */
+	cfg |= RCANFD_GCFG_CMPOC;
+
+	rcar_canfd_set_bit(gpriv, RCANFD_GCFG, cfg);
+
+	/* Channel configuration settings */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_set_bit(gpriv, RCANFD_CCTR(ch), RCANFD_CCTR_ERRD);
+		rcar_canfd_update_bit(gpriv, RCANFD_CCTR(ch),
+				      RCANFD_CCTR_BOMMASK,
+				      RCANFD_CCTR_BOM_ENTRY);
+	}
+}
+
+static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
+					   u32 ch)
+{
+	u32 cfg;
+	int start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	if (ch == 0) {
+		start = 0; /* Start from 0th rule */
+	} else {
+		/* Get number of existing rules and adjust */
+		cfg = rcar_canfd_read(gpriv, RCANFD_GAFLCFG0);
+		start = RCANFD_AFLCFG_GETRNC0(cfg);
+	}
+
+	/* Enable write access to entry */
+	page = RCANFD_AFL_PAGENUM(start);
+	rcar_canfd_set_bit(gpriv, RCANFD_GAFLECTR,
+			   (RCANFD_AFLCTR_AFLPN(page) | RCANFD_AFLCTR_AFLDAE));
+
+	/* Write number of rules for channel */
+	if (ch == 0)
+		rcar_canfd_set_bit(gpriv, RCANFD_GAFLCFG0,
+				   RCANFD_AFLCFG_SETRNC0(num_rules));
+	else
+		rcar_canfd_set_bit(gpriv, RCANFD_GAFLCFG0,
+				   RCANFD_AFLCFG_SETRNC1(num_rules));
+
+	/* Accept all IDs */
+	rcar_canfd_write(gpriv, RCANFD_GAFLID(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* IDE or RTR is not considered for matching */
+	rcar_canfd_write(gpriv, RCANFD_GAFLM(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* Any data length accepted */
+	rcar_canfd_write(gpriv, RCANFD_GAFLP0(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* Place the msg in corresponding Rx FIFO entry */
+	rcar_canfd_write(gpriv, RCANFD_GAFLP1(RCANFD_F_GAFL_OFFSET, start),
+			 RCANFD_AFLPTR1_RFFIFO(ridx));
+
+	/* Disable write access to page */
+	rcar_canfd_clear_bit(gpriv, RCANFD_GAFLECTR, RCANFD_AFLCTR_AFLDAE);
+}
+
+static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	/* Rx FIFO is used for reception */
+	u32 cfg;
+	u16 rfdc, rfpls;
+
+	/* Select Rx FIFO based on channel */
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	rfdc = 2;		/* b010 - 8 messages Rx FIFO depth */
+	rfpls = 7;		/* b111 - Max 64 bytes payload */
+
+	cfg = (RCANFD_RFFIFO_RFIM | RCANFD_RFFIFO_RFDC(rfdc) |
+		RCANFD_RFFIFO_RFPLS(rfpls) | RCANFD_RFFIFO_RFIE);
+	rcar_canfd_write(gpriv, RCANFD_RFCC(ridx), cfg);
+}
+
+static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	/* Tx/Rx(Common) FIFO configured in Tx mode is
+	 * used for transmission
+	 *
+	 * Each channel has 3 Common FIFO dedicated to them.
+	 * Use the 1st (index 0) out of 3
+	 */
+	u32 cfg;
+	u16 cftml, cfm, cfdc, cfpls;
+
+	cftml = 0;		/* 0th buffer */
+	cfm = 1;		/* b01 - Transmit mode */
+	cfdc = 2;		/* b010 - 8 messages Tx FIFO depth */
+	cfpls = 7;		/* b111 - Max 64 bytes payload */
+
+	cfg = (RCANFD_CMFIFO_TML(cftml) | RCANFD_CMFIFO_M(cfm) |
+		RCANFD_CMFIFO_CFIM | RCANFD_CMFIFO_DC(cfdc) |
+		RCANFD_CMFIFO_PLS(cfpls) | RCANFD_CMFIFO_CFTXIE);
+	rcar_canfd_write(gpriv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
+
+	/* Clear FD mode specific control/status register */
+	rcar_canfd_write(gpriv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
+}
+
+static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
+{
+	u32 ctr;
+
+	/* Clear any stray error interrupt flags */
+	rcar_canfd_write(gpriv, RCANFD_GERFL, 0);
+
+	/* Global interrupts setup */
+	ctr = RCANFD_GCTR_MEIE;
+	ctr |= RCANFD_GCTR_CFMPOFIE;
+
+	rcar_canfd_set_bit(gpriv, RCANFD_GCTR, ctr);
+}
+
+static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
+						 *gpriv)
+{
+	/* Disable all interrupts */
+	rcar_canfd_write(gpriv, RCANFD_GCTR, 0);
+
+	/* Clear any stray error interrupt flags */
+	rcar_canfd_write(gpriv, RCANFD_GERFL, 0);
+}
+
+static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
+						 *priv)
+{
+	u32 ctr, ch = priv->channel;
+
+	/* Clear any stray error flags */
+	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
+
+	/* Channel interrupts setup */
+	ctr = (RCANFD_CCTR_TAIE |
+	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
+	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
+	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
+	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
+	rcar_canfd_set_bit(priv, RCANFD_CCTR(ch), ctr);
+}
+
+static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
+						  *priv)
+{
+	u32 ctr, ch = priv->channel;
+
+	ctr = (RCANFD_CCTR_TAIE |
+	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
+	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
+	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
+	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
+	rcar_canfd_clear_bit(priv, RCANFD_CCTR(ch), ctr);
+
+	/* Clear any stray error flags */
+	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
+}
+
+static void rcar_canfd_global_error(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 ch = priv->channel;
+	u32 gerfl, sts;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	gerfl = rcar_canfd_read(priv, RCANFD_GERFL);
+	if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
+		netdev_dbg(ndev, "Ch0: ECC Error flag\n");
+		stats->tx_dropped++;
+	}
+	if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
+		netdev_dbg(ndev, "Ch1: ECC Error flag\n");
+		stats->tx_dropped++;
+	}
+	if (gerfl & RCANFD_GERFL_MES) {
+		sts = rcar_canfd_read(priv,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		if (sts & RCANFD_CMFIFO_CFMLT) {
+			netdev_dbg(ndev, "Tx Message Lost flag\n");
+			stats->tx_dropped++;
+			rcar_canfd_write(priv,
+					 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
+					 sts & ~RCANFD_CMFIFO_CFMLT);
+		}
+
+		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
+		if (sts & RCANFD_RFFIFO_RFMLT) {
+			netdev_dbg(ndev, "Rx Message Lost flag\n");
+			stats->rx_dropped++;
+			rcar_canfd_write(priv, RCANFD_RFSTS(ridx),
+					 sts & ~RCANFD_RFFIFO_RFMLT);
+		}
+	}
+	if (gerfl & RCANFD_GERFL_CMPOF) {
+		/* Message Lost flag will be set for respective channel
+		 * when this condition happens with counters and flags
+		 * already updated.
+		 */
+		netdev_dbg(ndev, "global payload overflow interrupt\n");
+	}
+
+	/* Clear all global error interrupts. Only affected channels bits
+	 * get cleared
+	 */
+	rcar_canfd_write(priv, RCANFD_GERFL, 0);
+}
+
+static void rcar_canfd_error(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	struct can_frame *cf;
+	struct sk_buff *skb;
+	u32 cerfl, csts;
+	u32 txerr = 0, rxerr = 0;
+	u32 ch = priv->channel;
+
+	/* Propagate the error condition to the CAN stack */
+	skb = alloc_can_err_skb(ndev, &cf);
+	if (!skb) {
+		stats->rx_dropped++;
+		return;
+	}
+
+	/* Channel error interrupt */
+	cerfl = rcar_canfd_read(priv, RCANFD_CERFL(ch));
+	csts = rcar_canfd_read(priv, RCANFD_CSTS(ch));
+	txerr = RCANFD_CSTS_TECCNT(csts);
+	rxerr = RCANFD_CSTS_RECCNT(csts);
+
+	netdev_dbg(ndev, "ch erfl %x sts %x txerr %u rxerr %u\n",
+		   cerfl, csts, txerr, rxerr);
+
+	if (cerfl & RCANFD_CERFL_BEF) {
+		netdev_dbg(ndev, "Bus error\n");
+		cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
+		cf->data[2] = CAN_ERR_PROT_UNSPEC;
+		priv->can.can_stats.bus_error++;
+	}
+	if (cerfl & RCANFD_CERFL_ADEF) {
+		netdev_dbg(ndev, "ACK Delimiter Error\n");
+		stats->tx_errors++;
+		cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
+	}
+	if (cerfl & RCANFD_CERFL_B0EF) {
+		netdev_dbg(ndev, "Bit Error (dominant)\n");
+		stats->tx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_BIT0;
+	}
+	if (cerfl & RCANFD_CERFL_B1EF) {
+		netdev_dbg(ndev, "Bit Error (recessive)\n");
+		stats->tx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_BIT1;
+	}
+	if (cerfl & RCANFD_CERFL_CEF) {
+		netdev_dbg(ndev, "CRC Error\n");
+		stats->rx_errors++;
+		cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
+	}
+	if (cerfl & RCANFD_CERFL_AEF) {
+		netdev_dbg(ndev, "ACK Error\n");
+		stats->tx_errors++;
+		cf->can_id |= CAN_ERR_ACK;
+		cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
+	}
+	if (cerfl & RCANFD_CERFL_FEF) {
+		netdev_dbg(ndev, "Form Error\n");
+		stats->rx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_FORM;
+	}
+	if (cerfl & RCANFD_CERFL_SEF) {
+		netdev_dbg(ndev, "Stuff Error\n");
+		stats->rx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_STUFF;
+	}
+	if (cerfl & RCANFD_CERFL_ALEF) {
+		netdev_dbg(ndev, "Arbitration lost Error\n");
+		priv->can.can_stats.arbitration_lost++;
+		cf->can_id |= CAN_ERR_LOSTARB;
+		cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
+	}
+	if (cerfl & RCANFD_CERFL_BLEF) {
+		netdev_dbg(ndev, "Bus Lock Error\n");
+		stats->rx_errors++;
+		cf->can_id |= CAN_ERR_BUSERROR;
+	}
+	if (cerfl & RCANFD_CERFL_EWEF) {
+		netdev_dbg(ndev, "Error warning interrupt\n");
+		priv->can.state = CAN_STATE_ERROR_WARNING;
+		priv->can.can_stats.error_warning++;
+		cf->can_id |= CAN_ERR_CRTL;
+		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
+			CAN_ERR_CRTL_RX_WARNING;
+		cf->data[6] = txerr;
+		cf->data[7] = rxerr;
+	}
+	if (cerfl & RCANFD_CERFL_EPEF) {
+		netdev_dbg(ndev, "Error passive interrupt\n");
+		priv->can.state = CAN_STATE_ERROR_PASSIVE;
+		priv->can.can_stats.error_passive++;
+		cf->can_id |= CAN_ERR_CRTL;
+		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
+			CAN_ERR_CRTL_RX_PASSIVE;
+		cf->data[6] = txerr;
+		cf->data[7] = rxerr;
+	}
+	if (cerfl & RCANFD_CERFL_BOEEF) {
+		netdev_dbg(ndev, "Bus-off entry interrupt\n");
+		rcar_canfd_tx_failure_cleanup(ndev);
+		priv->can.state = CAN_STATE_BUS_OFF;
+		priv->can.can_stats.bus_off++;
+		can_bus_off(ndev);
+		cf->can_id |= CAN_ERR_BUSOFF;
+	}
+	if (cerfl & RCANFD_CERFL_OLEF) {
+		netdev_dbg(ndev,
+			   "Overload Frame Transmission error interrupt\n");
+		stats->tx_errors++;
+		cf->can_id |= CAN_ERR_PROT;
+		cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
+	}
+
+	/* Clear all channel error interrupts */
+	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
+	stats->rx_packets++;
+	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
+}
+
+static void rcar_canfd_tx_done(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 sts;
+	unsigned long flags;
+	u32 ch = priv->channel;
+
+	do {
+		u8 unsent, sent;
+
+		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
+		stats->tx_packets++;
+		stats->tx_bytes += priv->tx_len[sent];
+		priv->tx_len[sent] = 0;
+		can_get_echo_skb(ndev, sent);
+
+		spin_lock_irqsave(&priv->tx_lock, flags);
+		priv->tx_tail++;
+		sts = rcar_canfd_read(priv,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		unsent = RCANFD_CMFIFO_CFMC(sts);
+
+		/* Wake producer only when there is room */
+		if (unsent != RCANFD_FIFO_DEPTH)
+			netif_wake_queue(ndev);
+
+		if (priv->tx_head - priv->tx_tail <= unsent) {
+			spin_unlock_irqrestore(&priv->tx_lock, flags);
+			break;
+		}
+		spin_unlock_irqrestore(&priv->tx_lock, flags);
+
+	} while (1);
+
+	/* Clear interrupt */
+	rcar_canfd_write(priv, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
+			 sts & ~RCANFD_CMFIFO_CFTXIF);
+	can_led_event(ndev, CAN_LED_EVENT_TX);
+}
+
+static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
+{
+	struct rcar_canfd_global *gpriv = dev_id;
+	struct net_device *ndev;
+	struct rcar_canfd_channel *priv;
+	u32 sts, gerfl;
+	u32 ch, ridx;
+
+	/* Global error interrupts still indicate a condition specific
+	 * to a channel. RxFIFO interrupt is a global interrupt.
+	 */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		ndev = priv->ndev;
+		ridx = ch + RCANFD_RFFIFO_IDX;
+
+		/* Global error interrupts */
+		gerfl = rcar_canfd_read(priv, RCANFD_GERFL);
+		if (RCANFD_GERFL_ERR(gerfl))
+			rcar_canfd_global_error(ndev);
+
+		/* Handle Rx interrupts */
+		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
+		if (sts & RCANFD_RFFIFO_RFIF) {
+			if (napi_schedule_prep(&priv->napi)) {
+				/* Disable Rx FIFO interrupts */
+				rcar_canfd_clear_bit(priv,
+						     RCANFD_RFCC(ridx),
+						     RCANFD_RFFIFO_RFIE);
+				__napi_schedule(&priv->napi);
+			}
+		}
+	}
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
+{
+	struct rcar_canfd_global *gpriv = dev_id;
+	struct net_device *ndev;
+	struct rcar_canfd_channel *priv;
+	u32 sts, cerfl, ch;
+
+	/* Common FIFO is a per channel resource */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		ndev = priv->ndev;
+
+		/* Channel error interrupts */
+		cerfl = rcar_canfd_read(priv, RCANFD_CERFL(ch));
+		if (RCANFD_CERFL_ERR(cerfl))
+			rcar_canfd_error(ndev);
+
+		/* Handle Tx interrupts */
+		sts = rcar_canfd_read(priv,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		if (sts & RCANFD_CMFIFO_CFTXIF)
+			rcar_canfd_tx_done(ndev);
+	}
+	return IRQ_HANDLED;
+}
+
+static void rcar_canfd_set_bittiming(struct net_device *dev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(dev);
+	const struct can_bittiming *bt = &priv->can.bittiming;
+	const struct can_bittiming *dbt = &priv->can.data_bittiming;
+	u16 brp, sjw, tseg1, tseg2;
+	u32 cfg;
+	u32 ch = priv->channel;
+
+	/* Nominal bit timing settings */
+	brp = bt->brp - 1;
+	sjw = bt->sjw - 1;
+	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
+	tseg2 = bt->phase_seg2 - 1;
+
+	cfg = (RCANFD_NR_TSEG1(tseg1) | RCANFD_NR_BRP(brp) |
+	       RCANFD_NR_SJW(sjw) | RCANFD_NR_TSEG2(tseg2));
+
+	rcar_canfd_write(priv, RCANFD_CCFG(ch), cfg);
+	netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
+		   brp, sjw, tseg1, tseg2);
+
+	/* Data bit timing settings */
+	brp = dbt->brp - 1;
+	sjw = dbt->sjw - 1;
+	tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
+	tseg2 = dbt->phase_seg2 - 1;
+
+	cfg = (RCANFD_DR_TSEG1(tseg1) | RCANFD_DR_BRP(brp) |
+	       RCANFD_DR_SJW(sjw) | RCANFD_DR_TSEG2(tseg2));
+
+	rcar_canfd_write(priv, RCANFD_F_CDFG(ch), cfg);
+	netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
+		   brp, sjw, tseg1, tseg2);
+}
+
+static int rcar_canfd_start(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	int err = -EOPNOTSUPP;
+	u32 sts, ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	/* Ensure channel starts in FD mode */
+	if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
+		netdev_err(ndev, "enable can fd mode for channel %d\n", ch);
+		goto fail_mode;
+	}
+
+	rcar_canfd_set_bittiming(ndev);
+
+	rcar_canfd_enable_channel_interrupts(priv);
+
+	/* Set channel to Operational mode */
+	rcar_canfd_update_bit(priv, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_COPM);
+
+	/* Verify channel mode change */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_COM), 2, 500000);
+	if (err) {
+		netdev_err(ndev, "channel %u communication state failed\n", ch);
+		goto fail_mode_change;
+	}
+
+	/* Enable Common & Rx FIFO */
+	rcar_canfd_set_bit(priv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
+			   RCANFD_CMFIFO_CFE);
+	rcar_canfd_set_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFE);
+
+	priv->can.state = CAN_STATE_ERROR_ACTIVE;
+	return 0;
+
+fail_mode_change:
+	rcar_canfd_disable_channel_interrupts(priv);
+fail_mode:
+	return err;
+}
+
+static int rcar_canfd_open(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct rcar_canfd_global *gpriv = priv->gpriv;
+	int err;
+
+	/* Peripheral clock is already enabled in probe */
+	err = clk_prepare_enable(gpriv->can_clk);
+	if (err) {
+		netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
+		goto out_clock;
+	}
+
+	err = open_candev(ndev);
+	if (err) {
+		netdev_err(ndev, "open_candev() failed, error %d\n", err);
+		goto out_can_clock;
+	}
+
+	napi_enable(&priv->napi);
+	err = rcar_canfd_start(ndev);
+	if (err)
+		goto out_close;
+	netif_start_queue(ndev);
+	can_led_event(ndev, CAN_LED_EVENT_OPEN);
+	return 0;
+out_close:
+	napi_disable(&priv->napi);
+	close_candev(ndev);
+out_can_clock:
+	clk_disable_unprepare(gpriv->can_clk);
+out_clock:
+	return err;
+}
+
+static void rcar_canfd_stop(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	int err;
+	u32 sts, ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	/* Transition to channel reset mode  */
+	rcar_canfd_update_bit(priv, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_CRESET);
+
+	/* Check Channel reset mode */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_RESET), 2, 500000);
+	if (err)
+		netdev_err(ndev, "channel %u reset failed\n", ch);
+
+	rcar_canfd_disable_channel_interrupts(priv);
+
+	/* Disable Common & Rx FIFO */
+	rcar_canfd_clear_bit(priv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
+			     RCANFD_CMFIFO_CFE);
+	rcar_canfd_clear_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFE);
+
+	/* Set the state as STOPPED */
+	priv->can.state = CAN_STATE_STOPPED;
+}
+
+static int rcar_canfd_close(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct rcar_canfd_global *gpriv = priv->gpriv;
+
+	netif_stop_queue(ndev);
+	rcar_canfd_stop(ndev);
+	napi_disable(&priv->napi);
+	clk_disable_unprepare(gpriv->can_clk);
+	close_candev(ndev);
+	can_led_event(ndev, CAN_LED_EVENT_STOP);
+	return 0;
+}
+
+static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
+					 struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
+	u32 sts, id, ptr;
+	unsigned long flags;
+	u32 ch = priv->channel;
+
+	if (can_dropped_invalid_skb(ndev, skb))
+		return NETDEV_TX_OK;
+
+	if (cf->can_id & CAN_EFF_FLAG) {
+		id = cf->can_id & CAN_EFF_MASK;
+		id |= RCANFD_CMFIFO_CFIDE;
+	} else {
+		id = cf->can_id & CAN_SFF_MASK;
+	}
+
+	if (cf->can_id & CAN_RTR_FLAG)
+		id |= RCANFD_CMFIFO_CFRTR;
+
+	rcar_canfd_write(priv, RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX),
+			 id);
+	ptr = RCANFD_CMFIFO_CFDLC(can_len2dlc(cf->len));
+	rcar_canfd_write(priv, RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX),
+			 ptr);
+
+	sts = rcar_canfd_read(priv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX));
+	if (can_is_canfd_skb(skb)) {
+		/* CAN FD frame format */
+		sts |= RCANFD_CMFIFO_CFFDF;
+		if (cf->flags & CANFD_BRS)
+			sts |= RCANFD_CMFIFO_CFBRS;
+		else
+			sts &= ~RCANFD_CMFIFO_CFBRS;
+	} else {
+		sts &= ~RCANFD_CMFIFO_CFFDF;
+	}
+	rcar_canfd_write(priv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), sts);
+
+	rcar_canfd_put_data(cf, priv,
+			    RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
+
+	priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
+	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
+
+	spin_lock_irqsave(&priv->tx_lock, flags);
+	priv->tx_head++;
+
+	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
+	 * pointer for the Common FIFO
+	 */
+	rcar_canfd_write(priv, RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
+
+	/* Stop the queue if we've filled all FIFO entries */
+	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
+		netif_stop_queue(ndev);
+
+	spin_unlock_irqrestore(&priv->tx_lock, flags);
+	return NETDEV_TX_OK;
+}
+
+static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
+{
+	struct net_device_stats *stats = &priv->ndev->stats;
+	struct canfd_frame *cf;
+	struct sk_buff *skb;
+	u32 sts = 0, id, ptr;
+	u32 ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	id = rcar_canfd_read(priv, RCANFD_F_RFID(ridx));
+	ptr = rcar_canfd_read(priv, RCANFD_F_RFPTR(ridx));
+
+	sts = rcar_canfd_read(priv, RCANFD_F_RFFDSTS(ridx));
+	if (sts & RCANFD_RFFIFO_RFFDF)
+		skb = alloc_canfd_skb(priv->ndev, &cf);
+	else
+		skb = alloc_can_skb(priv->ndev,
+				    (struct can_frame **)&cf);
+
+	if (!skb) {
+		stats->rx_dropped++;
+		return;
+	}
+
+	if (sts & RCANFD_RFFIFO_RFFDF)
+		cf->len = can_dlc2len(RCANFD_RFFIFO_RFDLC(ptr));
+	else
+		cf->len = get_can_dlc(RCANFD_RFFIFO_RFDLC(ptr));
+
+	if (sts & RCANFD_RFFIFO_RFESI) {
+		cf->flags |= CANFD_ESI;
+		netdev_dbg(priv->ndev, "ESI Error\n");
+	}
+
+	if (id & RCANFD_RFFIFO_RFIDE)
+		cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+	else
+		cf->can_id = id & CAN_SFF_MASK;
+
+	if (!(sts & RCANFD_RFFIFO_RFFDF) && (id & RCANFD_RFFIFO_RFRTR)) {
+		cf->can_id |= CAN_RTR_FLAG;
+	} else {
+		if (sts & RCANFD_RFFIFO_RFBRS)
+			cf->flags |= CANFD_BRS;
+
+		rcar_canfd_get_data(cf, priv, RCANFD_F_RFDF(ridx, 0));
+	}
+
+	/* Write 0xff to RFPC to increment the CPU-side
+	 * pointer of the Rx FIFO
+	 */
+	rcar_canfd_write(priv, RCANFD_RFPCTR(ridx), 0xff);
+
+	can_led_event(priv->ndev, CAN_LED_EVENT_RX);
+
+	stats->rx_bytes += cf->len;
+	stats->rx_packets++;
+	netif_receive_skb(skb);
+}
+
+static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
+{
+	struct rcar_canfd_channel *priv =
+		container_of(napi, struct rcar_canfd_channel, napi);
+	int num_pkts;
+	u32 sts;
+	u32 ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
+		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
+		/* Clear interrupt bit */
+		if (sts & RCANFD_RFFIFO_RFIF)
+			rcar_canfd_write(priv, RCANFD_RFSTS(ridx),
+					 sts & ~RCANFD_RFFIFO_RFIF);
+
+		/* Check FIFO empty condition */
+		if (sts & RCANFD_RFFIFO_RFEMP)
+			break;
+
+		rcar_canfd_rx_pkt(priv);
+	}
+
+	/* All packets processed */
+	if (num_pkts < quota) {
+		napi_complete(napi);
+		/* Enable Rx FIFO interrupts */
+		rcar_canfd_set_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFIE);
+	}
+	return num_pkts;
+}
+
+static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
+{
+	int err;
+
+	switch (mode) {
+	case CAN_MODE_START:
+		err = rcar_canfd_start(ndev);
+		if (err)
+			return err;
+		netif_wake_queue(ndev);
+		return 0;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int rcar_canfd_get_berr_counter(const struct net_device *dev,
+				       struct can_berr_counter *bec)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(dev);
+	u32 val, ch = priv->channel;
+
+	/* Peripheral clock is already enabled in probe */
+	val = rcar_canfd_read(priv, RCANFD_CSTS(ch));
+	bec->txerr = RCANFD_CSTS_TECCNT(val);
+	bec->rxerr = RCANFD_CSTS_RECCNT(val);
+	return 0;
+}
+
+static const struct net_device_ops rcar_canfd_netdev_ops = {
+	.ndo_open = rcar_canfd_open,
+	.ndo_stop = rcar_canfd_close,
+	.ndo_start_xmit = rcar_canfd_start_xmit,
+	.ndo_change_mtu = can_change_mtu,
+};
+
+static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	struct platform_device *pdev = gpriv->pdev;
+	struct rcar_canfd_channel *priv;
+	struct net_device *ndev;
+	int err = -ENODEV;
+
+	ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
+	if (!ndev) {
+		dev_err(&pdev->dev, "alloc_candev() failed\n");
+		err = -ENOMEM;
+		goto fail;
+	}
+	priv = netdev_priv(ndev);
+
+	ndev->netdev_ops = &rcar_canfd_netdev_ops;
+	ndev->flags |= IFF_ECHO;
+	priv->ndev = ndev;
+	priv->base = gpriv->base;
+	priv->channel = ch;
+	priv->can.clock.freq = gpriv->freq;
+	dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
+
+	priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
+	priv->can.data_bittiming_const =
+		&rcar_canfd_data_bittiming_const;
+
+	/* Controller starts in CAN FD mode, which supports classical CAN and
+	 * CAN FD frames. For classical CAN frames only configurations, data
+	 * bitrate should be configured the same as nominal bitrate.
+	 */
+	priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
+		CAN_CTRLMODE_FD;
+
+	priv->can.do_set_mode = rcar_canfd_do_set_mode;
+	priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
+	priv->gpriv = gpriv;
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+
+	netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
+		       RCANFD_NAPI_WEIGHT);
+	err = register_candev(ndev);
+	if (err) {
+		dev_err(&pdev->dev,
+			"register_candev() failed, error %d\n", err);
+		goto fail_candev;
+	}
+	spin_lock_init(&priv->tx_lock);
+	devm_can_led_init(ndev);
+	gpriv->ch[priv->channel] = priv;
+	dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
+	return 0;
+
+fail_candev:
+	netif_napi_del(&priv->napi);
+	free_candev(ndev);
+fail:
+	return err;
+}
+
+static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	struct rcar_canfd_channel *priv = gpriv->ch[ch];
+
+	if (priv) {
+		unregister_candev(priv->ndev);
+		netif_napi_del(&priv->napi);
+		free_candev(priv->ndev);
+	}
+}
+
+static int rcar_canfd_probe(struct platform_device *pdev)
+{
+	struct resource *mem;
+	void __iomem *addr;
+	u32 sts, ch;
+	struct rcar_canfd_global *gpriv;
+	struct device_node *of_child;
+	unsigned long channels_mask = 0;
+	int err, ch_irq, g_irq;
+
+	of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
+	if (of_child && of_device_is_available(of_child))
+		channels_mask |= BIT(0);	/* Channel 0 */
+
+	of_child = of_get_child_by_name(pdev->dev.of_node, "channel1");
+	if (of_child && of_device_is_available(of_child))
+		channels_mask |= BIT(1);	/* Channel 1 */
+
+	ch_irq = platform_get_irq(pdev, 0);
+	if (ch_irq < 0) {
+		dev_err(&pdev->dev, "no Channel IRQ resource\n");
+		err = ch_irq;
+		goto fail_dev;
+	}
+
+	g_irq = platform_get_irq(pdev, 1);
+	if (g_irq < 0) {
+		dev_err(&pdev->dev, "no Global IRQ resource\n");
+		err = g_irq;
+		goto fail_dev;
+	}
+
+	/* Global controller context */
+	gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
+	if (!gpriv) {
+		err = -ENOMEM;
+		goto fail_dev;
+	}
+	gpriv->pdev = pdev;
+	gpriv->channels_mask = channels_mask;
+
+	/* Peripheral clock */
+	gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
+	if (IS_ERR(gpriv->clkp)) {
+		err = PTR_ERR(gpriv->clkp);
+		dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
+			err);
+		goto fail_dev;
+	}
+
+	/* fCAN clock: Pick External clock. If not available fallback to
+	 * CANFD clock
+	 */
+	gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
+	if (IS_ERR(gpriv->can_clk)) {
+		gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
+		if (IS_ERR(gpriv->can_clk)) {
+			err = PTR_ERR(gpriv->can_clk);
+			dev_err(&pdev->dev,
+				"cannot get canfd clock, error %d\n", err);
+			goto fail_dev;
+		}
+		gpriv->clock_select = RCANFD_CANFDCLK;
+
+	} else {
+		gpriv->clock_select = RCANFD_EXTCLK;
+	}
+	gpriv->freq = clk_get_rate(gpriv->can_clk);
+
+	if (gpriv->clock_select == RCANFD_CANFDCLK)
+		/* CANFD clock is further divided by (1/2) within the IP */
+		gpriv->freq /= 2;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	addr = devm_ioremap_resource(&pdev->dev, mem);
+	if (IS_ERR(addr)) {
+		err = PTR_ERR(addr);
+		goto fail_dev;
+	}
+	gpriv->base = addr;
+
+	/* Request IRQ that's common for both channels */
+	err = devm_request_irq(&pdev->dev, ch_irq,
+			       rcar_canfd_channel_interrupt, 0,
+			       "canfd.chn", gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+			ch_irq, err);
+		goto fail_dev;
+	}
+	err = devm_request_irq(&pdev->dev, g_irq,
+			       rcar_canfd_global_interrupt, 0,
+			       "canfd.gbl", gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+			g_irq, err);
+		goto fail_dev;
+	}
+
+	/* Enable peripheral clock for register access */
+	err = clk_prepare_enable(gpriv->clkp);
+	if (err) {
+		dev_err(&pdev->dev,
+			"failed to enable peripheral clock, error %d\n", err);
+		goto fail_dev;
+	}
+
+	err = rcar_canfd_reset_controller(gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "reset controller failed\n");
+		goto fail_clk;
+	}
+
+	/* Controller in Global reset & Channel reset mode */
+	rcar_canfd_configure_controller(gpriv);
+
+	/* Configure per channel attributes */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		/* Configure Channel's Rx fifo */
+		rcar_canfd_configure_rx(gpriv, ch);
+
+		/* Configure Channel's Tx (Common) fifo */
+		rcar_canfd_configure_tx(gpriv, ch);
+
+		/* Configure receive rules */
+		rcar_canfd_configure_afl_rules(gpriv, ch);
+	}
+
+	/* Configure common interrupts */
+	rcar_canfd_enable_global_interrupts(gpriv);
+
+	/* Start Global operation mode */
+	rcar_canfd_update_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_MODEMASK,
+			      RCANFD_GCTR_GOPM);
+
+	/* Verify mode change */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
+	if (err) {
+		dev_err(&pdev->dev, "global operational mode failed\n");
+		goto fail_mode;
+	}
+
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		err = rcar_canfd_channel_probe(gpriv, ch);
+		if (err)
+			goto fail_channel;
+	}
+
+	platform_set_drvdata(pdev, gpriv);
+	dev_info(&pdev->dev, "global operational state (clk %d)\n",
+		 gpriv->clock_select);
+	return 0;
+
+fail_channel:
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+		rcar_canfd_channel_remove(gpriv, ch);
+fail_mode:
+	rcar_canfd_disable_global_interrupts(gpriv);
+fail_clk:
+	clk_disable_unprepare(gpriv->clkp);
+fail_dev:
+	return err;
+}
+
+static int rcar_canfd_remove(struct platform_device *pdev)
+{
+	struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
+	struct rcar_canfd_channel *priv;
+	u32 ch;
+
+	rcar_canfd_reset_controller(gpriv);
+	rcar_canfd_disable_global_interrupts(gpriv);
+
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		if (priv) {
+			rcar_canfd_disable_channel_interrupts(priv);
+			unregister_candev(priv->ndev);
+			netif_napi_del(&priv->napi);
+			free_candev(priv->ndev);
+		}
+	}
+
+	/* Enter global sleep mode */
+	rcar_canfd_set_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_SLPR);
+	clk_disable_unprepare(gpriv->clkp);
+	return 0;
+}
+
+static int __maybe_unused rcar_canfd_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int __maybe_unused rcar_canfd_resume(struct device *dev)
+{
+	return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
+			 rcar_canfd_resume);
+
+static const struct of_device_id rcar_canfd_of_table[] = {
+	{ .compatible = "renesas,rcar-gen3-canfd" },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
+
+static struct platform_driver rcar_canfd_driver = {
+	.driver = {
+		.name = RCANFD_DRV_NAME,
+		.of_match_table = of_match_ptr(rcar_canfd_of_table),
+		.pm = &rcar_canfd_pm_ops,
+	},
+	.probe = rcar_canfd_probe,
+	.remove = rcar_canfd_remove,
+};
+
+module_platform_driver(rcar_canfd_driver);
+
+MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
+MODULE_ALIAS("platform:" RCANFD_DRV_NAME);
-- 
1.9.1

Re: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Rob Herring]

On Thu, Mar 03, 2016 at 03:38:35PM +0000, Ramesh Shanmugasundaram wrote:
> This patch adds support for the CAN FD controller found in Renesas R-Car
> SoCs. The controller operates in CAN FD mode by default.
> 
> CAN FD mode supports both Classical CAN & CAN FD frame formats. The
> controller supports ISO 11898-1:2015 CAN FD format only.
> 
> This controller supports two channels and the driver can enable either
> or both of the channels.
> 
> Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs (one
> per channel) for transmission. Rx filter rules are configured to the
> minimum (one per channel) and it accepts Standard, Extended, Data &
> Remote Frame combinations.
> 
> Note: There are few documentation errors in R-Car Gen3 Hardware User
> Manual v0.5E with respect to CAN FD controller. They are listed below:
> 
> 1. CAN FD interrupt numbers 29 & 30 are listed as per channel
> interrupts. However, they are common to both channels (i.e.) they are
> global and channel interrupts respectively.
> 
> 2. CANFD clock is derived from PLL1. This is not documented.
> 
> 3. CANFD clock is further divided by (1/2) within the CAN FD controller.
> This is not documented.
> 
> 4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
> is mentioned 4 Tq in the manual.
> 
> 5. The maximum number of message RAM area the controller can use is 3584
> bytes. It is specified 10752 bytes in the manual.
> 
> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
> ---
> Changes since v1:
> 	* Removed testmodes & debugfs code (suggested by Oliver H)
> 	* Fixed tx path race issue by introducing lock (suggested by Marc K)
> 	* Removed __maybe_unused attribute of rcar_canfd_of_table
> 
> Thanks,
> Ramesh
> ---
>  .../devicetree/bindings/net/can/rcar_canfd.txt     |   86 ++
>  drivers/net/can/Kconfig                            |   10 +
>  drivers/net/can/Makefile                           |    1 +
>  drivers/net/can/rcar_canfd.c                       | 1624 ++++++++++++++++++++
>  4 files changed, 1721 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
>  create mode 100644 drivers/net/can/rcar_canfd.c
> 
> diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> new file mode 100644
> index 0000000..4299bd8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> @@ -0,0 +1,86 @@
> +Renesas R-Car CAN FD controller Device Tree Bindings
> +----------------------------------------------------
> +
> +Required properties:
> +- compatible: Must contain one or more of the following:
> +  - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
> +  - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
> +
> +  When compatible with the generic version, nodes must list the
> +  SoC-specific version corresponding to the platform first, followed by the
> +  family-specific and/or generic versions.
> +
> +- reg: physical base address and size of the R-Car CAN FD register map.
> +- interrupts: interrupt specifier for the Global & Channel interrupts
> +- clocks: phandles and clock specifiers for 3 clock inputs.
> +- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
> +- pinctrl-0: pin control group to be used for this controller.
> +- pinctrl-names: must be "default".
> +
> +Required properties for "renesas,r8a7795-canfd" compatible:
> +In R8A7795 SoC, canfd clock is a div6 clock and can be used by both CAN
> +and CAN FD controller at the same time. It needs to be scaled to maximum
> +frequency if any of these controllers use it. This is done using the
> +below properties.
> +
> +- assigned-clocks: phandle of canfd clock.
> +- assigned-clock-rates: maximum frequency of this clock.
> +
> +Each channel is represented as a child node. They can be enabled/disabled
> +using "status" property.

How many channels? Required or optional?

> +
> +Example
> +-------
> +
> +SoC common .dtsi file:
> +
> +		canfd: canfd@e66c0000 {

can@e66c0000

> +			compatible = "renesas,r8a7795-canfd",
> +				     "renesas,rcar-gen3-canfd";
> +			reg = <0 0xe66c0000 0 0x8000>;
> +			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> +				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 914>,
> +			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
> +			       <&can_clk>;
> +			clock-names = "fck", "canfd", "can_clk";
> +			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
> +			assigned-clock-rates = <40000000>;
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +
> +			channel0 {
> +				status = "disabled";
> +			};
> +
> +			channel1 {
> +				status = "disabled";
> +			};
> +		};
> +
> +Board specific .dts file:
> +
> +E.g. below enables Channel 1 alone in the board.
> +
> +&canfd {
> +        pinctrl-0 = <&canfd1_pins>;
> +        pinctrl-names = "default";
> +        status = "okay";
> +
> +	channel1 {
> +		status = "okay";
> +	};
> +};
> +
> +E.g. below enables Channel 0 alone in the board using External clock
> +as fCAN clock.
> +
> +&canfd {
> +        pinctrl-0 = <&canfd0_pins &can_clk_pins>;
> +        pinctrl-names = "default";
> +        status = "okay";
> +
> +	channel0 {
> +		status = "okay";
> +	};
> +};

Re: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Oliver Hartkopp]

On 03/03/2016 04:38 PM, Ramesh Shanmugasundaram wrote:

> Changes since v1:
> 	* Removed testmodes & debugfs code (suggested by Oliver H)
> 	* Fixed tx path race issue by introducing lock (suggested by Marc K)
> 	* Removed __maybe_unused attribute of rcar_canfd_of_table
> 


>  obj-$(CONFIG_CAN_M_CAN)		+= m_can/
>  obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
> +obj-$(CONFIG_CANFD_RCAR)	+= rcar_canfd.o

Just for the sake of an ordered directory structure:

Would it make sense to create a rcar directory where rcar_can.c and
rcar_canfd.c are placed?

Additionally (besides of one accident with the obsolete PCH_CAN) all CAN
drivers start with CONFIG_CAN_...

Following that scheme the config option should be named

	CONFIG_CAN_RCAR_CANFD

as we had in CONFIG_CAN_IFI_CANFD.


>  obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
>  obj-$(CONFIG_CAN_SUN4I)		+= sun4i_can.o
>  obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
> diff --git a/drivers/net/can/rcar_canfd.c b/drivers/net/can/rcar_canfd.c

(..)

> +/* Channel priv data */
> +struct rcar_canfd_channel {
> +	struct can_priv can;			/* Must be the first member */
> +	struct net_device *ndev;
> +	struct rcar_canfd_global *gpriv;	/* Controller reference */
> +	void __iomem *base;			/* Register base address */
> +#ifdef CONFIG_DEBUG_FS
> +	struct dentry *dev_root;
> +#endif /* CONFIG_DEBUG_FS */

Some missed stuff from debugfs removal?

> +	struct napi_struct napi;
> +	u8  tx_len[RCANFD_FIFO_DEPTH];		/* For net stats */
> +	u32 tx_head;				/* Incremented on xmit */
> +	u32 tx_tail;				/* Incremented on xmit done */
> +	u32 channel;				/* Channel number */
> +	spinlock_t tx_lock;			/* To protect tx path */
> +};

(..)

> +static int rcar_canfd_start(struct net_device *ndev)
> +{
> +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
> +	int err = -EOPNOTSUPP;
> +	u32 sts, ch = priv->channel;
> +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
> +
> +	/* Ensure channel starts in FD mode */
> +	if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
> +		netdev_err(ndev, "enable can fd mode for channel %d\n", ch);
> +		goto fail_mode;
> +	}

What's the reason behind this check?

A CAN FD capable CAN controller can be either configured to run as CAN 2.0
(Classic CAN) or as CAN FD controller.

So why are to throwing an error here and produce an initialization failure?

Regards,
Oliver

RE: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Oliver,

Thanks for the review comments.

> On 03/03/2016 04:38 PM, Ramesh Shanmugasundaram wrote:
> 
> > Changes since v1:
> > 	* Removed testmodes & debugfs code (suggested by Oliver H)
> > 	* Fixed tx path race issue by introducing lock (suggested by Marc K)
> > 	* Removed __maybe_unused attribute of rcar_canfd_of_table
> >
> 
> 
> >  obj-$(CONFIG_CAN_M_CAN)		+= m_can/
> >  obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
> > +obj-$(CONFIG_CANFD_RCAR)	+= rcar_canfd.o
> 
> Just for the sake of an ordered directory structure:
> 
> Would it make sense to create a rcar directory where rcar_can.c and
> rcar_canfd.c are placed?
> 
Yes. I'll place them in rcar dir.

> Additionally (besides of one accident with the obsolete PCH_CAN) all CAN
> drivers start with CONFIG_CAN_...
> 
> Following that scheme the config option should be named
> 
> 	CONFIG_CAN_RCAR_CANFD
> 
> as we had in CONFIG_CAN_IFI_CANFD.

Agreed.

> 
> >  obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
> >  obj-$(CONFIG_CAN_SUN4I)		+= sun4i_can.o
> >  obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
> > diff --git a/drivers/net/can/rcar_canfd.c
> > b/drivers/net/can/rcar_canfd.c
> 
> (..)
> 
> > +/* Channel priv data */
> > +struct rcar_canfd_channel {
> > +	struct can_priv can;			/* Must be the first member */
> > +	struct net_device *ndev;
> > +	struct rcar_canfd_global *gpriv;	/* Controller reference */
> > +	void __iomem *base;			/* Register base address */
> > +#ifdef CONFIG_DEBUG_FS
> > +	struct dentry *dev_root;
> > +#endif /* CONFIG_DEBUG_FS */
> 
> Some missed stuff from debugfs removal?

:-(. Sorry. Will clean up.

> 
> > +	struct napi_struct napi;
> > +	u8  tx_len[RCANFD_FIFO_DEPTH];		/* For net stats */
> > +	u32 tx_head;				/* Incremented on xmit */
> > +	u32 tx_tail;				/* Incremented on xmit done */
> > +	u32 channel;				/* Channel number */
> > +	spinlock_t tx_lock;			/* To protect tx path */
> > +};
> 
> (..)
> 
> > +static int rcar_canfd_start(struct net_device *ndev) {
> > +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
> > +	int err = -EOPNOTSUPP;
> > +	u32 sts, ch = priv->channel;
> > +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
> > +
> > +	/* Ensure channel starts in FD mode */
> > +	if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
> > +		netdev_err(ndev, "enable can fd mode for channel %d\n", ch);
> > +		goto fail_mode;
> > +	}
> 
> What's the reason behind this check?
> 
> A CAN FD capable CAN controller can be either configured to run as CAN 2.0
> (Classic CAN) or as CAN FD controller.
> 
> So why are to throwing an error here and produce an initialization
> failure?

When this controller is configured in FD mode and used only with CAN 2.0 nodes, it still expects a DTSEG (data bitrate) configuration same as NTSEG (nominal bitrate). This check, specifically in ndo_open, ensures both are configured and will work fine with CAN 2.0 nodes (e.g.)

"ip link set can0 up type can bitrate 1000000 dbitrate 1000000 fd on"

If I don't have this check, a configuration like this

"ip link set can0 up type can bitrate 1000000"

will bring up the controller without DTSEG configured. 

Thanks,
Ramesh

Re: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Marc Kleine-Budde]

[-- Attachment #1.1: Type: text/plain, Size: 3633 bytes --]

On 03/07/2016 09:02 AM, Ramesh Shanmugasundaram wrote:
> Hi Oliver,
> 
> Thanks for the review comments.
> 
>> On 03/03/2016 04:38 PM, Ramesh Shanmugasundaram wrote:
>>
>>> Changes since v1:
>>> 	* Removed testmodes & debugfs code (suggested by Oliver H)
>>> 	* Fixed tx path race issue by introducing lock (suggested by Marc K)
>>> 	* Removed __maybe_unused attribute of rcar_canfd_of_table
>>>
>>
>>
>>>  obj-$(CONFIG_CAN_M_CAN)		+= m_can/
>>>  obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
>>> +obj-$(CONFIG_CANFD_RCAR)	+= rcar_canfd.o
>>
>> Just for the sake of an ordered directory structure:
>>
>> Would it make sense to create a rcar directory where rcar_can.c and
>> rcar_canfd.c are placed?
>>
> Yes. I'll place them in rcar dir.
> 
>> Additionally (besides of one accident with the obsolete PCH_CAN) all CAN
>> drivers start with CONFIG_CAN_...
>>
>> Following that scheme the config option should be named
>>
>> 	CONFIG_CAN_RCAR_CANFD
>>
>> as we had in CONFIG_CAN_IFI_CANFD.
> 
> Agreed.
> 
>>
>>>  obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
>>>  obj-$(CONFIG_CAN_SUN4I)		+= sun4i_can.o
>>>  obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
>>> diff --git a/drivers/net/can/rcar_canfd.c
>>> b/drivers/net/can/rcar_canfd.c
>>
>> (..)
>>
>>> +/* Channel priv data */
>>> +struct rcar_canfd_channel {
>>> +	struct can_priv can;			/* Must be the first member */
>>> +	struct net_device *ndev;
>>> +	struct rcar_canfd_global *gpriv;	/* Controller reference */
>>> +	void __iomem *base;			/* Register base address */
>>> +#ifdef CONFIG_DEBUG_FS
>>> +	struct dentry *dev_root;
>>> +#endif /* CONFIG_DEBUG_FS */
>>
>> Some missed stuff from debugfs removal?
> 
> :-(. Sorry. Will clean up.
> 
>>
>>> +	struct napi_struct napi;
>>> +	u8  tx_len[RCANFD_FIFO_DEPTH];		/* For net stats */
>>> +	u32 tx_head;				/* Incremented on xmit */
>>> +	u32 tx_tail;				/* Incremented on xmit done */
>>> +	u32 channel;				/* Channel number */
>>> +	spinlock_t tx_lock;			/* To protect tx path */
>>> +};
>>
>> (..)
>>
>>> +static int rcar_canfd_start(struct net_device *ndev) {
>>> +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
>>> +	int err = -EOPNOTSUPP;
>>> +	u32 sts, ch = priv->channel;
>>> +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
>>> +
>>> +	/* Ensure channel starts in FD mode */
>>> +	if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
>>> +		netdev_err(ndev, "enable can fd mode for channel %d\n", ch);
>>> +		goto fail_mode;
>>> +	}
>>
>> What's the reason behind this check?
>>
>> A CAN FD capable CAN controller can be either configured to run as CAN 2.0
>> (Classic CAN) or as CAN FD controller.
>>
>> So why are to throwing an error here and produce an initialization
>> failure?
> 
> When this controller is configured in FD mode and used only with CAN 2.0 nodes, it still expects a DTSEG (data bitrate) configuration same as NTSEG (nominal bitrate). This check, specifically in ndo_open, ensures both are configured and will work fine with CAN 2.0 nodes (e.g.)
> 
> "ip link set can0 up type can bitrate 1000000 dbitrate 1000000 fd on"
> 
> If I don't have this check, a configuration like this
> 
> "ip link set can0 up type can bitrate 1000000"
> 
> will bring up the controller without DTSEG configured. 

That should bring up the controller in CAN 2.0 mode.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
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[-- Attachment #2: OpenPGP digital signature --]
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RE: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Marc,

> On 03/07/2016 09:02 AM, Ramesh Shanmugasundaram wrote:
> > Hi Oliver,
> >
> > Thanks for the review comments.
> >
> >> On 03/03/2016 04:38 PM, Ramesh Shanmugasundaram wrote:
> >>
> >>> Changes since v1:
> >>> 	* Removed testmodes & debugfs code (suggested by Oliver H)
> >>> 	* Fixed tx path race issue by introducing lock (suggested by Marc K)
> >>> 	* Removed __maybe_unused attribute of rcar_canfd_of_table
> >>>
> >>
> >>
> >>>  obj-$(CONFIG_CAN_M_CAN)		+= m_can/
> >>>  obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
> >>> +obj-$(CONFIG_CANFD_RCAR)	+= rcar_canfd.o
> >>
> >> Just for the sake of an ordered directory structure:
> >>
> >> Would it make sense to create a rcar directory where rcar_can.c and
> >> rcar_canfd.c are placed?
> >>
> > Yes. I'll place them in rcar dir.
> >
> >> Additionally (besides of one accident with the obsolete PCH_CAN) all
> >> CAN drivers start with CONFIG_CAN_...
> >>
> >> Following that scheme the config option should be named
> >>
> >> 	CONFIG_CAN_RCAR_CANFD
> >>
> >> as we had in CONFIG_CAN_IFI_CANFD.
> >
> > Agreed.
> >
> >>
> >>>  obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
> >>>  obj-$(CONFIG_CAN_SUN4I)		+= sun4i_can.o
> >>>  obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
> >>> diff --git a/drivers/net/can/rcar_canfd.c
> >>> b/drivers/net/can/rcar_canfd.c
> >>
> >> (..)
> >>
> >>> +/* Channel priv data */
> >>> +struct rcar_canfd_channel {
> >>> +	struct can_priv can;			/* Must be the first member */
> >>> +	struct net_device *ndev;
> >>> +	struct rcar_canfd_global *gpriv;	/* Controller reference */
> >>> +	void __iomem *base;			/* Register base address */
> >>> +#ifdef CONFIG_DEBUG_FS
> >>> +	struct dentry *dev_root;
> >>> +#endif /* CONFIG_DEBUG_FS */
> >>
> >> Some missed stuff from debugfs removal?
> >
> > :-(. Sorry. Will clean up.
> >
> >>
> >>> +	struct napi_struct napi;
> >>> +	u8  tx_len[RCANFD_FIFO_DEPTH];		/* For net stats */
> >>> +	u32 tx_head;				/* Incremented on xmit */
> >>> +	u32 tx_tail;				/* Incremented on xmit done */
> >>> +	u32 channel;				/* Channel number */
> >>> +	spinlock_t tx_lock;			/* To protect tx path */
> >>> +};
> >>
> >> (..)
> >>
> >>> +static int rcar_canfd_start(struct net_device *ndev) {
> >>> +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
> >>> +	int err = -EOPNOTSUPP;
> >>> +	u32 sts, ch = priv->channel;
> >>> +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
> >>> +
> >>> +	/* Ensure channel starts in FD mode */
> >>> +	if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
> >>> +		netdev_err(ndev, "enable can fd mode for channel %d\n", ch);
> >>> +		goto fail_mode;
> >>> +	}
> >>
> >> What's the reason behind this check?
> >>
> >> A CAN FD capable CAN controller can be either configured to run as
> >> CAN 2.0 (Classic CAN) or as CAN FD controller.
> >>
> >> So why are to throwing an error here and produce an initialization
> >> failure?
> >
> > When this controller is configured in FD mode and used only with CAN
> > 2.0 nodes, it still expects a DTSEG (data bitrate) configuration same
> > as NTSEG (nominal bitrate). This check, specifically in ndo_open,
> > ensures both are configured and will work fine with CAN 2.0 nodes
> > (e.g.)
> >
> > "ip link set can0 up type can bitrate 1000000 dbitrate 1000000 fd on"
> >
> > If I don't have this check, a configuration like this
> >
> > "ip link set can0 up type can bitrate 1000000"
> >
> > will bring up the controller without DTSEG configured.
> 
> That should bring up the controller in CAN 2.0 mode.

Yes, that's the user's intention but the manual states DTSEG still need to be configured. In the above configuration, it will not be.
Besides, this will not be a "pure" CAN 2.0 node (i.e.) if a frame with length > 8 bytes is received the controller will "ACK" because in FD mode it can receive up to 64 bytes frame.

The controller does support a "pure" classical CAN mode with a different set of register map itself. Do you think a pure CAN 2.0 mode support would be beneficial? I can submit this in coming days on top of current submission.

The current submission status is:
 - Controller operates in CAN FD mode only.
 - If needed to interoperate with CAN 2.0 nodes, data bitrate still need to be configured and it will work perfectly. However, it is not a "pure" CAN 2.0 node as mentioned above.

Thanks,
Ramesh

RE: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Rob,

Thanks for the review comments.

> On Thu, Mar 03, 2016 at 03:38:35PM +0000, Ramesh Shanmugasundaram wrote:
> > This patch adds support for the CAN FD controller found in Renesas
> > R-Car SoCs. The controller operates in CAN FD mode by default.
> >
> > CAN FD mode supports both Classical CAN & CAN FD frame formats. The
> > controller supports ISO 11898-1:2015 CAN FD format only.
> >
> > This controller supports two channels and the driver can enable either
> > or both of the channels.
> >
> > Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs
> > (one per channel) for transmission. Rx filter rules are configured to
> > the minimum (one per channel) and it accepts Standard, Extended, Data
> > & Remote Frame combinations.
> >
> > Note: There are few documentation errors in R-Car Gen3 Hardware User
> > Manual v0.5E with respect to CAN FD controller. They are listed below:
> >
> > 1. CAN FD interrupt numbers 29 & 30 are listed as per channel
> > interrupts. However, they are common to both channels (i.e.) they are
> > global and channel interrupts respectively.
> >
> > 2. CANFD clock is derived from PLL1. This is not documented.
> >
> > 3. CANFD clock is further divided by (1/2) within the CAN FD controller.
> > This is not documented.
> >
> > 4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
> > is mentioned 4 Tq in the manual.
> >
> > 5. The maximum number of message RAM area the controller can use is
> > 3584 bytes. It is specified 10752 bytes in the manual.
> >
> > Signed-off-by: Ramesh Shanmugasundaram
> > <ramesh.shanmugasundaram@bp.renesas.com>
> > ---
> > Changes since v1:
> > 	* Removed testmodes & debugfs code (suggested by Oliver H)
> > 	* Fixed tx path race issue by introducing lock (suggested by Marc K)
> > 	* Removed __maybe_unused attribute of rcar_canfd_of_table
> >
> > Thanks,
> > Ramesh
> > ---
> >  .../devicetree/bindings/net/can/rcar_canfd.txt     |   86 ++
> >  drivers/net/can/Kconfig                            |   10 +
> >  drivers/net/can/Makefile                           |    1 +
> >  drivers/net/can/rcar_canfd.c                       | 1624
> ++++++++++++++++++++
> >  4 files changed, 1721 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> >  create mode 100644 drivers/net/can/rcar_canfd.c
> >
> > diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> > b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> > new file mode 100644
> > index 0000000..4299bd8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> > @@ -0,0 +1,86 @@
> > +Renesas R-Car CAN FD controller Device Tree Bindings
> > +----------------------------------------------------
> > +
> > +Required properties:
> > +- compatible: Must contain one or more of the following:
> > +  - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
> > +  - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible
> controller.
> > +
> > +  When compatible with the generic version, nodes must list the
> > + SoC-specific version corresponding to the platform first, followed
> > + by the  family-specific and/or generic versions.
> > +
> > +- reg: physical base address and size of the R-Car CAN FD register map.
> > +- interrupts: interrupt specifier for the Global & Channel interrupts
> > +- clocks: phandles and clock specifiers for 3 clock inputs.
> > +- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
> > +- pinctrl-0: pin control group to be used for this controller.
> > +- pinctrl-names: must be "default".
> > +
> > +Required properties for "renesas,r8a7795-canfd" compatible:
> > +In R8A7795 SoC, canfd clock is a div6 clock and can be used by both
> > +CAN and CAN FD controller at the same time. It needs to be scaled to
> > +maximum frequency if any of these controllers use it. This is done
> > +using the below properties.
> > +
> > +- assigned-clocks: phandle of canfd clock.
> > +- assigned-clock-rates: maximum frequency of this clock.
> > +
> > +Each channel is represented as a child node. They can be
> > +enabled/disabled using "status" property.
> 
> How many channels? Required or optional?

Two channels and it is a required property. I will update as below in the next revision.

Required child node:
The controller supports two channels and each is represented as a child
node. The names of the child nodes are "channel0" and "channel1" respectively.
Each child node supports the "status" property only, which is used to
enable/disable the respective channel.

> 
> > +
> > +Example
> > +-------
> > +
> > +SoC common .dtsi file:
> > +
> > +		canfd: canfd@e66c0000 {
> 
> can@e66c0000

Thanks. I will update.

Thanks,
Ramesh

Re: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Oliver Hartkopp]

On 03/07/2016 09:32 AM, Ramesh Shanmugasundaram wrote:

>>>>> +	/* Ensure channel starts in FD mode */
>>>>> +	if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
>>>>> +		netdev_err(ndev, "enable can fd mode for channel %d\n", ch);
>>>>> +		goto fail_mode;
>>>>> +	}
>>>>
>>>> What's the reason behind this check?
>>>>
>>>> A CAN FD capable CAN controller can be either configured to run as
>>>> CAN 2.0 (Classic CAN) or as CAN FD controller.
>>>>
>>>> So why are to throwing an error here and produce an initialization
>>>> failure?
>>>
>>> When this controller is configured in FD mode and used only with CAN
>>> 2.0 nodes, it still expects a DTSEG (data bitrate) configuration same
>>> as NTSEG (nominal bitrate). This check, specifically in ndo_open,
>>> ensures both are configured and will work fine with CAN 2.0 nodes
>>> (e.g.)
>>>
>>> "ip link set can0 up type can bitrate 1000000 dbitrate 1000000 fd on"
>>>
>>> If I don't have this check, a configuration like this
>>>
>>> "ip link set can0 up type can bitrate 1000000"
>>>
>>> will bring up the controller without DTSEG configured.

What about spending some status flag or setting the data bitrate equal to the
nominal bitrate unless a data bitrate is provided?

>>
>> That should bring up the controller in CAN 2.0 mode.
> 
> Yes, that's the user's intention but the manual states DTSEG still need to be configured. In the above configuration, it will not be.
> Besides, this will not be a "pure" CAN 2.0 node (i.e.) if a frame with length > 8 bytes is received the controller will "ACK" because in FD mode it can receive up to 64 bytes frame.

Oh. We probably mix something up here (CAN frame formats & bitrates).

A CAN2.0 frame and a CAN FD frame have very different representations on the
wire! So if you see a FDF (former EDL) bit this is a CAN FD frame, which
requires two bitrates (nominal/data bitrate) where the data bitrate has to be
greater or equal the nominal bitrate.

The fact that the data bitrate is equal the nominal/arbitration bitrate has
nothing to do with CAN2.0 then. Regarding your answer this is not even "a pure
CAN2.0" node - it still looks like a CAN FD node with equal data/nominal bitrates.

The fact that a CAN FD frame has a size of 8 bytes doesn't make it a CAN2.0
frame :-)

> 
> The controller does support a "pure" classical CAN mode with a different set of register map itself.

Is this a can_rcar controller register mapping then?

> Do you think a pure CAN 2.0 mode support would be beneficial? I can submit this in coming days on top of current submission.
> 
> The current submission status is:
>  - Controller operates in CAN FD mode only.
>  - If needed to interoperate with CAN 2.0 nodes, data bitrate still need to be configured and it will work perfectly. However, it is not a "pure" CAN 2.0 node as mentioned above.

When you have a CAN FD /capable/ controller the idea is:

"ip link set can0 up type can bitrate 1000000"

The controller is in CAN2.0 mode:

1. It can send and receive CAN2.0 frames @1MBit/s.
2. The MTU is set to 16 (sizeof(struct can_frame)) ; CAN_CTRLMODE_FD is unset.
3. The CAN controller is not CAN FD tolerant (will produce error frames)

"ip link set can0 up type can bitrate 1000000 dbitrate 1000000 fd on"

1. It can send and receive CAN2.0 frames @1MBit/s.
2. It can send and receive CAN FD frames @1MBit/s (arbitration&data bitrate).
3. The MTU is set to 72 (sizeof(struct canfd_frame)) ; CAN_CTRLMODE_FD is set.

For CAN FD frames the data bitrate can be increased like:
"ip link set can0 up type can bitrate 1000000 dbitrate 4000000 fd on"

So when CAN_CTRLMODE_FD is unset the controller should act like a "pure
CAN2.0" node. When people configure a CAN FD controller with "fd on" and use
CAN2.0 frames all the time this is ok either - but the controller is able to
process CAN FD frames with the correct bitrate too.

Regards,
Oliver

RE: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Oliver,

Thanks for the comments.

> On 03/07/2016 09:32 AM, Ramesh Shanmugasundaram wrote:
> 
> >>>>> +	/* Ensure channel starts in FD mode */
> >>>>> +	if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
> >>>>> +		netdev_err(ndev, "enable can fd mode for channel %d\n",
> ch);
> >>>>> +		goto fail_mode;
> >>>>> +	}
> >>>>
> >>>> What's the reason behind this check?
> >>>>
> >>>> A CAN FD capable CAN controller can be either configured to run as
> >>>> CAN 2.0 (Classic CAN) or as CAN FD controller.
> >>>>
> >>>> So why are to throwing an error here and produce an initialization
> >>>> failure?
> >>>
> >>> When this controller is configured in FD mode and used only with CAN
> >>> 2.0 nodes, it still expects a DTSEG (data bitrate) configuration
> >>> same as NTSEG (nominal bitrate). This check, specifically in
> >>> ndo_open, ensures both are configured and will work fine with CAN
> >>> 2.0 nodes
> >>> (e.g.)
> >>>
> >>> "ip link set can0 up type can bitrate 1000000 dbitrate 1000000 fd on"
> >>>
> >>> If I don't have this check, a configuration like this
> >>>
> >>> "ip link set can0 up type can bitrate 1000000"
> >>>
> >>> will bring up the controller without DTSEG configured.
> 
> What about spending some status flag or setting the data bitrate equal to
> the nominal bitrate unless a data bitrate is provided?

As you mentioned further down, when a user does this 

"ip link set can0 up type can bitrate 1000000"

the intention is to put the controller in CAN 2.0 mode. Even if we use a status flag or copy the data bitrate equal to the nominal bitrate, what would it achieve? It still cannot be a CAN 2.0 node - it is a CAN FD node configured with same nominal & data bitrate.

This is why I have this check in ndo_open, so that the user is aware it is a CAN FD node always and avoid misconfiguration like above with EOPNOTSUPP. 

> 
> >>
> >> That should bring up the controller in CAN 2.0 mode.
> >
> > Yes, that's the user's intention but the manual states DTSEG still need
> to be configured. In the above configuration, it will not be.
> > Besides, this will not be a "pure" CAN 2.0 node (i.e.) if a frame with
> length > 8 bytes is received the controller will "ACK" because in FD mode
> it can receive up to 64 bytes frame.
> 
> Oh. We probably mix something up here (CAN frame formats & bitrates).
> 
> A CAN2.0 frame and a CAN FD frame have very different representations on
> the wire! So if you see a FDF (former EDL) bit this is a CAN FD frame,
> which requires two bitrates (nominal/data bitrate) where the data bitrate
> has to be greater or equal the nominal bitrate.
> 
> The fact that the data bitrate is equal the nominal/arbitration bitrate
> has nothing to do with CAN2.0 then. Regarding your answer this is not even
> "a pure CAN2.0" node - it still looks like a CAN FD node with equal
> data/nominal bitrates.

I agree. May be I mixed up my wordings but my intention is same - the controller is still an FD node & not pure CAN 2.0 node. This is why I have the check.

> 
> The fact that a CAN FD frame has a size of 8 bytes doesn't make it a
> CAN2.0 frame :-)
> 
> >
> > The controller does support a "pure" classical CAN mode with a different
> set of register map itself.
> 
> Is this a can_rcar controller register mapping then?

Nope. This is a different IP compared to can_rcar. It has a different set of register map within the IP to act as a pure classical CAN 2.0 node. When I say "pure", it will pass CAN 2.0 conformance tests :-). It is worth adding this support? Do you think of a strong use case?
 
> 
> > Do you think a pure CAN 2.0 mode support would be beneficial? I can
> submit this in coming days on top of current submission.
> >
> > The current submission status is:
> >  - Controller operates in CAN FD mode only.
> >  - If needed to interoperate with CAN 2.0 nodes, data bitrate still need
> to be configured and it will work perfectly. However, it is not a "pure"
> CAN 2.0 node as mentioned above.
> 
> When you have a CAN FD /capable/ controller the idea is:
> 
> "ip link set can0 up type can bitrate 1000000"
> 
> The controller is in CAN2.0 mode:
> 
> 1. It can send and receive CAN2.0 frames @1MBit/s.
> 2. The MTU is set to 16 (sizeof(struct can_frame)) ; CAN_CTRLMODE_FD is
> unset.
> 3. The CAN controller is not CAN FD tolerant (will produce error frames)
> 
> "ip link set can0 up type can bitrate 1000000 dbitrate 1000000 fd on"
> 
> 1. It can send and receive CAN2.0 frames @1MBit/s.
> 2. It can send and receive CAN FD frames @1MBit/s (arbitration&data
> bitrate).
> 3. The MTU is set to 72 (sizeof(struct canfd_frame)) ; CAN_CTRLMODE_FD is
> set.
> 
> For CAN FD frames the data bitrate can be increased like:
> "ip link set can0 up type can bitrate 1000000 dbitrate 4000000 fd on"
> 
> So when CAN_CTRLMODE_FD is unset the controller should act like a "pure
> CAN2.0" node.

Yes & I am glad you clarified this expectation. I think we both agree on this. With my current submission status, the controller can act as a CAN FD node only. Do you agree that the check I had in ndo_open makes sense now?

Thanks,
Ramesh

Re: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Oliver Hartkopp]

Hi Ramesh,

On 08.03.2016 09:57, Ramesh Shanmugasundaram wrote:

>
> As you mentioned further down, when a user does this
>
> "ip link set can0 up type can bitrate 1000000"
>
> the intention is to put the controller in CAN 2.0 mode. Even if we use a status flag or copy the data bitrate equal to the nominal bitrate, what would it achieve? It still cannot be a CAN 2.0 node - it is a CAN FD node configured with same nominal & data bitrate.
>
> This is why I have this check in ndo_open, so that the user is aware it is a CAN FD node always and avoid misconfiguration like above with EOPNOTSUPP.
>

ok - got it now.

In fact you provided a CAN driver which is "CAN-FD-only".
We did not had that before but there's a solution for this kind of setup.

There is a similar case with CAN_CTRLMODE_FD_NON_ISO we had on the M_CAN 
driver which only provides non-ISO configuration for the supported IP core and 
_no_ option to _change_ this value:

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=6cfda7fbebe8a4fd33ea5722fa0212f98f643c35

If you would do it similar in rcar_canfd.c with

/* CAN_CTRLMODE_FD is fixed with R-Car CAN FD */
priv->can.ctrlmode = CAN_CTRLMODE_FD;

and remove CAN_CTRLMODE_FD from the priv->can.ctrlmode_supported assignment 
then it should do the entire configuration process correctly for you.
Including the proper tests for the two bitrates.
(see open_candev() in linux/drivers/net/can/dev.c)

Right?

Best regards,
Oliver

RE: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Oliver,

Thanks for the comments.

> On 08.03.2016 09:57, Ramesh Shanmugasundaram wrote:
> 
> >
> > As you mentioned further down, when a user does this
> >
> > "ip link set can0 up type can bitrate 1000000"
> >
> > the intention is to put the controller in CAN 2.0 mode. Even if we use a
> status flag or copy the data bitrate equal to the nominal bitrate, what
> would it achieve? It still cannot be a CAN 2.0 node - it is a CAN FD node
> configured with same nominal & data bitrate.
> >
> > This is why I have this check in ndo_open, so that the user is aware it
> is a CAN FD node always and avoid misconfiguration like above with
> EOPNOTSUPP.
> >
> 
> ok - got it now.
> 
> In fact you provided a CAN driver which is "CAN-FD-only".

Yes. That's the status of current submission.

> We did not had that before but there's a solution for this kind of setup.
> 
> There is a similar case with CAN_CTRLMODE_FD_NON_ISO we had on the M_CAN
> driver which only provides non-ISO configuration for the supported IP core
> and _no_ option to _change_ this value:
> 
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id
> =6cfda7fbebe8a4fd33ea5722fa0212f98f643c35
> 
> If you would do it similar in rcar_canfd.c with
> 
> /* CAN_CTRLMODE_FD is fixed with R-Car CAN FD */
> priv->can.ctrlmode = CAN_CTRLMODE_FD;
> 
> and remove CAN_CTRLMODE_FD from the priv->can.ctrlmode_supported
> assignment then it should do the entire configuration process correctly
> for you.
> Including the proper tests for the two bitrates.
> (see open_candev() in linux/drivers/net/can/dev.c)
> 
> Right?

I did try this option earlier but there are two problems with this method.

1) Below configuration is not possible

ip link set can0 up type can bitrate 1000000 dbitrate 1000000 fd on

"fd on" -> This is not allowed because CAN_CTRLMODE_FD bit is not set in ctrlmode_supported.

2) If I ignore "fd on", my interface MTU stays as CAN_MTU only. If I have to change the MTU alone to CANFD_MTU using another netlink message, it again checks ctrlmode_supported where it would fail. I have the option of providing my own change_mtu function & ignore this check but two configuration messages are required for my driver alone :-(.

Both these anomalies are addressed with the current check I have. 

Thanks,
Ramesh

Re: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Oliver Hartkopp]

On 03/08/2016 01:48 PM, Ramesh Shanmugasundaram wrote:

>> In fact you provided a CAN driver which is "CAN-FD-only".
> 
> Yes. That's the status of current submission.
> 
>> We did not had that before but there's a solution for this kind of setup.
>>
>> There is a similar case with CAN_CTRLMODE_FD_NON_ISO we had on the M_CAN
>> driver which only provides non-ISO configuration for the supported IP core
>> and _no_ option to _change_ this value:
>>
>> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id
>> =6cfda7fbebe8a4fd33ea5722fa0212f98f643c35
>>
>> If you would do it similar in rcar_canfd.c with
>>
>> /* CAN_CTRLMODE_FD is fixed with R-Car CAN FD */
>> priv->can.ctrlmode = CAN_CTRLMODE_FD;
>>
>> and remove CAN_CTRLMODE_FD from the priv->can.ctrlmode_supported
>> assignment then it should do the entire configuration process correctly
>> for you.
>> Including the proper tests for the two bitrates.
>> (see open_candev() in linux/drivers/net/can/dev.c)
>>
>> Right?
> 
> I did try this option earlier but there are two problems with this method.
> 
> 1) Below configuration is not possible
> 
> ip link set can0 up type can bitrate 1000000 dbitrate 1000000 fd on
> 
> "fd on" -> This is not allowed because CAN_CTRLMODE_FD bit is not set in ctrlmode_supported.
> 
> 2) If I ignore "fd on", my interface MTU stays as CAN_MTU only. If I have to change the MTU alone to CANFD_MTU using another netlink message, it again checks ctrlmode_supported where it would fail. I have the option of providing my own change_mtu function & ignore this check but two configuration messages are required for my driver alone :-(.
> 
> Both these anomalies are addressed with the current check I have. 

Oh - you are right with complaining about this inconsistency.

Can you check my RFC patch for Linux stable I just sent on the mailing list?
http://marc.info/?l=linux-can&m=145745724917976&w=2

Many thanks,
Oliver

RE: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Oliver, Marc,

> On 03/08/2016 01:48 PM, Ramesh Shanmugasundaram wrote:
> 
> >> In fact you provided a CAN driver which is "CAN-FD-only".
> >
> > Yes. That's the status of current submission.

(...)

> >
> > I did try this option earlier but there are two problems with this
> method.
> >
> > 1) Below configuration is not possible
> >
> > ip link set can0 up type can bitrate 1000000 dbitrate 1000000 fd on
> >
> > "fd on" -> This is not allowed because CAN_CTRLMODE_FD bit is not set in
> ctrlmode_supported.
> >
> > 2) If I ignore "fd on", my interface MTU stays as CAN_MTU only. If I
> have to change the MTU alone to CANFD_MTU using another netlink message,
> it again checks ctrlmode_supported where it would fail. I have the option
> of providing my own change_mtu function & ignore this check but two
> configuration messages are required for my driver alone :-(.
> >
> > Both these anomalies are addressed with the current check I have.
> 
> Oh - you are right with complaining about this inconsistency.
> 
> Can you check my RFC patch for Linux stable I just sent on the mailing
> list?
> http://marc.info/?l=linux-can&m=145745724917976&w=2

As we are fixing this issue in CAN dev.c, I'll remove this check in ndo_open and set CAN_CTRLMODE_FD flag in ctrlmode & remove the flag in ctrlmode_supported in the next v3 version of the patch.

Are there any further comments on v2 patch please?

Thanks,
Ramesh

Re: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Oliver Hartkopp]

Hi Ramesh,

On 03/11/2016 08:14 AM, Ramesh Shanmugasundaram wrote:

> As we are fixing this issue in CAN dev.c, I'll remove this check in ndo_open and set CAN_CTRLMODE_FD flag in ctrlmode & remove the flag in ctrlmode_supported in the next v3 version of the patch.

I posted a V2 version of that fix some minutes ago.
It also adds some documentation and a new variable ctrlmode_static which 
makes it clear how to specify static/fixed control modes.

Please use the new can_set_static_ctrlmode() helper as suggested in the 
changes for m_can.c.

A feedback is welcome whether this new fix fits your expectations.

> Are there any further comments on v2 patch please?

Besides the stuff I wrote above: No :-)

Best regards,
Oliver

[PATCH v3] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

This patch adds support for the CAN FD controller found in Renesas R-Car
SoCs. The controller operates in CAN FD only mode by default.

CAN FD mode supports both Classical CAN & CAN FD frame formats. The
controller supports ISO 11898-1:2015 CAN FD format only.

This controller supports two channels and the driver can enable either
or both of the channels.

Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs (one
per channel) for transmission. Rx filter rules are configured to the
minimum (one per channel) and it accepts Standard, Extended, Data &
Remote Frame combinations.

Note: There are few documentation errors in R-Car Gen3 Hardware User
Manual v0.5E with respect to CAN FD controller. They are listed below:

1. CAN FD interrupt numbers 29 & 30 are listed as per channel
interrupts. However, they are common to both channels (i.e.) they are
global and channel interrupts respectively.

2. CANFD clock is derived from PLL1. This is not documented.

3. CANFD clock is further divided by (1/2) within the CAN FD controller.
This is not documented.

4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
is specified 4 Tq in the manual.

5. The maximum number of message RAM area the controller can use is 3584
bytes. It is specified 10752 bytes in the manual.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
---
Hi All,

   Thanks for the review comments.

   This updated patch is based on linux-can-next tag (linux-can-next-for-4.6-20160310).

   This patch depends on

   [RFC] [PATCH v3] can: fix handling of unmodifiable configuration options
   (http://comments.gmane.org/gmane.linux.can/9126)

Changes since v2:
	* Rebased to latest tag (linux-can-next-for-4.6-20160310)
	* Cleaned up leftover debugfs code (Thanks Oliver H)
	* Revised devicetree documentation text (as suggested by Rob H)
	  (https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg01597.html)
	* Used new can subsystem api to set static configuration & removed check in rcar_canfd_start (as suggested by Oliver H)
	  (Refer: http://comments.gmane.org/gmane.linux.can/9126 &
	   https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg01867.html)
	* Clubbed Renesas controller drivers to driver/net/can/rcar dir (as suggested by Oliver H)
	* Updated commit message

Changes since v1:
	* Removed testmodes & debugfs code (suggested by Oliver H)
	* Fixed tx path race issue by introducing lock (suggested by Marc K)
	* Removed __maybe_unused attribute of rcar_canfd_of_table
---
 .../devicetree/bindings/net/can/rcar_canfd.txt     |   89 ++
 drivers/net/can/Kconfig                            |   11 +-
 drivers/net/can/Makefile                           |    2 +-
 drivers/net/can/rcar/Kconfig                       |   19 +
 drivers/net/can/rcar/Makefile                      |    6 +
 drivers/net/can/{ => rcar}/rcar_can.c              |    0
 drivers/net/can/rcar/rcar_canfd.c                  | 1614 ++++++++++++++++++++
 7 files changed, 1730 insertions(+), 11 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
 create mode 100644 drivers/net/can/rcar/Kconfig
 create mode 100644 drivers/net/can/rcar/Makefile
 rename drivers/net/can/{ => rcar}/rcar_can.c (100%)
 create mode 100644 drivers/net/can/rcar/rcar_canfd.c

diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
new file mode 100644
index 0000000..d45182b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
@@ -0,0 +1,89 @@
+Renesas R-Car CAN FD controller Device Tree Bindings
+----------------------------------------------------
+
+Required properties:
+- compatible: Must contain one or more of the following:
+  - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
+  - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
+
+  When compatible with the generic version, nodes must list the
+  SoC-specific version corresponding to the platform first, followed by the
+  family-specific and/or generic versions.
+
+- reg: physical base address and size of the R-Car CAN FD register map.
+- interrupts: interrupt specifier for the Global & Channel interrupts
+- clocks: phandles and clock specifiers for 3 clock inputs.
+- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
+- pinctrl-0: pin control group to be used for this controller.
+- pinctrl-names: must be "default".
+
+Required child nodes:
+The controller supports two channels and each is represented as a child node.
+The name of the child nodes are "channel0" and "channel1" respectively. Each
+child node supports the "status" property only, which is used to
+enable/disable the respective channel.
+
+Required properties for "renesas,r8a7795-canfd" compatible:
+In R8A7795 SoC, canfd clock is a div6 clock and can be used by both CAN
+and CAN FD controller at the same time. It needs to be scaled to maximum
+frequency if any of these controllers use it. This is done using the
+below properties.
+
+- assigned-clocks: phandle of canfd clock.
+- assigned-clock-rates: maximum frequency of this clock.
+
+Example
+-------
+
+SoC common .dtsi file:
+
+		canfd: can@e66c0000 {
+			compatible = "renesas,r8a7795-canfd",
+				     "renesas,rcar-gen3-canfd";
+			reg = <0 0xe66c0000 0 0x8000>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 914>,
+			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
+			       <&can_clk>;
+			clock-names = "fck", "canfd", "can_clk";
+			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
+			assigned-clock-rates = <40000000>;
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			channel0 {
+				status = "disabled";
+			};
+
+			channel1 {
+				status = "disabled";
+			};
+		};
+
+Board specific .dts file:
+
+E.g. below enables Channel 1 alone in the board.
+
+&canfd {
+        pinctrl-0 = <&canfd1_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+	channel1 {
+		status = "okay";
+	};
+};
+
+E.g. below enables Channel 0 alone in the board using External clock
+as fCAN clock.
+
+&canfd {
+        pinctrl-0 = <&canfd0_pins &can_clk_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+	channel0 {
+		status = "okay";
+	};
+};
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 0d40aef..22570ea 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -104,16 +104,6 @@ config CAN_JANZ_ICAN3
 	  This driver can also be built as a module. If so, the module will be
 	  called janz-ican3.ko.
 
-config CAN_RCAR
-	tristate "Renesas R-Car CAN controller"
-	depends on ARCH_RENESAS || ARM
-	---help---
-	  Say Y here if you want to use CAN controller found on Renesas R-Car
-	  SoCs.
-
-	  To compile this driver as a module, choose M here: the module will
-	  be called rcar_can.
-
 config CAN_SUN4I
 	tristate "Allwinner A10 CAN controller"
 	depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
@@ -152,6 +142,7 @@ source "drivers/net/can/cc770/Kconfig"
 source "drivers/net/can/ifi_canfd/Kconfig"
 source "drivers/net/can/m_can/Kconfig"
 source "drivers/net/can/mscan/Kconfig"
+source "drivers/net/can/rcar/Kconfig"
 source "drivers/net/can/sja1000/Kconfig"
 source "drivers/net/can/softing/Kconfig"
 source "drivers/net/can/spi/Kconfig"
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index e3db0c8..26ba4b7 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -10,6 +10,7 @@ can-dev-y			:= dev.o
 
 can-dev-$(CONFIG_CAN_LEDS)	+= led.o
 
+obj-y				+= rcar/
 obj-y				+= spi/
 obj-y				+= usb/
 obj-y				+= softing/
@@ -24,7 +25,6 @@ obj-$(CONFIG_CAN_IFI_CANFD)	+= ifi_canfd/
 obj-$(CONFIG_CAN_JANZ_ICAN3)	+= janz-ican3.o
 obj-$(CONFIG_CAN_MSCAN)		+= mscan/
 obj-$(CONFIG_CAN_M_CAN)		+= m_can/
-obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
 obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
 obj-$(CONFIG_CAN_SUN4I)		+= sun4i_can.o
 obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
diff --git a/drivers/net/can/rcar/Kconfig b/drivers/net/can/rcar/Kconfig
new file mode 100644
index 0000000..c41622a
--- /dev/null
+++ b/drivers/net/can/rcar/Kconfig
@@ -0,0 +1,19 @@
+config CAN_RCAR
+	tristate "Renesas R-Car CAN controller"
+	depends on ARCH_RENESAS || ARM
+	---help---
+	  Say Y here if you want to use CAN controller found on Renesas R-Car
+	  SoCs.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called rcar_can.
+
+config CAN_RCAR_CANFD
+	tristate "Renesas R-Car CAN FD controller"
+	depends on ARCH_RENESAS || ARM
+	---help---
+	  Say Y here if you want to use CAN FD controller found on
+	  Renesas R-Car SoCs.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called rcar_canfd.
diff --git a/drivers/net/can/rcar/Makefile b/drivers/net/can/rcar/Makefile
new file mode 100644
index 0000000..08de36a
--- /dev/null
+++ b/drivers/net/can/rcar/Makefile
@@ -0,0 +1,6 @@
+#
+#  Makefile for the Renesas R-Car CAN & CAN FD controller drivers
+#
+
+obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
+obj-$(CONFIG_CAN_RCAR_CANFD)	+= rcar_canfd.o
diff --git a/drivers/net/can/rcar_can.c b/drivers/net/can/rcar/rcar_can.c
similarity index 100%
rename from drivers/net/can/rcar_can.c
rename to drivers/net/can/rcar/rcar_can.c
diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
new file mode 100644
index 0000000..0b09729
--- /dev/null
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -0,0 +1,1614 @@
+/* Renesas R-Car CAN FD device driver
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/netdevice.h>
+#include <linux/platform_device.h>
+#include <linux/can/led.h>
+#include <linux/can/dev.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+
+#define RCANFD_DRV_NAME			"rcar_canfd"
+
+#define RCANFD_FIFO_DEPTH		8	/* Tx FIFO depth */
+#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
+
+#define RCANFD_NUM_CHANNELS		2
+#define RCANFD_CHANNELS_MASK		0x3	/* Two channels max */
+
+/* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
+ * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
+ * number is added to RFFIFO index.
+ */
+#define RCANFD_RFFIFO_IDX		0
+
+/* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
+ * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
+ */
+#define RCANFD_CFFIFO_IDX		0
+
+/* Global register bits */
+#define RCANFD_GINTF_CANFD		BIT(0)
+
+#define RCANFD_GCFG_TPRI		BIT(0)
+#define RCANFD_GCFG_DCE			BIT(1)
+#define RCANFD_GCFG_DCS			BIT(4)
+#define RCANFD_GCFG_CMPOC		BIT(5)
+#define RCANFD_GCFG_EEFE		BIT(6)
+
+#define RCANFD_GCTR_SLPR		BIT(2)
+#define RCANFD_GCTR_MODEMASK		(0x3)
+#define RCANFD_GCTR_GOPM		(0x0)
+#define RCANFD_GCTR_GRESET		(0x1)
+#define RCANFD_GCTR_GHLT		(0x2)
+
+#define RCANFD_GCTR_DEIE		BIT(8)
+#define RCANFD_GCTR_MEIE		BIT(9)
+#define RCANFD_GCTR_THLEIE		BIT(10)
+#define RCANFD_GCTR_CFMPOFIE		BIT(11)
+#define RCANFD_GCTR_TSRST		BIT(16)
+
+#define RCANFD_GSTS_RAMINIT		BIT(3)
+#define RCANFD_GSTS_SLP			BIT(2)
+#define RCANFD_GSTS_HLT			BIT(1)
+#define RCANFD_GSTS_RESET		BIT(0)
+
+#define RCANFD_GSTS_GNOPM		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+/* Channel register bits */
+#define RCANFD_CCTR_CSLPR		BIT(2)
+#define RCANFD_CCTR_MODEMASK		(0x3)
+#define RCANFD_CCTR_COPM		(0x0)
+#define RCANFD_CCTR_CRESET		(0x1)
+#define RCANFD_CCTR_CHLT		(0x2)
+#define RCANFD_CCTR_CTMASK		(0x3 << 25)
+#define RCANFD_CCTR_CTMS_ILB		(0x3 << 25)
+#define RCANFD_CCTR_CTME		BIT(24)
+#define RCANFD_CCTR_ERRD		BIT(23)
+#define RCANFD_CCTR_BOMMASK		(0x3 << 21)
+#define RCANFD_CCTR_BOM_ENTRY		(0x1 << 21)
+#define RCANFD_CCTR_TDCVFIE		BIT(19)
+#define RCANFD_CCTR_SOCOIE		BIT(18)
+#define RCANFD_CCTR_EOCOIE		BIT(17)
+#define RCANFD_CCTR_TAIE		BIT(16)
+#define RCANFD_CCTR_ALIE		BIT(15)
+#define RCANFD_CCTR_BLIE		BIT(14)
+#define RCANFD_CCTR_OLIE		BIT(13)
+#define RCANFD_CCTR_BORIE		BIT(12)
+#define RCANFD_CCTR_BOEIE		BIT(11)
+#define RCANFD_CCTR_EPIE		BIT(10)
+#define RCANFD_CCTR_EWIE		BIT(9)
+#define RCANFD_CCTR_BEIE		BIT(8)
+
+#define RCANFD_CSTS_COM			BIT(7)
+#define RCANFD_CSTS_REC			BIT(6)
+#define RCANFD_CSTS_TRM			BIT(5)
+#define RCANFD_CSTS_BO			BIT(4)
+#define RCANFD_CSTS_EP			BIT(3)
+#define RCANFD_CSTS_SLP			BIT(2)
+#define RCANFD_CSTS_HALT		BIT(1)
+#define RCANFD_CSTS_RESET		BIT(0)
+
+#define RCANFD_CSTS_TECCNT(x)		(((x) >> 24) & 0xff)
+#define RCANFD_CSTS_RECCNT(x)		(((x) >> 16) & 0xff)
+
+/* Bit Configuration register */
+#define RCANFD_BRP(x)			(((x) & 0x3ff) << 0)
+#define RCANFD_SJW(x)			(((x) & 0x3) << 24)
+#define RCANFD_TSEG1(x)			(((x) & 0xf) << 16)
+#define RCANFD_TSEG2(x)			(((x) & 0x7) << 20)
+
+#define RCANFD_NR_BRP(x)		(((x) & 0x3ff) << 0)
+#define RCANFD_NR_SJW(x)		(((x) & 0x1f) << 11)
+#define RCANFD_NR_TSEG1(x)		(((x) & 0x7f) << 16)
+#define RCANFD_NR_TSEG2(x)		(((x) & 0x1f) << 24)
+
+#define RCANFD_DR_BRP(x)		(((x) & 0xff) << 0)
+#define RCANFD_DR_SJW(x)		(((x) & 0x7) << 24)
+#define RCANFD_DR_TSEG1(x)		(((x) & 0xf) << 16)
+#define RCANFD_DR_TSEG2(x)		(((x) & 0x7) << 20)
+
+/* Global Error flag bits */
+#define RCANFD_GERFL_EEF1		BIT(17)
+#define RCANFD_GERFL_EEF0		BIT(16)
+#define RCANFD_GERFL_CMPOF		BIT(3)
+#define RCANFD_GERFL_THLES		BIT(2)
+#define RCANFD_GERFL_MES		BIT(1)
+#define RCANFD_GERFL_DEF		BIT(0)
+
+#define RCANFD_GERFL_ERR(x)		((x) & (RCANFD_GERFL_EEF1 |\
+						RCANFD_GERFL_EEF0 |\
+						RCANFD_GERFL_MES |\
+						RCANFD_GERFL_CMPOF))
+
+/* Channel Error flag bits */
+#define RCANFD_CERFL_ADEF		BIT(14)
+#define RCANFD_CERFL_B0EF		BIT(13)
+#define RCANFD_CERFL_B1EF		BIT(12)
+#define RCANFD_CERFL_CEF		BIT(11)
+#define RCANFD_CERFL_AEF		BIT(10)
+#define RCANFD_CERFL_FEF		BIT(9)
+#define RCANFD_CERFL_SEF		BIT(8)
+#define RCANFD_CERFL_ALEF		BIT(7)
+#define RCANFD_CERFL_BLEF		BIT(6)
+#define RCANFD_CERFL_OLEF		BIT(5)
+#define RCANFD_CERFL_BOREF		BIT(4)
+#define RCANFD_CERFL_BOEEF		BIT(3)
+#define RCANFD_CERFL_EPEF		BIT(2)
+#define RCANFD_CERFL_EWEF		BIT(1)
+#define RCANFD_CERFL_BEF		BIT(0)
+
+#define RCANFD_CERFL_ERR(x)		((x) & (0x7fff)) /* above bits 14:0 */
+
+/* CAN FD specific registers */
+#define RCANFD_DCFG_TDCE		BIT(9)
+#define RCANFD_DCFG_TDCOC		BIT(8)
+#define RCANFD_DCFG_TDCO(x)		(((x) & 0x7f) >> 16)
+
+#define RCANFD_DCSTS_TDCR(x)		(((x) >> 0) & 0x7f)
+#define RCANFD_DCSTS_SOCCNT(x)		(((x) >> 24) & 0xff)
+#define RCANFD_DCSTS_EOCCNT(x)		(((x) >> 16) & 0xff)
+
+#define RCANFD_DCSTS_TDCVF		BIT(7)
+#define RCANFD_DCSTS_EOCO		BIT(8)
+#define RCANFD_DCSTS_SOCO		BIT(9)
+
+/* Rx FIFO bits */
+#define RCANFD_RFFIFO_RFIF		BIT(3)
+#define RCANFD_RFFIFO_RFMLT		BIT(2)
+#define RCANFD_RFFIFO_RFFLL		BIT(1)
+#define RCANFD_RFFIFO_RFEMP		BIT(0)
+
+#define RCANFD_RFFIFO_RFESI		BIT(0)
+#define RCANFD_RFFIFO_RFBRS		BIT(1)
+#define RCANFD_RFFIFO_RFFDF		BIT(2)
+
+#define RCANFD_RFFIFO_RFIDE		BIT(31)
+#define RCANFD_RFFIFO_RFRTR		BIT(30)
+
+#define RCANFD_RFFIFO_RFDLC(x)		(((x) >> 28) & 0xf)
+#define RCANFD_RFFIFO_RFPTR(x)		(((x) >> 16) & 0xfff)
+#define RCANFD_RFFIFO_RFTS(x)		(((x) >> 0) & 0xff)
+
+#define RCANFD_RFFIFO_RFIM		BIT(12)
+#define RCANFD_RFFIFO_RFDC(x)		(((x) & 0x7) << 8)
+#define RCANFD_RFFIFO_RFPLS(x)		(((x) & 0x7) << 4)
+#define RCANFD_RFFIFO_RFIE		BIT(1)
+#define RCANFD_RFFIFO_RFE		BIT(0)
+
+/* Common FIFO bits */
+#define RCANFD_CMFIFO_TML(x)		(((x) & 0xf) << 20)
+#define RCANFD_CMFIFO_M(x)		(((x) & 0x3) << 16)
+#define RCANFD_CMFIFO_CFIM		BIT(12)
+#define RCANFD_CMFIFO_DC(x)		(((x) & 0x7) << 8)
+#define RCANFD_CMFIFO_PLS(x)		(((x) & 0x7) << 4)
+#define RCANFD_CMFIFO_CFTXIE		BIT(2)
+#define RCANFD_CMFIFO_CFE		BIT(0)
+
+#define RCANFD_CMFIFO_CFTXIF		BIT(4)
+#define RCANFD_CMFIFO_CFMLT		BIT(2)
+#define RCANFD_CMFIFO_CFFLL		BIT(1)
+#define RCANFD_CMFIFO_CFEMP		BIT(0)
+#define RCANFD_CMFIFO_CFMC(x)		(((x) >> 8) & 0xff)
+
+#define RCANFD_CMFIFO_CFESI		BIT(0)
+#define RCANFD_CMFIFO_CFBRS		BIT(1)
+#define RCANFD_CMFIFO_CFFDF		BIT(2)
+
+#define RCANFD_CMFIFO_CFIDE		BIT(31)
+#define RCANFD_CMFIFO_CFRTR		BIT(30)
+#define RCANFD_CMFIFO_CFID(x)		((x) & 0x1fffffff)
+
+#define RCANFD_CMFIFO_CFDLC(x)		(((x) & 0xf) << 28)
+#define RCANFD_CMFIFO_CFPTR(x)		(((x) & 0xfff) << 16)
+#define RCANFD_CMFIFO_CFTS(x)		(((x) & 0xff) << 0)
+
+/* Global Test Config register */
+#define RCANFD_GTSTCFG_C0CBCE		BIT(0)
+#define RCANFD_GTSTCFG_C1CBCE		BIT(1)
+
+#define RCANFD_GTSTCTR_ICBCTME		BIT(0)
+
+/* AFL Rx rules registers */
+#define RCANFD_AFLCFG_SETRNC0(x)	(((x) & 0xff) << 24)
+#define RCANFD_AFLCFG_SETRNC1(x)	(((x) & 0xff) << 16)
+#define RCANFD_AFLCFG_GETRNC0(x)	(((x) >> 24) & 0xff)
+#define RCANFD_AFLCFG_GETRNC1(x)	(((x) >> 16) & 0xff)
+
+#define RCANFD_AFL_PAGENUM(entry)	((entry) / 16)
+
+#define RCANFD_AFLCTR_AFLDAE		BIT(8)
+#define RCANFD_AFLCTR_AFLPN(x)		((x) & 0x1f)
+#define RCANFD_CHANNEL_NUMRULES		1	/* only one rule per channel */
+#define RCANFD_AFLID_GAFLLB		BIT(29)
+#define RCANFD_AFLPTR1_RFFIFO(x)	(1 << (x))
+
+/* Common register map offsets */
+
+/* Nominal rate registers */
+#define RCANFD_CCFG(m)			(0x0000 + (0x10 * (m)))
+#define RCANFD_CCTR(m)			(0x0004 + (0x10 * (m)))
+#define RCANFD_CSTS(m)			(0x0008 + (0x10 * (m)))
+#define RCANFD_CERFL(m)			(0x000C + (0x10 * (m)))
+
+/* Global registers */
+#define RCANFD_GCFG			(0x0084)
+#define RCANFD_GCTR			(0x0088)
+#define RCANFD_GSTS			(0x008c)
+#define RCANFD_GERFL			(0x0090)
+#define RCANFD_GTSC			(0x0094)
+#define RCANFD_GAFLECTR			(0x0098)
+#define RCANFD_GAFLCFG0			(0x009c)
+#define RCANFD_GAFLCFG1			(0x00a0)
+#define RCANFD_RMNB			(0x00a4)
+
+#define RCANFD_RMND(y)			(0x00a8 + (0x04 * (y)))
+
+/* Rx FIFO Control registers */
+#define RCANFD_RFCC(x)			(0x00b8 + (0x04 * (x)))
+#define RCANFD_RFSTS(x)			(0x00d8 + (0x04 * (x)))
+#define RCANFD_RFPCTR(x)		(0x00f8 + (0x04 * (x)))
+
+/* Common FIFO Control registers */
+#define RCANFD_CFCC(ch, idx)		(0x0118 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+#define RCANFD_CFSTS(ch, idx)		(0x0178 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+#define RCANFD_CFPCTR(ch, idx)		(0x01d8 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+
+#define RCANFD_FESTS			(0x0238)
+#define RCANFD_FFSTS			(0x023c)
+#define RCANFD_FMSTS			(0x0240)
+#define RCANFD_RFISTS			(0x0244)
+#define RCANFD_CFRISTS			(0x0248)
+#define RCANFD_CFTISTS			(0x024c)
+
+#define RCANFD_TMC(p)			(0x0250 + (0x01 * (p)))
+#define RCANFD_TMSTS(p)			(0x02d0 + (0x01 * (p)))
+
+#define RCANFD_TMTRSTS(y)		(0x0350 + (0x04 * (y)))
+#define RCANFD_TMTARSTS(y)		(0x0360 + (0x04 * (y)))
+#define RCANFD_TMTCSTS(y)		(0x0370 + (0x04 * (y)))
+#define RCANFD_TMTASTS(y)		(0x0380 + (0x04 * (y)))
+#define RCANFD_TMIEC(y)			(0x0390 + (0x04 * (y)))
+
+#define RCANFD_TXQCC(m)			(0x03a0 + (0x04 * (m)))
+#define RCANFD_TXQSTS(m)		(0x03c0 + (0x04 * (m)))
+#define RCANFD_TXQPCTR(m)		(0x03e0 + (0x04 * (m)))
+
+#define RCANFD_THLCC(m)			(0x0400 + (0x04 * (m)))
+#define RCANFD_THLSTS(m)		(0x0420 + (0x04 * (m)))
+#define RCANFD_THLPCTR(m)		(0x0440 + (0x04 * (m)))
+
+#define RCANFD_GTINTSTS0		(0x0460)
+#define RCANFD_GTINTSTS1		(0x0464)
+#define RCANFD_GTSTCFG			(0x0468)
+#define RCANFD_GTSTCTR			(0x046c)
+#define RCANFD_GLOCKK			(0x047c)
+#define RCANFD_GRMCFG			(0x04fc)
+
+/* Receive rule registers */
+#define RCANFD_GAFLID(offset, j)	((offset) + (0x10 * (j)))
+#define RCANFD_GAFLM(offset, j)		((offset) + 0x04 + (0x10 * (j)))
+#define RCANFD_GAFLP0(offset, j)	((offset) + 0x08 + (0x10 * (j)))
+#define RCANFD_GAFLP1(offset, j)	((offset) + 0x0c + (0x10 * (j)))
+
+/* CAN FD mode specific regsiter map */
+
+/* Data bitrate registers */
+#define RCANFD_F_CDFG(m)		(0x0500 + (0x20 * (m)))
+#define RCANFD_F_CFDCFG(m)		(0x0504 + (0x20 * (m)))
+#define RCANFD_F_CFDCTR(m)		(0x0508 + (0x20 * (m)))
+#define RCANFD_F_CFDSTS(m)		(0x050c + (0x20 * (m)))
+#define RCANFD_F_CFDCRC(m)		(0x0510 + (0x20 * (m)))
+
+#define RCANFD_F_GAFL_OFFSET		(0x1000)
+
+#define RCANFD_F_RMID(q)		(0x2000 + (0x10 * (q)))
+#define RCANFD_F_RMPTR(q)		(0x2004 + (0x10 * (q)))
+#define RCANFD_F_RMFDSTS(q)		(0x2008 + (0x10 * (q)))
+#define RCANFD_F_RMDF(q, b)		(0x200c + (0x04 * (b)) + (0x20 * (q)))
+
+/* Rx FIFO data registers */
+#define RCANFD_F_RFOFFSET		(0x3000)
+#define RCANFD_F_RFID(x)		(RCANFD_F_RFOFFSET + (0x80 * (x)))
+#define RCANFD_F_RFPTR(x)		(RCANFD_F_RFOFFSET + 0x04 + \
+					 (0x80 * (x)))
+#define RCANFD_F_RFFDSTS(x)		(RCANFD_F_RFOFFSET + 0x08 + \
+					 (0x80 * (x)))
+#define RCANFD_F_RFDF(x, df)		(RCANFD_F_RFOFFSET + 0x0c + \
+					 (0x80 * (x)) + (0x04 * (df)))
+
+/* Common FIFO data registers */
+#define RCANFD_F_CFOFFSET		(0x3400)
+#define RCANFD_F_CFID(ch, idx)		(RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
+					 (0x80 * (idx)))
+#define RCANFD_F_CFPTR(ch, idx)		(RCANFD_F_CFOFFSET + 0x04 + \
+					 (0x180 * (ch)) + (0x80 * (idx)))
+#define RCANFD_F_CFFDCSTS(ch, idx)	(RCANFD_F_CFOFFSET + 0x08 + \
+					 (0x180 * (ch)) + (0x80 * (idx)))
+#define RCANFD_F_CFDF(ch, idx, df)	(RCANFD_F_CFOFFSET + 0x0c + \
+					 (0x180 * (ch)) + (0x80 * (idx)) + \
+					 (0x04 * (df)))
+
+#define RCANFD_F_TMID(p)		(0x4000 + (0x20 * (p)))
+#define RCANFD_F_TMPTR(p)		(0x4004 + (0x20 * (p)))
+#define RCANFD_F_TMFDCTR(p)		(0x4008 + (0x20 * (p)))
+#define RCANFD_F_TMDF(p, b)		(0x400c + (0x20 * (p)) + (0x04 * (b)))
+
+#define RCANFD_F_THLACC(m)		(0x6000 + (0x04 * (m)))
+#define RCANFD_F_RPGACC(r)		(0x6400 + (0x04 * (r)))
+
+struct rcar_canfd_global;
+
+/* Channel priv data */
+struct rcar_canfd_channel {
+	struct can_priv can;			/* Must be the first member */
+	struct net_device *ndev;
+	struct rcar_canfd_global *gpriv;	/* Controller reference */
+	void __iomem *base;			/* Register base address */
+	struct napi_struct napi;
+	u8  tx_len[RCANFD_FIFO_DEPTH];		/* For net stats */
+	u32 tx_head;				/* Incremented on xmit */
+	u32 tx_tail;				/* Incremented on xmit done */
+	u32 channel;				/* Channel number */
+	spinlock_t tx_lock;			/* To protect tx path */
+};
+
+/* Global priv data */
+struct rcar_canfd_global {
+	struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
+	void __iomem *base;		/* Register base address */
+	struct platform_device *pdev;	/* Respective platform device */
+	struct clk *clkp;		/* Peripheral clock */
+	struct clk *can_clk;		/* fCAN clock */
+	int clock_select;		/* CANFD or Ext clock */
+	unsigned long channels_mask;	/* Enabled channels mask */
+	u32 freq;			/* fCAN clock frequency in Hz */
+};
+
+/* CAN FD mode nominal rate constants */
+static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
+	.name = RCANFD_DRV_NAME,
+	.tseg1_min = 2,
+	.tseg1_max = 128,
+	.tseg2_min = 2,
+	.tseg2_max = 32,
+	.sjw_max = 32,
+	.brp_min = 1,
+	.brp_max = 1024,
+	.brp_inc = 1,
+};
+
+/* CAN FD mode data rate constants */
+static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
+	.name = RCANFD_DRV_NAME,
+	.tseg1_min = 2,
+	.tseg1_max = 16,
+	.tseg2_min = 2,
+	.tseg2_max = 8,
+	.sjw_max = 8,
+	.brp_min = 1,
+	.brp_max = 256,
+	.brp_inc = 1,
+};
+
+/* fCAN clock select register settings */
+enum {
+	RCANFD_CANFDCLK = 0,	/* CANFD clock */
+	RCANFD_EXTCLK,		/* Externally input clock */
+};
+
+/* Helper functions */
+static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
+{
+	u32 data = readl(reg);
+
+	data &= ~mask;
+	data |= (val & mask);
+	writel(data, reg);
+}
+
+#define rcar_canfd_read(priv, offset)			\
+	readl(priv->base + (offset))
+#define rcar_canfd_write(priv, offset, val)		\
+	writel(val, priv->base + (offset))
+#define rcar_canfd_set_bit(priv, reg, val)		\
+	rcar_canfd_update(val, val, priv->base + (reg))
+#define rcar_canfd_clear_bit(priv, reg, val)		\
+	rcar_canfd_update(val, 0, priv->base + (reg))
+#define rcar_canfd_update_bit(priv, reg, mask, val)	\
+	rcar_canfd_update(mask, val, priv->base + (reg))
+
+static void rcar_canfd_get_data(struct canfd_frame *cf,
+				struct rcar_canfd_channel *priv, u32 off)
+{
+	u32 i, lwords;
+
+	lwords = cf->len / sizeof(u32);
+	if (cf->len % sizeof(u32))
+		lwords++;
+	for (i = 0; i < lwords; i++)
+		*((u32 *)cf->data + i) =
+			rcar_canfd_read(priv, off + (i * sizeof(u32)));
+}
+
+static void rcar_canfd_put_data(struct canfd_frame *cf,
+				struct rcar_canfd_channel *priv, u32 off)
+{
+	u32 i, j, lwords, leftover;
+	u32 data = 0;
+
+	lwords = cf->len / sizeof(u32);
+	leftover = cf->len % sizeof(u32);
+	for (i = 0; i < lwords; i++)
+		rcar_canfd_write(priv, off + (i * sizeof(u32)),
+				 *((u32 *)cf->data + i));
+
+	if (leftover) {
+		u8 *p = (u8 *)((u32 *)cf->data + i);
+
+		for (j = 0; j < leftover; j++)
+			data |= p[j] << (j * 8);
+		rcar_canfd_write(priv, off + (i * sizeof(u32)), data);
+	}
+}
+
+static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
+{
+	u32 i;
+
+	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
+		can_free_echo_skb(ndev, i);
+}
+
+static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
+{
+	u32 sts, ch;
+	int err;
+
+	/* Check RAMINIT flag as CAN RAM initialization takes place
+	 * after the MCU reset
+	 */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 !(sts & RCANFD_GSTS_RAMINIT), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
+		return err;
+	}
+
+	/* Transition to Global Reset mode */
+	rcar_canfd_clear_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_SLPR);
+	rcar_canfd_update_bit(gpriv, RCANFD_GCTR,
+			      RCANFD_GCTR_MODEMASK, RCANFD_GCTR_GRESET);
+
+	/* Ensure Global reset mode */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 (sts & RCANFD_GSTS_RESET), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
+		return err;
+	}
+
+	/* Reset Global error flags */
+	rcar_canfd_write(gpriv, RCANFD_GERFL, 0x0);
+
+	/* Set the controller into FD mode */
+	rcar_canfd_set_bit(gpriv, RCANFD_GRMCFG, RCANFD_GINTF_CANFD);
+
+	/* Transition all Channels to reset mode */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_clear_bit(gpriv, RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
+
+		rcar_canfd_update_bit(gpriv, RCANFD_CCTR(ch),
+				      RCANFD_CCTR_MODEMASK,
+				      RCANFD_CCTR_CRESET);
+
+		/* Ensure Channel reset mode */
+		err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
+					 (sts & RCANFD_CSTS_RESET), 2, 500000);
+		if (err) {
+			dev_dbg(&gpriv->pdev->dev,
+				"channel %u reset failed\n", ch);
+			return err;
+		}
+	}
+	return 0;
+}
+
+static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
+{
+	u32 cfg, ch;
+
+	/* Global Configuration settings */
+	cfg = RCANFD_GCFG_EEFE;		/* ECC error flag enabled */
+
+	/* Set External Clock if selected */
+	if (gpriv->clock_select != RCANFD_CANFDCLK)
+		cfg |= RCANFD_GCFG_DCS;
+
+	/* Truncate payload to configured message size RFPLS */
+	cfg |= RCANFD_GCFG_CMPOC;
+
+	rcar_canfd_set_bit(gpriv, RCANFD_GCFG, cfg);
+
+	/* Channel configuration settings */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_set_bit(gpriv, RCANFD_CCTR(ch), RCANFD_CCTR_ERRD);
+		rcar_canfd_update_bit(gpriv, RCANFD_CCTR(ch),
+				      RCANFD_CCTR_BOMMASK,
+				      RCANFD_CCTR_BOM_ENTRY);
+	}
+}
+
+static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
+					   u32 ch)
+{
+	u32 cfg;
+	int start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	if (ch == 0) {
+		start = 0; /* Start from 0th rule */
+	} else {
+		/* Get number of existing rules and adjust */
+		cfg = rcar_canfd_read(gpriv, RCANFD_GAFLCFG0);
+		start = RCANFD_AFLCFG_GETRNC0(cfg);
+	}
+
+	/* Enable write access to entry */
+	page = RCANFD_AFL_PAGENUM(start);
+	rcar_canfd_set_bit(gpriv, RCANFD_GAFLECTR,
+			   (RCANFD_AFLCTR_AFLPN(page) | RCANFD_AFLCTR_AFLDAE));
+
+	/* Write number of rules for channel */
+	if (ch == 0)
+		rcar_canfd_set_bit(gpriv, RCANFD_GAFLCFG0,
+				   RCANFD_AFLCFG_SETRNC0(num_rules));
+	else
+		rcar_canfd_set_bit(gpriv, RCANFD_GAFLCFG0,
+				   RCANFD_AFLCFG_SETRNC1(num_rules));
+
+	/* Accept all IDs */
+	rcar_canfd_write(gpriv, RCANFD_GAFLID(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* IDE or RTR is not considered for matching */
+	rcar_canfd_write(gpriv, RCANFD_GAFLM(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* Any data length accepted */
+	rcar_canfd_write(gpriv, RCANFD_GAFLP0(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* Place the msg in corresponding Rx FIFO entry */
+	rcar_canfd_write(gpriv, RCANFD_GAFLP1(RCANFD_F_GAFL_OFFSET, start),
+			 RCANFD_AFLPTR1_RFFIFO(ridx));
+
+	/* Disable write access to page */
+	rcar_canfd_clear_bit(gpriv, RCANFD_GAFLECTR, RCANFD_AFLCTR_AFLDAE);
+}
+
+static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	/* Rx FIFO is used for reception */
+	u32 cfg;
+	u16 rfdc, rfpls;
+
+	/* Select Rx FIFO based on channel */
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	rfdc = 2;		/* b010 - 8 messages Rx FIFO depth */
+	rfpls = 7;		/* b111 - Max 64 bytes payload */
+
+	cfg = (RCANFD_RFFIFO_RFIM | RCANFD_RFFIFO_RFDC(rfdc) |
+		RCANFD_RFFIFO_RFPLS(rfpls) | RCANFD_RFFIFO_RFIE);
+	rcar_canfd_write(gpriv, RCANFD_RFCC(ridx), cfg);
+}
+
+static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	/* Tx/Rx(Common) FIFO configured in Tx mode is
+	 * used for transmission
+	 *
+	 * Each channel has 3 Common FIFO dedicated to them.
+	 * Use the 1st (index 0) out of 3
+	 */
+	u32 cfg;
+	u16 cftml, cfm, cfdc, cfpls;
+
+	cftml = 0;		/* 0th buffer */
+	cfm = 1;		/* b01 - Transmit mode */
+	cfdc = 2;		/* b010 - 8 messages Tx FIFO depth */
+	cfpls = 7;		/* b111 - Max 64 bytes payload */
+
+	cfg = (RCANFD_CMFIFO_TML(cftml) | RCANFD_CMFIFO_M(cfm) |
+		RCANFD_CMFIFO_CFIM | RCANFD_CMFIFO_DC(cfdc) |
+		RCANFD_CMFIFO_PLS(cfpls) | RCANFD_CMFIFO_CFTXIE);
+	rcar_canfd_write(gpriv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
+
+	/* Clear FD mode specific control/status register */
+	rcar_canfd_write(gpriv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
+}
+
+static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
+{
+	u32 ctr;
+
+	/* Clear any stray error interrupt flags */
+	rcar_canfd_write(gpriv, RCANFD_GERFL, 0);
+
+	/* Global interrupts setup */
+	ctr = RCANFD_GCTR_MEIE;
+	ctr |= RCANFD_GCTR_CFMPOFIE;
+
+	rcar_canfd_set_bit(gpriv, RCANFD_GCTR, ctr);
+}
+
+static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
+						 *gpriv)
+{
+	/* Disable all interrupts */
+	rcar_canfd_write(gpriv, RCANFD_GCTR, 0);
+
+	/* Clear any stray error interrupt flags */
+	rcar_canfd_write(gpriv, RCANFD_GERFL, 0);
+}
+
+static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
+						 *priv)
+{
+	u32 ctr, ch = priv->channel;
+
+	/* Clear any stray error flags */
+	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
+
+	/* Channel interrupts setup */
+	ctr = (RCANFD_CCTR_TAIE |
+	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
+	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
+	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
+	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
+	rcar_canfd_set_bit(priv, RCANFD_CCTR(ch), ctr);
+}
+
+static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
+						  *priv)
+{
+	u32 ctr, ch = priv->channel;
+
+	ctr = (RCANFD_CCTR_TAIE |
+	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
+	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
+	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
+	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
+	rcar_canfd_clear_bit(priv, RCANFD_CCTR(ch), ctr);
+
+	/* Clear any stray error flags */
+	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
+}
+
+static void rcar_canfd_global_error(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 ch = priv->channel;
+	u32 gerfl, sts;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	gerfl = rcar_canfd_read(priv, RCANFD_GERFL);
+	if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
+		netdev_dbg(ndev, "Ch0: ECC Error flag\n");
+		stats->tx_dropped++;
+	}
+	if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
+		netdev_dbg(ndev, "Ch1: ECC Error flag\n");
+		stats->tx_dropped++;
+	}
+	if (gerfl & RCANFD_GERFL_MES) {
+		sts = rcar_canfd_read(priv,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		if (sts & RCANFD_CMFIFO_CFMLT) {
+			netdev_dbg(ndev, "Tx Message Lost flag\n");
+			stats->tx_dropped++;
+			rcar_canfd_write(priv,
+					 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
+					 sts & ~RCANFD_CMFIFO_CFMLT);
+		}
+
+		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
+		if (sts & RCANFD_RFFIFO_RFMLT) {
+			netdev_dbg(ndev, "Rx Message Lost flag\n");
+			stats->rx_dropped++;
+			rcar_canfd_write(priv, RCANFD_RFSTS(ridx),
+					 sts & ~RCANFD_RFFIFO_RFMLT);
+		}
+	}
+	if (gerfl & RCANFD_GERFL_CMPOF) {
+		/* Message Lost flag will be set for respective channel
+		 * when this condition happens with counters and flags
+		 * already updated.
+		 */
+		netdev_dbg(ndev, "global payload overflow interrupt\n");
+	}
+
+	/* Clear all global error interrupts. Only affected channels bits
+	 * get cleared
+	 */
+	rcar_canfd_write(priv, RCANFD_GERFL, 0);
+}
+
+static void rcar_canfd_error(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	struct can_frame *cf;
+	struct sk_buff *skb;
+	u32 cerfl, csts;
+	u32 txerr = 0, rxerr = 0;
+	u32 ch = priv->channel;
+
+	/* Propagate the error condition to the CAN stack */
+	skb = alloc_can_err_skb(ndev, &cf);
+	if (!skb) {
+		stats->rx_dropped++;
+		return;
+	}
+
+	/* Channel error interrupt */
+	cerfl = rcar_canfd_read(priv, RCANFD_CERFL(ch));
+	csts = rcar_canfd_read(priv, RCANFD_CSTS(ch));
+	txerr = RCANFD_CSTS_TECCNT(csts);
+	rxerr = RCANFD_CSTS_RECCNT(csts);
+
+	netdev_dbg(ndev, "ch erfl %x sts %x txerr %u rxerr %u\n",
+		   cerfl, csts, txerr, rxerr);
+
+	if (cerfl & RCANFD_CERFL_BEF) {
+		netdev_dbg(ndev, "Bus error\n");
+		cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
+		cf->data[2] = CAN_ERR_PROT_UNSPEC;
+		priv->can.can_stats.bus_error++;
+	}
+	if (cerfl & RCANFD_CERFL_ADEF) {
+		netdev_dbg(ndev, "ACK Delimiter Error\n");
+		stats->tx_errors++;
+		cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
+	}
+	if (cerfl & RCANFD_CERFL_B0EF) {
+		netdev_dbg(ndev, "Bit Error (dominant)\n");
+		stats->tx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_BIT0;
+	}
+	if (cerfl & RCANFD_CERFL_B1EF) {
+		netdev_dbg(ndev, "Bit Error (recessive)\n");
+		stats->tx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_BIT1;
+	}
+	if (cerfl & RCANFD_CERFL_CEF) {
+		netdev_dbg(ndev, "CRC Error\n");
+		stats->rx_errors++;
+		cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
+	}
+	if (cerfl & RCANFD_CERFL_AEF) {
+		netdev_dbg(ndev, "ACK Error\n");
+		stats->tx_errors++;
+		cf->can_id |= CAN_ERR_ACK;
+		cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
+	}
+	if (cerfl & RCANFD_CERFL_FEF) {
+		netdev_dbg(ndev, "Form Error\n");
+		stats->rx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_FORM;
+	}
+	if (cerfl & RCANFD_CERFL_SEF) {
+		netdev_dbg(ndev, "Stuff Error\n");
+		stats->rx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_STUFF;
+	}
+	if (cerfl & RCANFD_CERFL_ALEF) {
+		netdev_dbg(ndev, "Arbitration lost Error\n");
+		priv->can.can_stats.arbitration_lost++;
+		cf->can_id |= CAN_ERR_LOSTARB;
+		cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
+	}
+	if (cerfl & RCANFD_CERFL_BLEF) {
+		netdev_dbg(ndev, "Bus Lock Error\n");
+		stats->rx_errors++;
+		cf->can_id |= CAN_ERR_BUSERROR;
+	}
+	if (cerfl & RCANFD_CERFL_EWEF) {
+		netdev_dbg(ndev, "Error warning interrupt\n");
+		priv->can.state = CAN_STATE_ERROR_WARNING;
+		priv->can.can_stats.error_warning++;
+		cf->can_id |= CAN_ERR_CRTL;
+		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
+			CAN_ERR_CRTL_RX_WARNING;
+		cf->data[6] = txerr;
+		cf->data[7] = rxerr;
+	}
+	if (cerfl & RCANFD_CERFL_EPEF) {
+		netdev_dbg(ndev, "Error passive interrupt\n");
+		priv->can.state = CAN_STATE_ERROR_PASSIVE;
+		priv->can.can_stats.error_passive++;
+		cf->can_id |= CAN_ERR_CRTL;
+		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
+			CAN_ERR_CRTL_RX_PASSIVE;
+		cf->data[6] = txerr;
+		cf->data[7] = rxerr;
+	}
+	if (cerfl & RCANFD_CERFL_BOEEF) {
+		netdev_dbg(ndev, "Bus-off entry interrupt\n");
+		rcar_canfd_tx_failure_cleanup(ndev);
+		priv->can.state = CAN_STATE_BUS_OFF;
+		priv->can.can_stats.bus_off++;
+		can_bus_off(ndev);
+		cf->can_id |= CAN_ERR_BUSOFF;
+	}
+	if (cerfl & RCANFD_CERFL_OLEF) {
+		netdev_dbg(ndev,
+			   "Overload Frame Transmission error interrupt\n");
+		stats->tx_errors++;
+		cf->can_id |= CAN_ERR_PROT;
+		cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
+	}
+
+	/* Clear all channel error interrupts */
+	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
+	stats->rx_packets++;
+	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
+}
+
+static void rcar_canfd_tx_done(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 sts;
+	unsigned long flags;
+	u32 ch = priv->channel;
+
+	do {
+		u8 unsent, sent;
+
+		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
+		stats->tx_packets++;
+		stats->tx_bytes += priv->tx_len[sent];
+		priv->tx_len[sent] = 0;
+		can_get_echo_skb(ndev, sent);
+
+		spin_lock_irqsave(&priv->tx_lock, flags);
+		priv->tx_tail++;
+		sts = rcar_canfd_read(priv,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		unsent = RCANFD_CMFIFO_CFMC(sts);
+
+		/* Wake producer only when there is room */
+		if (unsent != RCANFD_FIFO_DEPTH)
+			netif_wake_queue(ndev);
+
+		if (priv->tx_head - priv->tx_tail <= unsent) {
+			spin_unlock_irqrestore(&priv->tx_lock, flags);
+			break;
+		}
+		spin_unlock_irqrestore(&priv->tx_lock, flags);
+
+	} while (1);
+
+	/* Clear interrupt */
+	rcar_canfd_write(priv, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
+			 sts & ~RCANFD_CMFIFO_CFTXIF);
+	can_led_event(ndev, CAN_LED_EVENT_TX);
+}
+
+static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
+{
+	struct rcar_canfd_global *gpriv = dev_id;
+	struct net_device *ndev;
+	struct rcar_canfd_channel *priv;
+	u32 sts, gerfl;
+	u32 ch, ridx;
+
+	/* Global error interrupts still indicate a condition specific
+	 * to a channel. RxFIFO interrupt is a global interrupt.
+	 */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		ndev = priv->ndev;
+		ridx = ch + RCANFD_RFFIFO_IDX;
+
+		/* Global error interrupts */
+		gerfl = rcar_canfd_read(priv, RCANFD_GERFL);
+		if (RCANFD_GERFL_ERR(gerfl))
+			rcar_canfd_global_error(ndev);
+
+		/* Handle Rx interrupts */
+		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
+		if (sts & RCANFD_RFFIFO_RFIF) {
+			if (napi_schedule_prep(&priv->napi)) {
+				/* Disable Rx FIFO interrupts */
+				rcar_canfd_clear_bit(priv,
+						     RCANFD_RFCC(ridx),
+						     RCANFD_RFFIFO_RFIE);
+				__napi_schedule(&priv->napi);
+			}
+		}
+	}
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
+{
+	struct rcar_canfd_global *gpriv = dev_id;
+	struct net_device *ndev;
+	struct rcar_canfd_channel *priv;
+	u32 sts, cerfl, ch;
+
+	/* Common FIFO is a per channel resource */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		ndev = priv->ndev;
+
+		/* Channel error interrupts */
+		cerfl = rcar_canfd_read(priv, RCANFD_CERFL(ch));
+		if (RCANFD_CERFL_ERR(cerfl))
+			rcar_canfd_error(ndev);
+
+		/* Handle Tx interrupts */
+		sts = rcar_canfd_read(priv,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		if (sts & RCANFD_CMFIFO_CFTXIF)
+			rcar_canfd_tx_done(ndev);
+	}
+	return IRQ_HANDLED;
+}
+
+static void rcar_canfd_set_bittiming(struct net_device *dev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(dev);
+	const struct can_bittiming *bt = &priv->can.bittiming;
+	const struct can_bittiming *dbt = &priv->can.data_bittiming;
+	u16 brp, sjw, tseg1, tseg2;
+	u32 cfg;
+	u32 ch = priv->channel;
+
+	/* Nominal bit timing settings */
+	brp = bt->brp - 1;
+	sjw = bt->sjw - 1;
+	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
+	tseg2 = bt->phase_seg2 - 1;
+
+	cfg = (RCANFD_NR_TSEG1(tseg1) | RCANFD_NR_BRP(brp) |
+	       RCANFD_NR_SJW(sjw) | RCANFD_NR_TSEG2(tseg2));
+
+	rcar_canfd_write(priv, RCANFD_CCFG(ch), cfg);
+	netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
+		   brp, sjw, tseg1, tseg2);
+
+	/* Data bit timing settings */
+	brp = dbt->brp - 1;
+	sjw = dbt->sjw - 1;
+	tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
+	tseg2 = dbt->phase_seg2 - 1;
+
+	cfg = (RCANFD_DR_TSEG1(tseg1) | RCANFD_DR_BRP(brp) |
+	       RCANFD_DR_SJW(sjw) | RCANFD_DR_TSEG2(tseg2));
+
+	rcar_canfd_write(priv, RCANFD_F_CDFG(ch), cfg);
+	netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
+		   brp, sjw, tseg1, tseg2);
+}
+
+static int rcar_canfd_start(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	int err = -EOPNOTSUPP;
+	u32 sts, ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	rcar_canfd_set_bittiming(ndev);
+
+	rcar_canfd_enable_channel_interrupts(priv);
+
+	/* Set channel to Operational mode */
+	rcar_canfd_update_bit(priv, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_COPM);
+
+	/* Verify channel mode change */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_COM), 2, 500000);
+	if (err) {
+		netdev_err(ndev, "channel %u communication state failed\n", ch);
+		goto fail_mode_change;
+	}
+
+	/* Enable Common & Rx FIFO */
+	rcar_canfd_set_bit(priv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
+			   RCANFD_CMFIFO_CFE);
+	rcar_canfd_set_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFE);
+
+	priv->can.state = CAN_STATE_ERROR_ACTIVE;
+	return 0;
+
+fail_mode_change:
+	rcar_canfd_disable_channel_interrupts(priv);
+	return err;
+}
+
+static int rcar_canfd_open(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct rcar_canfd_global *gpriv = priv->gpriv;
+	int err;
+
+	/* Peripheral clock is already enabled in probe */
+	err = clk_prepare_enable(gpriv->can_clk);
+	if (err) {
+		netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
+		goto out_clock;
+	}
+
+	err = open_candev(ndev);
+	if (err) {
+		netdev_err(ndev, "open_candev() failed, error %d\n", err);
+		goto out_can_clock;
+	}
+
+	napi_enable(&priv->napi);
+	err = rcar_canfd_start(ndev);
+	if (err)
+		goto out_close;
+	netif_start_queue(ndev);
+	can_led_event(ndev, CAN_LED_EVENT_OPEN);
+	return 0;
+out_close:
+	napi_disable(&priv->napi);
+	close_candev(ndev);
+out_can_clock:
+	clk_disable_unprepare(gpriv->can_clk);
+out_clock:
+	return err;
+}
+
+static void rcar_canfd_stop(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	int err;
+	u32 sts, ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	/* Transition to channel reset mode  */
+	rcar_canfd_update_bit(priv, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_CRESET);
+
+	/* Check Channel reset mode */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_RESET), 2, 500000);
+	if (err)
+		netdev_err(ndev, "channel %u reset failed\n", ch);
+
+	rcar_canfd_disable_channel_interrupts(priv);
+
+	/* Disable Common & Rx FIFO */
+	rcar_canfd_clear_bit(priv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
+			     RCANFD_CMFIFO_CFE);
+	rcar_canfd_clear_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFE);
+
+	/* Set the state as STOPPED */
+	priv->can.state = CAN_STATE_STOPPED;
+}
+
+static int rcar_canfd_close(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct rcar_canfd_global *gpriv = priv->gpriv;
+
+	netif_stop_queue(ndev);
+	rcar_canfd_stop(ndev);
+	napi_disable(&priv->napi);
+	clk_disable_unprepare(gpriv->can_clk);
+	close_candev(ndev);
+	can_led_event(ndev, CAN_LED_EVENT_STOP);
+	return 0;
+}
+
+static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
+					 struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
+	u32 sts, id, ptr;
+	unsigned long flags;
+	u32 ch = priv->channel;
+
+	if (can_dropped_invalid_skb(ndev, skb))
+		return NETDEV_TX_OK;
+
+	if (cf->can_id & CAN_EFF_FLAG) {
+		id = cf->can_id & CAN_EFF_MASK;
+		id |= RCANFD_CMFIFO_CFIDE;
+	} else {
+		id = cf->can_id & CAN_SFF_MASK;
+	}
+
+	if (cf->can_id & CAN_RTR_FLAG)
+		id |= RCANFD_CMFIFO_CFRTR;
+
+	rcar_canfd_write(priv, RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX),
+			 id);
+	ptr = RCANFD_CMFIFO_CFDLC(can_len2dlc(cf->len));
+	rcar_canfd_write(priv, RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX),
+			 ptr);
+
+	sts = rcar_canfd_read(priv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX));
+	if (can_is_canfd_skb(skb)) {
+		/* CAN FD frame format */
+		sts |= RCANFD_CMFIFO_CFFDF;
+		if (cf->flags & CANFD_BRS)
+			sts |= RCANFD_CMFIFO_CFBRS;
+		else
+			sts &= ~RCANFD_CMFIFO_CFBRS;
+	} else {
+		sts &= ~RCANFD_CMFIFO_CFFDF;
+	}
+	rcar_canfd_write(priv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), sts);
+
+	rcar_canfd_put_data(cf, priv,
+			    RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
+
+	priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
+	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
+
+	spin_lock_irqsave(&priv->tx_lock, flags);
+	priv->tx_head++;
+
+	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
+	 * pointer for the Common FIFO
+	 */
+	rcar_canfd_write(priv, RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
+
+	/* Stop the queue if we've filled all FIFO entries */
+	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
+		netif_stop_queue(ndev);
+
+	spin_unlock_irqrestore(&priv->tx_lock, flags);
+	return NETDEV_TX_OK;
+}
+
+static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
+{
+	struct net_device_stats *stats = &priv->ndev->stats;
+	struct canfd_frame *cf;
+	struct sk_buff *skb;
+	u32 sts = 0, id, ptr;
+	u32 ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	id = rcar_canfd_read(priv, RCANFD_F_RFID(ridx));
+	ptr = rcar_canfd_read(priv, RCANFD_F_RFPTR(ridx));
+
+	sts = rcar_canfd_read(priv, RCANFD_F_RFFDSTS(ridx));
+	if (sts & RCANFD_RFFIFO_RFFDF)
+		skb = alloc_canfd_skb(priv->ndev, &cf);
+	else
+		skb = alloc_can_skb(priv->ndev,
+				    (struct can_frame **)&cf);
+
+	if (!skb) {
+		stats->rx_dropped++;
+		return;
+	}
+
+	if (sts & RCANFD_RFFIFO_RFFDF)
+		cf->len = can_dlc2len(RCANFD_RFFIFO_RFDLC(ptr));
+	else
+		cf->len = get_can_dlc(RCANFD_RFFIFO_RFDLC(ptr));
+
+	if (sts & RCANFD_RFFIFO_RFESI) {
+		cf->flags |= CANFD_ESI;
+		netdev_dbg(priv->ndev, "ESI Error\n");
+	}
+
+	if (id & RCANFD_RFFIFO_RFIDE)
+		cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+	else
+		cf->can_id = id & CAN_SFF_MASK;
+
+	if (!(sts & RCANFD_RFFIFO_RFFDF) && (id & RCANFD_RFFIFO_RFRTR)) {
+		cf->can_id |= CAN_RTR_FLAG;
+	} else {
+		if (sts & RCANFD_RFFIFO_RFBRS)
+			cf->flags |= CANFD_BRS;
+
+		rcar_canfd_get_data(cf, priv, RCANFD_F_RFDF(ridx, 0));
+	}
+
+	/* Write 0xff to RFPC to increment the CPU-side
+	 * pointer of the Rx FIFO
+	 */
+	rcar_canfd_write(priv, RCANFD_RFPCTR(ridx), 0xff);
+
+	can_led_event(priv->ndev, CAN_LED_EVENT_RX);
+
+	stats->rx_bytes += cf->len;
+	stats->rx_packets++;
+	netif_receive_skb(skb);
+}
+
+static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
+{
+	struct rcar_canfd_channel *priv =
+		container_of(napi, struct rcar_canfd_channel, napi);
+	int num_pkts;
+	u32 sts;
+	u32 ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
+		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
+		/* Clear interrupt bit */
+		if (sts & RCANFD_RFFIFO_RFIF)
+			rcar_canfd_write(priv, RCANFD_RFSTS(ridx),
+					 sts & ~RCANFD_RFFIFO_RFIF);
+
+		/* Check FIFO empty condition */
+		if (sts & RCANFD_RFFIFO_RFEMP)
+			break;
+
+		rcar_canfd_rx_pkt(priv);
+	}
+
+	/* All packets processed */
+	if (num_pkts < quota) {
+		napi_complete(napi);
+		/* Enable Rx FIFO interrupts */
+		rcar_canfd_set_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFIE);
+	}
+	return num_pkts;
+}
+
+static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
+{
+	int err;
+
+	switch (mode) {
+	case CAN_MODE_START:
+		err = rcar_canfd_start(ndev);
+		if (err)
+			return err;
+		netif_wake_queue(ndev);
+		return 0;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int rcar_canfd_get_berr_counter(const struct net_device *dev,
+				       struct can_berr_counter *bec)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(dev);
+	u32 val, ch = priv->channel;
+
+	/* Peripheral clock is already enabled in probe */
+	val = rcar_canfd_read(priv, RCANFD_CSTS(ch));
+	bec->txerr = RCANFD_CSTS_TECCNT(val);
+	bec->rxerr = RCANFD_CSTS_RECCNT(val);
+	return 0;
+}
+
+static const struct net_device_ops rcar_canfd_netdev_ops = {
+	.ndo_open = rcar_canfd_open,
+	.ndo_stop = rcar_canfd_close,
+	.ndo_start_xmit = rcar_canfd_start_xmit,
+	.ndo_change_mtu = can_change_mtu,
+};
+
+static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	struct platform_device *pdev = gpriv->pdev;
+	struct rcar_canfd_channel *priv;
+	struct net_device *ndev;
+	int err = -ENODEV;
+
+	ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
+	if (!ndev) {
+		dev_err(&pdev->dev, "alloc_candev() failed\n");
+		err = -ENOMEM;
+		goto fail;
+	}
+	priv = netdev_priv(ndev);
+
+	ndev->netdev_ops = &rcar_canfd_netdev_ops;
+	ndev->flags |= IFF_ECHO;
+	priv->ndev = ndev;
+	priv->base = gpriv->base;
+	priv->channel = ch;
+	priv->can.clock.freq = gpriv->freq;
+	dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
+
+	priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
+	priv->can.data_bittiming_const =
+		&rcar_canfd_data_bittiming_const;
+
+	/* Controller starts in CAN FD only mode. In this mode, to interoperate
+	 * with classical CAN only nodes, data bitrate should be configured the
+	 * same as nominal bitrate.
+	 */
+	can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
+	priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
+
+	priv->can.do_set_mode = rcar_canfd_do_set_mode;
+	priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
+	priv->gpriv = gpriv;
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+
+	netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
+		       RCANFD_NAPI_WEIGHT);
+	err = register_candev(ndev);
+	if (err) {
+		dev_err(&pdev->dev,
+			"register_candev() failed, error %d\n", err);
+		goto fail_candev;
+	}
+	spin_lock_init(&priv->tx_lock);
+	devm_can_led_init(ndev);
+	gpriv->ch[priv->channel] = priv;
+	dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
+	return 0;
+
+fail_candev:
+	netif_napi_del(&priv->napi);
+	free_candev(ndev);
+fail:
+	return err;
+}
+
+static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	struct rcar_canfd_channel *priv = gpriv->ch[ch];
+
+	if (priv) {
+		unregister_candev(priv->ndev);
+		netif_napi_del(&priv->napi);
+		free_candev(priv->ndev);
+	}
+}
+
+static int rcar_canfd_probe(struct platform_device *pdev)
+{
+	struct resource *mem;
+	void __iomem *addr;
+	u32 sts, ch;
+	struct rcar_canfd_global *gpriv;
+	struct device_node *of_child;
+	unsigned long channels_mask = 0;
+	int err, ch_irq, g_irq;
+
+	of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
+	if (of_child && of_device_is_available(of_child))
+		channels_mask |= BIT(0);	/* Channel 0 */
+
+	of_child = of_get_child_by_name(pdev->dev.of_node, "channel1");
+	if (of_child && of_device_is_available(of_child))
+		channels_mask |= BIT(1);	/* Channel 1 */
+
+	ch_irq = platform_get_irq(pdev, 0);
+	if (ch_irq < 0) {
+		dev_err(&pdev->dev, "no Channel IRQ resource\n");
+		err = ch_irq;
+		goto fail_dev;
+	}
+
+	g_irq = platform_get_irq(pdev, 1);
+	if (g_irq < 0) {
+		dev_err(&pdev->dev, "no Global IRQ resource\n");
+		err = g_irq;
+		goto fail_dev;
+	}
+
+	/* Global controller context */
+	gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
+	if (!gpriv) {
+		err = -ENOMEM;
+		goto fail_dev;
+	}
+	gpriv->pdev = pdev;
+	gpriv->channels_mask = channels_mask;
+
+	/* Peripheral clock */
+	gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
+	if (IS_ERR(gpriv->clkp)) {
+		err = PTR_ERR(gpriv->clkp);
+		dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
+			err);
+		goto fail_dev;
+	}
+
+	/* fCAN clock: Pick External clock. If not available fallback to
+	 * CANFD clock
+	 */
+	gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
+	if (IS_ERR(gpriv->can_clk)) {
+		gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
+		if (IS_ERR(gpriv->can_clk)) {
+			err = PTR_ERR(gpriv->can_clk);
+			dev_err(&pdev->dev,
+				"cannot get canfd clock, error %d\n", err);
+			goto fail_dev;
+		}
+		gpriv->clock_select = RCANFD_CANFDCLK;
+
+	} else {
+		gpriv->clock_select = RCANFD_EXTCLK;
+	}
+	gpriv->freq = clk_get_rate(gpriv->can_clk);
+
+	if (gpriv->clock_select == RCANFD_CANFDCLK)
+		/* CANFD clock is further divided by (1/2) within the IP */
+		gpriv->freq /= 2;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	addr = devm_ioremap_resource(&pdev->dev, mem);
+	if (IS_ERR(addr)) {
+		err = PTR_ERR(addr);
+		goto fail_dev;
+	}
+	gpriv->base = addr;
+
+	/* Request IRQ that's common for both channels */
+	err = devm_request_irq(&pdev->dev, ch_irq,
+			       rcar_canfd_channel_interrupt, 0,
+			       "canfd.chn", gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+			ch_irq, err);
+		goto fail_dev;
+	}
+	err = devm_request_irq(&pdev->dev, g_irq,
+			       rcar_canfd_global_interrupt, 0,
+			       "canfd.gbl", gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+			g_irq, err);
+		goto fail_dev;
+	}
+
+	/* Enable peripheral clock for register access */
+	err = clk_prepare_enable(gpriv->clkp);
+	if (err) {
+		dev_err(&pdev->dev,
+			"failed to enable peripheral clock, error %d\n", err);
+		goto fail_dev;
+	}
+
+	err = rcar_canfd_reset_controller(gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "reset controller failed\n");
+		goto fail_clk;
+	}
+
+	/* Controller in Global reset & Channel reset mode */
+	rcar_canfd_configure_controller(gpriv);
+
+	/* Configure per channel attributes */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		/* Configure Channel's Rx fifo */
+		rcar_canfd_configure_rx(gpriv, ch);
+
+		/* Configure Channel's Tx (Common) fifo */
+		rcar_canfd_configure_tx(gpriv, ch);
+
+		/* Configure receive rules */
+		rcar_canfd_configure_afl_rules(gpriv, ch);
+	}
+
+	/* Configure common interrupts */
+	rcar_canfd_enable_global_interrupts(gpriv);
+
+	/* Start Global operation mode */
+	rcar_canfd_update_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_MODEMASK,
+			      RCANFD_GCTR_GOPM);
+
+	/* Verify mode change */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
+	if (err) {
+		dev_err(&pdev->dev, "global operational mode failed\n");
+		goto fail_mode;
+	}
+
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		err = rcar_canfd_channel_probe(gpriv, ch);
+		if (err)
+			goto fail_channel;
+	}
+
+	platform_set_drvdata(pdev, gpriv);
+	dev_info(&pdev->dev, "global operational state (clk %d)\n",
+		 gpriv->clock_select);
+	return 0;
+
+fail_channel:
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+		rcar_canfd_channel_remove(gpriv, ch);
+fail_mode:
+	rcar_canfd_disable_global_interrupts(gpriv);
+fail_clk:
+	clk_disable_unprepare(gpriv->clkp);
+fail_dev:
+	return err;
+}
+
+static int rcar_canfd_remove(struct platform_device *pdev)
+{
+	struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
+	struct rcar_canfd_channel *priv;
+	u32 ch;
+
+	rcar_canfd_reset_controller(gpriv);
+	rcar_canfd_disable_global_interrupts(gpriv);
+
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		if (priv) {
+			rcar_canfd_disable_channel_interrupts(priv);
+			unregister_candev(priv->ndev);
+			netif_napi_del(&priv->napi);
+			free_candev(priv->ndev);
+		}
+	}
+
+	/* Enter global sleep mode */
+	rcar_canfd_set_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_SLPR);
+	clk_disable_unprepare(gpriv->clkp);
+	return 0;
+}
+
+static int __maybe_unused rcar_canfd_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int __maybe_unused rcar_canfd_resume(struct device *dev)
+{
+	return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
+			 rcar_canfd_resume);
+
+static const struct of_device_id rcar_canfd_of_table[] = {
+	{ .compatible = "renesas,rcar-gen3-canfd" },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
+
+static struct platform_driver rcar_canfd_driver = {
+	.driver = {
+		.name = RCANFD_DRV_NAME,
+		.of_match_table = of_match_ptr(rcar_canfd_of_table),
+		.pm = &rcar_canfd_pm_ops,
+	},
+	.probe = rcar_canfd_probe,
+	.remove = rcar_canfd_remove,
+};
+
+module_platform_driver(rcar_canfd_driver);
+
+MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
+MODULE_ALIAS("platform:" RCANFD_DRV_NAME);
-- 
1.9.1

Re: [PATCH v3] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Marc Kleine-Budde]

[-- Attachment #1.1: Type: text/plain, Size: 2875 bytes --]

On 03/15/2016 10:48 AM, Ramesh Shanmugasundaram wrote:
> This patch adds support for the CAN FD controller found in Renesas R-Car
> SoCs. The controller operates in CAN FD only mode by default.
> 
> CAN FD mode supports both Classical CAN & CAN FD frame formats. The
> controller supports ISO 11898-1:2015 CAN FD format only.
> 
> This controller supports two channels and the driver can enable either
> or both of the channels.
> 
> Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs (one
> per channel) for transmission. Rx filter rules are configured to the
> minimum (one per channel) and it accepts Standard, Extended, Data &
> Remote Frame combinations.
> 
> Note: There are few documentation errors in R-Car Gen3 Hardware User
> Manual v0.5E with respect to CAN FD controller. They are listed below:
> 
> 1. CAN FD interrupt numbers 29 & 30 are listed as per channel
> interrupts. However, they are common to both channels (i.e.) they are
> global and channel interrupts respectively.
> 
> 2. CANFD clock is derived from PLL1. This is not documented.
> 
> 3. CANFD clock is further divided by (1/2) within the CAN FD controller.
> This is not documented.
> 
> 4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
> is specified 4 Tq in the manual.
> 
> 5. The maximum number of message RAM area the controller can use is 3584
> bytes. It is specified 10752 bytes in the manual.
> 
> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
> ---
> Hi All,
> 
>    Thanks for the review comments.
> 
>    This updated patch is based on linux-can-next tag (linux-can-next-for-4.6-20160310).
> 
>    This patch depends on
> 
>    [RFC] [PATCH v3] can: fix handling of unmodifiable configuration options
>    (http://comments.gmane.org/gmane.linux.can/9126)
> 
> Changes since v2:
> 	* Rebased to latest tag (linux-can-next-for-4.6-20160310)
> 	* Cleaned up leftover debugfs code (Thanks Oliver H)
> 	* Revised devicetree documentation text (as suggested by Rob H)
> 	  (https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg01597.html)
> 	* Used new can subsystem api to set static configuration & removed check in rcar_canfd_start (as suggested by Oliver H)
> 	  (Refer: http://comments.gmane.org/gmane.linux.can/9126 &
> 	   https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg01867.html)
> 	* Clubbed Renesas controller drivers to driver/net/can/rcar dir (as suggested by Oliver H)

Please make moving of the existing drivers a separate patch.

Marc
-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |


[-- Attachment #2: OpenPGP digital signature --]
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RE: [PATCH v3] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Marc,

> Subject: Re: [PATCH v3] can: rcar_canfd: Add Renesas R-Car CAN FD driver
> 
> On 03/15/2016 10:48 AM, Ramesh Shanmugasundaram wrote:
> > This patch adds support for the CAN FD controller found in Renesas
> > R-Car SoCs. The controller operates in CAN FD only mode by default.
> >
> > CAN FD mode supports both Classical CAN & CAN FD frame formats. The
> > controller supports ISO 11898-1:2015 CAN FD format only.
> >
> > This controller supports two channels and the driver can enable either
> > or both of the channels.
> >
> > Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs
> > (one per channel) for transmission. Rx filter rules are configured to
> > the minimum (one per channel) and it accepts Standard, Extended, Data
> > & Remote Frame combinations.
> >
> > Note: There are few documentation errors in R-Car Gen3 Hardware User
> > Manual v0.5E with respect to CAN FD controller. They are listed below:
> >
> > 1. CAN FD interrupt numbers 29 & 30 are listed as per channel
> > interrupts. However, they are common to both channels (i.e.) they are
> > global and channel interrupts respectively.
> >
> > 2. CANFD clock is derived from PLL1. This is not documented.
> >
> > 3. CANFD clock is further divided by (1/2) within the CAN FD controller.
> > This is not documented.
> >
> > 4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
> > is specified 4 Tq in the manual.
> >
> > 5. The maximum number of message RAM area the controller can use is
> > 3584 bytes. It is specified 10752 bytes in the manual.
> >
> > Signed-off-by: Ramesh Shanmugasundaram
> > <ramesh.shanmugasundaram@bp.renesas.com>
> > ---
> > Hi All,
> >
> >    Thanks for the review comments.
> >
> >    This updated patch is based on linux-can-next tag (linux-can-next-
> for-4.6-20160310).
> >
> >    This patch depends on
> >
> >    [RFC] [PATCH v3] can: fix handling of unmodifiable configuration
> options
> >    (http://comments.gmane.org/gmane.linux.can/9126)
> >
> > Changes since v2:
> > 	* Rebased to latest tag (linux-can-next-for-4.6-20160310)
> > 	* Cleaned up leftover debugfs code (Thanks Oliver H)
> > 	* Revised devicetree documentation text (as suggested by Rob H)
> > 	  (https://www.mail-archive.com/linux-renesas-
> soc@vger.kernel.org/msg01597.html)
> > 	* Used new can subsystem api to set static configuration & removed
> check in rcar_canfd_start (as suggested by Oliver H)
> > 	  (Refer: http://comments.gmane.org/gmane.linux.can/9126 &
> > 	   https://www.mail-archive.com/linux-renesas-
> soc@vger.kernel.org/msg01867.html)
> > 	* Clubbed Renesas controller drivers to driver/net/can/rcar dir (as
> > suggested by Oliver H)
> 
> Please make moving of the existing drivers a separate patch.

OK. I'll submit new patch with CAN FD driver in new "rcar" dir and will provide a separate patch on top that will move the CAN driver to "rcar" dir.

Thanks,
Ramesh

Re: [PATCH v3] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Rob Herring]

On Tue, Mar 15, 2016 at 09:48:14AM +0000, Ramesh Shanmugasundaram wrote:
> This patch adds support for the CAN FD controller found in Renesas R-Car
> SoCs. The controller operates in CAN FD only mode by default.
> 
> CAN FD mode supports both Classical CAN & CAN FD frame formats. The
> controller supports ISO 11898-1:2015 CAN FD format only.
> 
> This controller supports two channels and the driver can enable either
> or both of the channels.
> 
> Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs (one
> per channel) for transmission. Rx filter rules are configured to the
> minimum (one per channel) and it accepts Standard, Extended, Data &
> Remote Frame combinations.
> 
> Note: There are few documentation errors in R-Car Gen3 Hardware User
> Manual v0.5E with respect to CAN FD controller. They are listed below:
> 
> 1. CAN FD interrupt numbers 29 & 30 are listed as per channel
> interrupts. However, they are common to both channels (i.e.) they are
> global and channel interrupts respectively.
> 
> 2. CANFD clock is derived from PLL1. This is not documented.
> 
> 3. CANFD clock is further divided by (1/2) within the CAN FD controller.
> This is not documented.
> 
> 4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
> is specified 4 Tq in the manual.
> 
> 5. The maximum number of message RAM area the controller can use is 3584
> bytes. It is specified 10752 bytes in the manual.
> 
> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
> ---
> Hi All,
> 
>    Thanks for the review comments.
> 
>    This updated patch is based on linux-can-next tag (linux-can-next-for-4.6-20160310).
> 
>    This patch depends on
> 
>    [RFC] [PATCH v3] can: fix handling of unmodifiable configuration options
>    (http://comments.gmane.org/gmane.linux.can/9126)
> 
> Changes since v2:
> 	* Rebased to latest tag (linux-can-next-for-4.6-20160310)
> 	* Cleaned up leftover debugfs code (Thanks Oliver H)
> 	* Revised devicetree documentation text (as suggested by Rob H)
> 	  (https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg01597.html)
> 	* Used new can subsystem api to set static configuration & removed check in rcar_canfd_start (as suggested by Oliver H)
> 	  (Refer: http://comments.gmane.org/gmane.linux.can/9126 &
> 	   https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg01867.html)
> 	* Clubbed Renesas controller drivers to driver/net/can/rcar dir (as suggested by Oliver H)
> 	* Updated commit message
> 
> Changes since v1:
> 	* Removed testmodes & debugfs code (suggested by Oliver H)
> 	* Fixed tx path race issue by introducing lock (suggested by Marc K)
> 	* Removed __maybe_unused attribute of rcar_canfd_of_table
> ---
>  .../devicetree/bindings/net/can/rcar_canfd.txt     |   89 ++

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/net/can/Kconfig                            |   11 +-
>  drivers/net/can/Makefile                           |    2 +-
>  drivers/net/can/rcar/Kconfig                       |   19 +
>  drivers/net/can/rcar/Makefile                      |    6 +
>  drivers/net/can/{ => rcar}/rcar_can.c              |    0
>  drivers/net/can/rcar/rcar_canfd.c                  | 1614 ++++++++++++++++++++
>  7 files changed, 1730 insertions(+), 11 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
>  create mode 100644 drivers/net/can/rcar/Kconfig
>  create mode 100644 drivers/net/can/rcar/Makefile
>  rename drivers/net/can/{ => rcar}/rcar_can.c (100%)
>  create mode 100644 drivers/net/can/rcar/rcar_canfd.c

[PATCH v4 0/2] Add CAN FD driver support to r8a7795 SoC

[Ramesh Shanmugasundaram]

Hi All,

   Thanks for the review comments.

   This patch is based on linux-can-next tag (linux-can-next-for-4.6-20160310)

   This patch depends on

   [RFC] [PATCH v4] can: fix handling of unmodifiable configuration options
   (http://permalink.gmane.org/gmane.linux.can/9148)

Changes since v3:
	* Split v3 patch into two (Marc K)
	  (1) Introduce rcar_canfd.c driver in drivers/net/can/rcar dir
	  (2) Move rcar_can.c driver to new drivers/net/can/rcar dir
	* Added Acked-by Rob H for the bindings
	* Added comments on CAN FD only mode in driver & Kconfig (Oliver H)

Changes since v2:
	* Rebased to latest tag (linux-can-next-for-4.6-20160310)
	* Cleaned up leftover debugfs code (Thanks Oliver H)
	* Revised devicetree documentation text (as suggested by Rob H)
	  (https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg01597.html)
	* Used new can subsystem api to set static configuration & removed check in rcar_canfd_start (as suggested by Oliver H)
	  (Refer: http://comments.gmane.org/gmane.linux.can/9126 &
	   https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg01867.html)
	* Clubbed Renesas controller drivers to driver/net/can/rcar dir (as suggested by Oliver H)
	* Updated commit message

Changes since v1:
	* Removed testmodes & debugfs code (suggested by Oliver H)
	* Fixed tx path race issue by introducing lock (suggested by Marc K)
	* Removed __maybe_unused attribute of rcar_canfd_of_table


Ramesh Shanmugasundaram (2):
  can: rcar_canfd: Add Renesas R-Car CAN FD driver
  can: rcar_can: Move Renesas CAN driver to rcar dir

 .../devicetree/bindings/net/can/rcar_canfd.txt     |   89 ++
 drivers/net/can/Kconfig                            |   11 +-
 drivers/net/can/Makefile                           |    2 +-
 drivers/net/can/rcar/Kconfig                       |   21 +
 drivers/net/can/rcar/Makefile                      |    6 +
 drivers/net/can/{ => rcar}/rcar_can.c              |    0
 drivers/net/can/rcar/rcar_canfd.c                  | 1623 ++++++++++++++++++++
 7 files changed, 1741 insertions(+), 11 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
 create mode 100644 drivers/net/can/rcar/Kconfig
 create mode 100644 drivers/net/can/rcar/Makefile
 rename drivers/net/can/{ => rcar}/rcar_can.c (100%)
 create mode 100644 drivers/net/can/rcar/rcar_canfd.c

-- 
1.9.1

[PATCH 1/2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

This patch adds support for the CAN FD controller found in Renesas R-Car
SoCs. The controller operates in CAN FD only mode by default.

CAN FD mode supports both Classical CAN & CAN FD frame formats. The
controller supports ISO 11898-1:2015 CAN FD format only.

This controller supports two channels and the driver can enable either
or both of the channels.

Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs (one
per channel) for transmission. Rx filter rules are configured to the
minimum (one per channel) and it accepts Standard, Extended, Data &
Remote Frame combinations.

Note: There are few documentation errors in R-Car Gen3 Hardware User
Manual v0.5E with respect to CAN FD controller. They are listed below:

1. CAN FD interrupt numbers 29 & 30 are listed as per channel
interrupts. However, they are common to both channels (i.e.) they are
global and channel interrupts respectively.

2. CANFD clock is derived from PLL1. This is not documented.

3. CANFD clock is further divided by (1/2) within the CAN FD controller.
This is not documented.

4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
is specified 4 Tq in the manual.

5. The maximum number of message RAM area the controller can use is 3584
bytes. It is specified 10752 bytes in the manual.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/net/can/rcar_canfd.txt     |   89 ++
 drivers/net/can/Kconfig                            |    1 +
 drivers/net/can/Makefile                           |    1 +
 drivers/net/can/rcar/Kconfig                       |   11 +
 drivers/net/can/rcar/Makefile                      |    5 +
 drivers/net/can/rcar/rcar_canfd.c                  | 1623 ++++++++++++++++++++
 6 files changed, 1730 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
 create mode 100644 drivers/net/can/rcar/Kconfig
 create mode 100644 drivers/net/can/rcar/Makefile
 create mode 100644 drivers/net/can/rcar/rcar_canfd.c

diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
new file mode 100644
index 0000000..d45182b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
@@ -0,0 +1,89 @@
+Renesas R-Car CAN FD controller Device Tree Bindings
+----------------------------------------------------
+
+Required properties:
+- compatible: Must contain one or more of the following:
+  - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
+  - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
+
+  When compatible with the generic version, nodes must list the
+  SoC-specific version corresponding to the platform first, followed by the
+  family-specific and/or generic versions.
+
+- reg: physical base address and size of the R-Car CAN FD register map.
+- interrupts: interrupt specifier for the Global & Channel interrupts
+- clocks: phandles and clock specifiers for 3 clock inputs.
+- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
+- pinctrl-0: pin control group to be used for this controller.
+- pinctrl-names: must be "default".
+
+Required child nodes:
+The controller supports two channels and each is represented as a child node.
+The name of the child nodes are "channel0" and "channel1" respectively. Each
+child node supports the "status" property only, which is used to
+enable/disable the respective channel.
+
+Required properties for "renesas,r8a7795-canfd" compatible:
+In R8A7795 SoC, canfd clock is a div6 clock and can be used by both CAN
+and CAN FD controller at the same time. It needs to be scaled to maximum
+frequency if any of these controllers use it. This is done using the
+below properties.
+
+- assigned-clocks: phandle of canfd clock.
+- assigned-clock-rates: maximum frequency of this clock.
+
+Example
+-------
+
+SoC common .dtsi file:
+
+		canfd: can@e66c0000 {
+			compatible = "renesas,r8a7795-canfd",
+				     "renesas,rcar-gen3-canfd";
+			reg = <0 0xe66c0000 0 0x8000>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 914>,
+			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
+			       <&can_clk>;
+			clock-names = "fck", "canfd", "can_clk";
+			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
+			assigned-clock-rates = <40000000>;
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			channel0 {
+				status = "disabled";
+			};
+
+			channel1 {
+				status = "disabled";
+			};
+		};
+
+Board specific .dts file:
+
+E.g. below enables Channel 1 alone in the board.
+
+&canfd {
+        pinctrl-0 = <&canfd1_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+	channel1 {
+		status = "okay";
+	};
+};
+
+E.g. below enables Channel 0 alone in the board using External clock
+as fCAN clock.
+
+&canfd {
+        pinctrl-0 = <&canfd0_pins &can_clk_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+	channel0 {
+		status = "okay";
+	};
+};
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 0d40aef..13003a9 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -152,6 +152,7 @@ source "drivers/net/can/cc770/Kconfig"
 source "drivers/net/can/ifi_canfd/Kconfig"
 source "drivers/net/can/m_can/Kconfig"
 source "drivers/net/can/mscan/Kconfig"
+source "drivers/net/can/rcar/Kconfig"
 source "drivers/net/can/sja1000/Kconfig"
 source "drivers/net/can/softing/Kconfig"
 source "drivers/net/can/spi/Kconfig"
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index e3db0c8..226d5b5 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -10,6 +10,7 @@ can-dev-y			:= dev.o
 
 can-dev-$(CONFIG_CAN_LEDS)	+= led.o
 
+obj-y				+= rcar/
 obj-y				+= spi/
 obj-y				+= usb/
 obj-y				+= softing/
diff --git a/drivers/net/can/rcar/Kconfig b/drivers/net/can/rcar/Kconfig
new file mode 100644
index 0000000..6ea64d1
--- /dev/null
+++ b/drivers/net/can/rcar/Kconfig
@@ -0,0 +1,11 @@
+config CAN_RCAR_CANFD
+	tristate "Renesas R-Car CAN FD controller"
+	depends on ARCH_RENESAS || ARM
+	---help---
+	  Say Y here if you want to use CAN FD controller found on
+	  Renesas R-Car SoCs. The driver puts the controller in CAN FD only
+	  mode, which can interoperate with CAN2.0 nodes but does not support
+	  dedicated CAN 2.0 mode.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called rcar_canfd.
diff --git a/drivers/net/can/rcar/Makefile b/drivers/net/can/rcar/Makefile
new file mode 100644
index 0000000..cbaf498e
--- /dev/null
+++ b/drivers/net/can/rcar/Makefile
@@ -0,0 +1,5 @@
+#
+#  Makefile for the Renesas R-Car CAN FD controller driver
+#
+
+obj-$(CONFIG_CAN_RCAR_CANFD)	+= rcar_canfd.o
diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
new file mode 100644
index 0000000..62a7898
--- /dev/null
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -0,0 +1,1623 @@
+/* Renesas R-Car CAN FD device driver
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/* The R-Car CAN FD controller can operate in either one of the below two modes
+ *  - CAN FD only mode
+ *  - Classical CAN (CAN 2.0) only mode
+ *
+ * This driver puts the controller in CAN FD only mode by default. In this
+ * mode, the controller acts as a CAN FD node that can also interoperate with
+ * CAN 2.0 nodes.
+ *
+ * As of now, this driver does not support the Classical CAN (CAN 2.0) mode,
+ * which is handled by a different register map compared to CAN FD only mode.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/netdevice.h>
+#include <linux/platform_device.h>
+#include <linux/can/led.h>
+#include <linux/can/dev.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+
+#define RCANFD_DRV_NAME			"rcar_canfd"
+
+#define RCANFD_FIFO_DEPTH		8	/* Tx FIFO depth */
+#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
+
+#define RCANFD_NUM_CHANNELS		2
+#define RCANFD_CHANNELS_MASK		0x3	/* Two channels max */
+
+/* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
+ * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
+ * number is added to RFFIFO index.
+ */
+#define RCANFD_RFFIFO_IDX		0
+
+/* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
+ * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
+ */
+#define RCANFD_CFFIFO_IDX		0
+
+/* Global register bits */
+#define RCANFD_GINTF_CANFD		BIT(0)
+
+#define RCANFD_GCFG_TPRI		BIT(0)
+#define RCANFD_GCFG_DCE			BIT(1)
+#define RCANFD_GCFG_DCS			BIT(4)
+#define RCANFD_GCFG_CMPOC		BIT(5)
+#define RCANFD_GCFG_EEFE		BIT(6)
+
+#define RCANFD_GCTR_SLPR		BIT(2)
+#define RCANFD_GCTR_MODEMASK		(0x3)
+#define RCANFD_GCTR_GOPM		(0x0)
+#define RCANFD_GCTR_GRESET		(0x1)
+#define RCANFD_GCTR_GHLT		(0x2)
+
+#define RCANFD_GCTR_DEIE		BIT(8)
+#define RCANFD_GCTR_MEIE		BIT(9)
+#define RCANFD_GCTR_THLEIE		BIT(10)
+#define RCANFD_GCTR_CFMPOFIE		BIT(11)
+#define RCANFD_GCTR_TSRST		BIT(16)
+
+#define RCANFD_GSTS_RAMINIT		BIT(3)
+#define RCANFD_GSTS_SLP			BIT(2)
+#define RCANFD_GSTS_HLT			BIT(1)
+#define RCANFD_GSTS_RESET		BIT(0)
+
+#define RCANFD_GSTS_GNOPM		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+/* Channel register bits */
+#define RCANFD_CCTR_CSLPR		BIT(2)
+#define RCANFD_CCTR_MODEMASK		(0x3)
+#define RCANFD_CCTR_COPM		(0x0)
+#define RCANFD_CCTR_CRESET		(0x1)
+#define RCANFD_CCTR_CHLT		(0x2)
+#define RCANFD_CCTR_CTMASK		(0x3 << 25)
+#define RCANFD_CCTR_CTMS_ILB		(0x3 << 25)
+#define RCANFD_CCTR_CTME		BIT(24)
+#define RCANFD_CCTR_ERRD		BIT(23)
+#define RCANFD_CCTR_BOMMASK		(0x3 << 21)
+#define RCANFD_CCTR_BOM_ENTRY		(0x1 << 21)
+#define RCANFD_CCTR_TDCVFIE		BIT(19)
+#define RCANFD_CCTR_SOCOIE		BIT(18)
+#define RCANFD_CCTR_EOCOIE		BIT(17)
+#define RCANFD_CCTR_TAIE		BIT(16)
+#define RCANFD_CCTR_ALIE		BIT(15)
+#define RCANFD_CCTR_BLIE		BIT(14)
+#define RCANFD_CCTR_OLIE		BIT(13)
+#define RCANFD_CCTR_BORIE		BIT(12)
+#define RCANFD_CCTR_BOEIE		BIT(11)
+#define RCANFD_CCTR_EPIE		BIT(10)
+#define RCANFD_CCTR_EWIE		BIT(9)
+#define RCANFD_CCTR_BEIE		BIT(8)
+
+#define RCANFD_CSTS_COM			BIT(7)
+#define RCANFD_CSTS_REC			BIT(6)
+#define RCANFD_CSTS_TRM			BIT(5)
+#define RCANFD_CSTS_BO			BIT(4)
+#define RCANFD_CSTS_EP			BIT(3)
+#define RCANFD_CSTS_SLP			BIT(2)
+#define RCANFD_CSTS_HALT		BIT(1)
+#define RCANFD_CSTS_RESET		BIT(0)
+
+#define RCANFD_CSTS_TECCNT(x)		(((x) >> 24) & 0xff)
+#define RCANFD_CSTS_RECCNT(x)		(((x) >> 16) & 0xff)
+
+/* Bit Configuration register */
+#define RCANFD_BRP(x)			(((x) & 0x3ff) << 0)
+#define RCANFD_SJW(x)			(((x) & 0x3) << 24)
+#define RCANFD_TSEG1(x)			(((x) & 0xf) << 16)
+#define RCANFD_TSEG2(x)			(((x) & 0x7) << 20)
+
+#define RCANFD_NR_BRP(x)		(((x) & 0x3ff) << 0)
+#define RCANFD_NR_SJW(x)		(((x) & 0x1f) << 11)
+#define RCANFD_NR_TSEG1(x)		(((x) & 0x7f) << 16)
+#define RCANFD_NR_TSEG2(x)		(((x) & 0x1f) << 24)
+
+#define RCANFD_DR_BRP(x)		(((x) & 0xff) << 0)
+#define RCANFD_DR_SJW(x)		(((x) & 0x7) << 24)
+#define RCANFD_DR_TSEG1(x)		(((x) & 0xf) << 16)
+#define RCANFD_DR_TSEG2(x)		(((x) & 0x7) << 20)
+
+/* Global Error flag bits */
+#define RCANFD_GERFL_EEF1		BIT(17)
+#define RCANFD_GERFL_EEF0		BIT(16)
+#define RCANFD_GERFL_CMPOF		BIT(3)
+#define RCANFD_GERFL_THLES		BIT(2)
+#define RCANFD_GERFL_MES		BIT(1)
+#define RCANFD_GERFL_DEF		BIT(0)
+
+#define RCANFD_GERFL_ERR(x)		((x) & (RCANFD_GERFL_EEF1 |\
+						RCANFD_GERFL_EEF0 |\
+						RCANFD_GERFL_MES |\
+						RCANFD_GERFL_CMPOF))
+
+/* Channel Error flag bits */
+#define RCANFD_CERFL_ADEF		BIT(14)
+#define RCANFD_CERFL_B0EF		BIT(13)
+#define RCANFD_CERFL_B1EF		BIT(12)
+#define RCANFD_CERFL_CEF		BIT(11)
+#define RCANFD_CERFL_AEF		BIT(10)
+#define RCANFD_CERFL_FEF		BIT(9)
+#define RCANFD_CERFL_SEF		BIT(8)
+#define RCANFD_CERFL_ALEF		BIT(7)
+#define RCANFD_CERFL_BLEF		BIT(6)
+#define RCANFD_CERFL_OLEF		BIT(5)
+#define RCANFD_CERFL_BOREF		BIT(4)
+#define RCANFD_CERFL_BOEEF		BIT(3)
+#define RCANFD_CERFL_EPEF		BIT(2)
+#define RCANFD_CERFL_EWEF		BIT(1)
+#define RCANFD_CERFL_BEF		BIT(0)
+
+#define RCANFD_CERFL_ERR(x)		((x) & (0x7fff)) /* above bits 14:0 */
+
+/* CAN FD specific registers */
+#define RCANFD_DCFG_TDCE		BIT(9)
+#define RCANFD_DCFG_TDCOC		BIT(8)
+#define RCANFD_DCFG_TDCO(x)		(((x) & 0x7f) >> 16)
+
+#define RCANFD_DCSTS_TDCR(x)		(((x) >> 0) & 0x7f)
+#define RCANFD_DCSTS_SOCCNT(x)		(((x) >> 24) & 0xff)
+#define RCANFD_DCSTS_EOCCNT(x)		(((x) >> 16) & 0xff)
+
+#define RCANFD_DCSTS_TDCVF		BIT(7)
+#define RCANFD_DCSTS_EOCO		BIT(8)
+#define RCANFD_DCSTS_SOCO		BIT(9)
+
+/* Rx FIFO bits */
+#define RCANFD_RFFIFO_RFIF		BIT(3)
+#define RCANFD_RFFIFO_RFMLT		BIT(2)
+#define RCANFD_RFFIFO_RFFLL		BIT(1)
+#define RCANFD_RFFIFO_RFEMP		BIT(0)
+
+#define RCANFD_RFFIFO_RFESI		BIT(0)
+#define RCANFD_RFFIFO_RFBRS		BIT(1)
+#define RCANFD_RFFIFO_RFFDF		BIT(2)
+
+#define RCANFD_RFFIFO_RFIDE		BIT(31)
+#define RCANFD_RFFIFO_RFRTR		BIT(30)
+
+#define RCANFD_RFFIFO_RFDLC(x)		(((x) >> 28) & 0xf)
+#define RCANFD_RFFIFO_RFPTR(x)		(((x) >> 16) & 0xfff)
+#define RCANFD_RFFIFO_RFTS(x)		(((x) >> 0) & 0xff)
+
+#define RCANFD_RFFIFO_RFIM		BIT(12)
+#define RCANFD_RFFIFO_RFDC(x)		(((x) & 0x7) << 8)
+#define RCANFD_RFFIFO_RFPLS(x)		(((x) & 0x7) << 4)
+#define RCANFD_RFFIFO_RFIE		BIT(1)
+#define RCANFD_RFFIFO_RFE		BIT(0)
+
+/* Common FIFO bits */
+#define RCANFD_CMFIFO_TML(x)		(((x) & 0xf) << 20)
+#define RCANFD_CMFIFO_M(x)		(((x) & 0x3) << 16)
+#define RCANFD_CMFIFO_CFIM		BIT(12)
+#define RCANFD_CMFIFO_DC(x)		(((x) & 0x7) << 8)
+#define RCANFD_CMFIFO_PLS(x)		(((x) & 0x7) << 4)
+#define RCANFD_CMFIFO_CFTXIE		BIT(2)
+#define RCANFD_CMFIFO_CFE		BIT(0)
+
+#define RCANFD_CMFIFO_CFTXIF		BIT(4)
+#define RCANFD_CMFIFO_CFMLT		BIT(2)
+#define RCANFD_CMFIFO_CFFLL		BIT(1)
+#define RCANFD_CMFIFO_CFEMP		BIT(0)
+#define RCANFD_CMFIFO_CFMC(x)		(((x) >> 8) & 0xff)
+
+#define RCANFD_CMFIFO_CFESI		BIT(0)
+#define RCANFD_CMFIFO_CFBRS		BIT(1)
+#define RCANFD_CMFIFO_CFFDF		BIT(2)
+
+#define RCANFD_CMFIFO_CFIDE		BIT(31)
+#define RCANFD_CMFIFO_CFRTR		BIT(30)
+#define RCANFD_CMFIFO_CFID(x)		((x) & 0x1fffffff)
+
+#define RCANFD_CMFIFO_CFDLC(x)		(((x) & 0xf) << 28)
+#define RCANFD_CMFIFO_CFPTR(x)		(((x) & 0xfff) << 16)
+#define RCANFD_CMFIFO_CFTS(x)		(((x) & 0xff) << 0)
+
+/* Global Test Config register */
+#define RCANFD_GTSTCFG_C0CBCE		BIT(0)
+#define RCANFD_GTSTCFG_C1CBCE		BIT(1)
+
+#define RCANFD_GTSTCTR_ICBCTME		BIT(0)
+
+/* AFL Rx rules registers */
+#define RCANFD_AFLCFG_SETRNC0(x)	(((x) & 0xff) << 24)
+#define RCANFD_AFLCFG_SETRNC1(x)	(((x) & 0xff) << 16)
+#define RCANFD_AFLCFG_GETRNC0(x)	(((x) >> 24) & 0xff)
+#define RCANFD_AFLCFG_GETRNC1(x)	(((x) >> 16) & 0xff)
+
+#define RCANFD_AFL_PAGENUM(entry)	((entry) / 16)
+
+#define RCANFD_AFLCTR_AFLDAE		BIT(8)
+#define RCANFD_AFLCTR_AFLPN(x)		((x) & 0x1f)
+#define RCANFD_CHANNEL_NUMRULES		1	/* only one rule per channel */
+#define RCANFD_AFLID_GAFLLB		BIT(29)
+#define RCANFD_AFLPTR1_RFFIFO(x)	(1 << (x))
+
+/* Common register map offsets */
+
+/* Nominal rate registers */
+#define RCANFD_CCFG(m)			(0x0000 + (0x10 * (m)))
+#define RCANFD_CCTR(m)			(0x0004 + (0x10 * (m)))
+#define RCANFD_CSTS(m)			(0x0008 + (0x10 * (m)))
+#define RCANFD_CERFL(m)			(0x000C + (0x10 * (m)))
+
+/* Global registers */
+#define RCANFD_GCFG			(0x0084)
+#define RCANFD_GCTR			(0x0088)
+#define RCANFD_GSTS			(0x008c)
+#define RCANFD_GERFL			(0x0090)
+#define RCANFD_GTSC			(0x0094)
+#define RCANFD_GAFLECTR			(0x0098)
+#define RCANFD_GAFLCFG0			(0x009c)
+#define RCANFD_GAFLCFG1			(0x00a0)
+#define RCANFD_RMNB			(0x00a4)
+
+#define RCANFD_RMND(y)			(0x00a8 + (0x04 * (y)))
+
+/* Rx FIFO Control registers */
+#define RCANFD_RFCC(x)			(0x00b8 + (0x04 * (x)))
+#define RCANFD_RFSTS(x)			(0x00d8 + (0x04 * (x)))
+#define RCANFD_RFPCTR(x)		(0x00f8 + (0x04 * (x)))
+
+/* Common FIFO Control registers */
+#define RCANFD_CFCC(ch, idx)		(0x0118 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+#define RCANFD_CFSTS(ch, idx)		(0x0178 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+#define RCANFD_CFPCTR(ch, idx)		(0x01d8 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+
+#define RCANFD_FESTS			(0x0238)
+#define RCANFD_FFSTS			(0x023c)
+#define RCANFD_FMSTS			(0x0240)
+#define RCANFD_RFISTS			(0x0244)
+#define RCANFD_CFRISTS			(0x0248)
+#define RCANFD_CFTISTS			(0x024c)
+
+#define RCANFD_TMC(p)			(0x0250 + (0x01 * (p)))
+#define RCANFD_TMSTS(p)			(0x02d0 + (0x01 * (p)))
+
+#define RCANFD_TMTRSTS(y)		(0x0350 + (0x04 * (y)))
+#define RCANFD_TMTARSTS(y)		(0x0360 + (0x04 * (y)))
+#define RCANFD_TMTCSTS(y)		(0x0370 + (0x04 * (y)))
+#define RCANFD_TMTASTS(y)		(0x0380 + (0x04 * (y)))
+#define RCANFD_TMIEC(y)			(0x0390 + (0x04 * (y)))
+
+#define RCANFD_TXQCC(m)			(0x03a0 + (0x04 * (m)))
+#define RCANFD_TXQSTS(m)		(0x03c0 + (0x04 * (m)))
+#define RCANFD_TXQPCTR(m)		(0x03e0 + (0x04 * (m)))
+
+#define RCANFD_THLCC(m)			(0x0400 + (0x04 * (m)))
+#define RCANFD_THLSTS(m)		(0x0420 + (0x04 * (m)))
+#define RCANFD_THLPCTR(m)		(0x0440 + (0x04 * (m)))
+
+#define RCANFD_GTINTSTS0		(0x0460)
+#define RCANFD_GTINTSTS1		(0x0464)
+#define RCANFD_GTSTCFG			(0x0468)
+#define RCANFD_GTSTCTR			(0x046c)
+#define RCANFD_GLOCKK			(0x047c)
+#define RCANFD_GRMCFG			(0x04fc)
+
+/* Receive rule registers */
+#define RCANFD_GAFLID(offset, j)	((offset) + (0x10 * (j)))
+#define RCANFD_GAFLM(offset, j)		((offset) + 0x04 + (0x10 * (j)))
+#define RCANFD_GAFLP0(offset, j)	((offset) + 0x08 + (0x10 * (j)))
+#define RCANFD_GAFLP1(offset, j)	((offset) + 0x0c + (0x10 * (j)))
+
+/* CAN FD mode specific regsiter map */
+
+/* Data bitrate registers */
+#define RCANFD_F_CDFG(m)		(0x0500 + (0x20 * (m)))
+#define RCANFD_F_CFDCFG(m)		(0x0504 + (0x20 * (m)))
+#define RCANFD_F_CFDCTR(m)		(0x0508 + (0x20 * (m)))
+#define RCANFD_F_CFDSTS(m)		(0x050c + (0x20 * (m)))
+#define RCANFD_F_CFDCRC(m)		(0x0510 + (0x20 * (m)))
+
+#define RCANFD_F_GAFL_OFFSET		(0x1000)
+
+#define RCANFD_F_RMID(q)		(0x2000 + (0x10 * (q)))
+#define RCANFD_F_RMPTR(q)		(0x2004 + (0x10 * (q)))
+#define RCANFD_F_RMFDSTS(q)		(0x2008 + (0x10 * (q)))
+#define RCANFD_F_RMDF(q, b)		(0x200c + (0x04 * (b)) + (0x20 * (q)))
+
+/* Rx FIFO data registers */
+#define RCANFD_F_RFOFFSET		(0x3000)
+#define RCANFD_F_RFID(x)		(RCANFD_F_RFOFFSET + (0x80 * (x)))
+#define RCANFD_F_RFPTR(x)		(RCANFD_F_RFOFFSET + 0x04 + \
+					 (0x80 * (x)))
+#define RCANFD_F_RFFDSTS(x)		(RCANFD_F_RFOFFSET + 0x08 + \
+					 (0x80 * (x)))
+#define RCANFD_F_RFDF(x, df)		(RCANFD_F_RFOFFSET + 0x0c + \
+					 (0x80 * (x)) + (0x04 * (df)))
+
+/* Common FIFO data registers */
+#define RCANFD_F_CFOFFSET		(0x3400)
+#define RCANFD_F_CFID(ch, idx)		(RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
+					 (0x80 * (idx)))
+#define RCANFD_F_CFPTR(ch, idx)		(RCANFD_F_CFOFFSET + 0x04 + \
+					 (0x180 * (ch)) + (0x80 * (idx)))
+#define RCANFD_F_CFFDCSTS(ch, idx)	(RCANFD_F_CFOFFSET + 0x08 + \
+					 (0x180 * (ch)) + (0x80 * (idx)))
+#define RCANFD_F_CFDF(ch, idx, df)	(RCANFD_F_CFOFFSET + 0x0c + \
+					 (0x180 * (ch)) + (0x80 * (idx)) + \
+					 (0x04 * (df)))
+
+#define RCANFD_F_TMID(p)		(0x4000 + (0x20 * (p)))
+#define RCANFD_F_TMPTR(p)		(0x4004 + (0x20 * (p)))
+#define RCANFD_F_TMFDCTR(p)		(0x4008 + (0x20 * (p)))
+#define RCANFD_F_TMDF(p, b)		(0x400c + (0x20 * (p)) + (0x04 * (b)))
+
+#define RCANFD_F_THLACC(m)		(0x6000 + (0x04 * (m)))
+#define RCANFD_F_RPGACC(r)		(0x6400 + (0x04 * (r)))
+
+struct rcar_canfd_global;
+
+/* Channel priv data */
+struct rcar_canfd_channel {
+	struct can_priv can;			/* Must be the first member */
+	struct net_device *ndev;
+	struct rcar_canfd_global *gpriv;	/* Controller reference */
+	void __iomem *base;			/* Register base address */
+	struct napi_struct napi;
+	u8  tx_len[RCANFD_FIFO_DEPTH];		/* For net stats */
+	u32 tx_head;				/* Incremented on xmit */
+	u32 tx_tail;				/* Incremented on xmit done */
+	u32 channel;				/* Channel number */
+	spinlock_t tx_lock;			/* To protect tx path */
+};
+
+/* Global priv data */
+struct rcar_canfd_global {
+	struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
+	void __iomem *base;		/* Register base address */
+	struct platform_device *pdev;	/* Respective platform device */
+	struct clk *clkp;		/* Peripheral clock */
+	struct clk *can_clk;		/* fCAN clock */
+	int clock_select;		/* CANFD or Ext clock */
+	unsigned long channels_mask;	/* Enabled channels mask */
+	u32 freq;			/* fCAN clock frequency in Hz */
+};
+
+/* CAN FD mode nominal rate constants */
+static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
+	.name = RCANFD_DRV_NAME,
+	.tseg1_min = 2,
+	.tseg1_max = 128,
+	.tseg2_min = 2,
+	.tseg2_max = 32,
+	.sjw_max = 32,
+	.brp_min = 1,
+	.brp_max = 1024,
+	.brp_inc = 1,
+};
+
+/* CAN FD mode data rate constants */
+static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
+	.name = RCANFD_DRV_NAME,
+	.tseg1_min = 2,
+	.tseg1_max = 16,
+	.tseg2_min = 2,
+	.tseg2_max = 8,
+	.sjw_max = 8,
+	.brp_min = 1,
+	.brp_max = 256,
+	.brp_inc = 1,
+};
+
+/* fCAN clock select register settings */
+enum {
+	RCANFD_CANFDCLK = 0,	/* CANFD clock */
+	RCANFD_EXTCLK,		/* Externally input clock */
+};
+
+/* Helper functions */
+static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
+{
+	u32 data = readl(reg);
+
+	data &= ~mask;
+	data |= (val & mask);
+	writel(data, reg);
+}
+
+#define rcar_canfd_read(priv, offset)			\
+	readl(priv->base + (offset))
+#define rcar_canfd_write(priv, offset, val)		\
+	writel(val, priv->base + (offset))
+#define rcar_canfd_set_bit(priv, reg, val)		\
+	rcar_canfd_update(val, val, priv->base + (reg))
+#define rcar_canfd_clear_bit(priv, reg, val)		\
+	rcar_canfd_update(val, 0, priv->base + (reg))
+#define rcar_canfd_update_bit(priv, reg, mask, val)	\
+	rcar_canfd_update(mask, val, priv->base + (reg))
+
+static void rcar_canfd_get_data(struct canfd_frame *cf,
+				struct rcar_canfd_channel *priv, u32 off)
+{
+	u32 i, lwords;
+
+	lwords = cf->len / sizeof(u32);
+	if (cf->len % sizeof(u32))
+		lwords++;
+	for (i = 0; i < lwords; i++)
+		*((u32 *)cf->data + i) =
+			rcar_canfd_read(priv, off + (i * sizeof(u32)));
+}
+
+static void rcar_canfd_put_data(struct canfd_frame *cf,
+				struct rcar_canfd_channel *priv, u32 off)
+{
+	u32 i, j, lwords, leftover;
+	u32 data = 0;
+
+	lwords = cf->len / sizeof(u32);
+	leftover = cf->len % sizeof(u32);
+	for (i = 0; i < lwords; i++)
+		rcar_canfd_write(priv, off + (i * sizeof(u32)),
+				 *((u32 *)cf->data + i));
+
+	if (leftover) {
+		u8 *p = (u8 *)((u32 *)cf->data + i);
+
+		for (j = 0; j < leftover; j++)
+			data |= p[j] << (j * 8);
+		rcar_canfd_write(priv, off + (i * sizeof(u32)), data);
+	}
+}
+
+static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
+{
+	u32 i;
+
+	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
+		can_free_echo_skb(ndev, i);
+}
+
+static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
+{
+	u32 sts, ch;
+	int err;
+
+	/* Check RAMINIT flag as CAN RAM initialization takes place
+	 * after the MCU reset
+	 */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 !(sts & RCANFD_GSTS_RAMINIT), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
+		return err;
+	}
+
+	/* Transition to Global Reset mode */
+	rcar_canfd_clear_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_SLPR);
+	rcar_canfd_update_bit(gpriv, RCANFD_GCTR,
+			      RCANFD_GCTR_MODEMASK, RCANFD_GCTR_GRESET);
+
+	/* Ensure Global reset mode */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 (sts & RCANFD_GSTS_RESET), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
+		return err;
+	}
+
+	/* Reset Global error flags */
+	rcar_canfd_write(gpriv, RCANFD_GERFL, 0x0);
+
+	/* Set the controller into FD mode */
+	rcar_canfd_set_bit(gpriv, RCANFD_GRMCFG, RCANFD_GINTF_CANFD);
+
+	/* Transition all Channels to reset mode */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_clear_bit(gpriv, RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
+
+		rcar_canfd_update_bit(gpriv, RCANFD_CCTR(ch),
+				      RCANFD_CCTR_MODEMASK,
+				      RCANFD_CCTR_CRESET);
+
+		/* Ensure Channel reset mode */
+		err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
+					 (sts & RCANFD_CSTS_RESET), 2, 500000);
+		if (err) {
+			dev_dbg(&gpriv->pdev->dev,
+				"channel %u reset failed\n", ch);
+			return err;
+		}
+	}
+	return 0;
+}
+
+static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
+{
+	u32 cfg, ch;
+
+	/* Global Configuration settings */
+	cfg = RCANFD_GCFG_EEFE;		/* ECC error flag enabled */
+
+	/* Set External Clock if selected */
+	if (gpriv->clock_select != RCANFD_CANFDCLK)
+		cfg |= RCANFD_GCFG_DCS;
+
+	/* Truncate payload to configured message size RFPLS */
+	cfg |= RCANFD_GCFG_CMPOC;
+
+	rcar_canfd_set_bit(gpriv, RCANFD_GCFG, cfg);
+
+	/* Channel configuration settings */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_set_bit(gpriv, RCANFD_CCTR(ch), RCANFD_CCTR_ERRD);
+		rcar_canfd_update_bit(gpriv, RCANFD_CCTR(ch),
+				      RCANFD_CCTR_BOMMASK,
+				      RCANFD_CCTR_BOM_ENTRY);
+	}
+}
+
+static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
+					   u32 ch)
+{
+	u32 cfg;
+	int start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	if (ch == 0) {
+		start = 0; /* Start from 0th rule */
+	} else {
+		/* Get number of existing rules and adjust */
+		cfg = rcar_canfd_read(gpriv, RCANFD_GAFLCFG0);
+		start = RCANFD_AFLCFG_GETRNC0(cfg);
+	}
+
+	/* Enable write access to entry */
+	page = RCANFD_AFL_PAGENUM(start);
+	rcar_canfd_set_bit(gpriv, RCANFD_GAFLECTR,
+			   (RCANFD_AFLCTR_AFLPN(page) | RCANFD_AFLCTR_AFLDAE));
+
+	/* Write number of rules for channel */
+	if (ch == 0)
+		rcar_canfd_set_bit(gpriv, RCANFD_GAFLCFG0,
+				   RCANFD_AFLCFG_SETRNC0(num_rules));
+	else
+		rcar_canfd_set_bit(gpriv, RCANFD_GAFLCFG0,
+				   RCANFD_AFLCFG_SETRNC1(num_rules));
+
+	/* Accept all IDs */
+	rcar_canfd_write(gpriv, RCANFD_GAFLID(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* IDE or RTR is not considered for matching */
+	rcar_canfd_write(gpriv, RCANFD_GAFLM(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* Any data length accepted */
+	rcar_canfd_write(gpriv, RCANFD_GAFLP0(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* Place the msg in corresponding Rx FIFO entry */
+	rcar_canfd_write(gpriv, RCANFD_GAFLP1(RCANFD_F_GAFL_OFFSET, start),
+			 RCANFD_AFLPTR1_RFFIFO(ridx));
+
+	/* Disable write access to page */
+	rcar_canfd_clear_bit(gpriv, RCANFD_GAFLECTR, RCANFD_AFLCTR_AFLDAE);
+}
+
+static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	/* Rx FIFO is used for reception */
+	u32 cfg;
+	u16 rfdc, rfpls;
+
+	/* Select Rx FIFO based on channel */
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	rfdc = 2;		/* b010 - 8 messages Rx FIFO depth */
+	rfpls = 7;		/* b111 - Max 64 bytes payload */
+
+	cfg = (RCANFD_RFFIFO_RFIM | RCANFD_RFFIFO_RFDC(rfdc) |
+		RCANFD_RFFIFO_RFPLS(rfpls) | RCANFD_RFFIFO_RFIE);
+	rcar_canfd_write(gpriv, RCANFD_RFCC(ridx), cfg);
+}
+
+static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	/* Tx/Rx(Common) FIFO configured in Tx mode is
+	 * used for transmission
+	 *
+	 * Each channel has 3 Common FIFO dedicated to them.
+	 * Use the 1st (index 0) out of 3
+	 */
+	u32 cfg;
+	u16 cftml, cfm, cfdc, cfpls;
+
+	cftml = 0;		/* 0th buffer */
+	cfm = 1;		/* b01 - Transmit mode */
+	cfdc = 2;		/* b010 - 8 messages Tx FIFO depth */
+	cfpls = 7;		/* b111 - Max 64 bytes payload */
+
+	cfg = (RCANFD_CMFIFO_TML(cftml) | RCANFD_CMFIFO_M(cfm) |
+		RCANFD_CMFIFO_CFIM | RCANFD_CMFIFO_DC(cfdc) |
+		RCANFD_CMFIFO_PLS(cfpls) | RCANFD_CMFIFO_CFTXIE);
+	rcar_canfd_write(gpriv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
+
+	/* Clear FD mode specific control/status register */
+	rcar_canfd_write(gpriv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
+}
+
+static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
+{
+	u32 ctr;
+
+	/* Clear any stray error interrupt flags */
+	rcar_canfd_write(gpriv, RCANFD_GERFL, 0);
+
+	/* Global interrupts setup */
+	ctr = RCANFD_GCTR_MEIE;
+	ctr |= RCANFD_GCTR_CFMPOFIE;
+
+	rcar_canfd_set_bit(gpriv, RCANFD_GCTR, ctr);
+}
+
+static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
+						 *gpriv)
+{
+	/* Disable all interrupts */
+	rcar_canfd_write(gpriv, RCANFD_GCTR, 0);
+
+	/* Clear any stray error interrupt flags */
+	rcar_canfd_write(gpriv, RCANFD_GERFL, 0);
+}
+
+static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
+						 *priv)
+{
+	u32 ctr, ch = priv->channel;
+
+	/* Clear any stray error flags */
+	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
+
+	/* Channel interrupts setup */
+	ctr = (RCANFD_CCTR_TAIE |
+	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
+	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
+	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
+	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
+	rcar_canfd_set_bit(priv, RCANFD_CCTR(ch), ctr);
+}
+
+static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
+						  *priv)
+{
+	u32 ctr, ch = priv->channel;
+
+	ctr = (RCANFD_CCTR_TAIE |
+	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
+	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
+	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
+	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
+	rcar_canfd_clear_bit(priv, RCANFD_CCTR(ch), ctr);
+
+	/* Clear any stray error flags */
+	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
+}
+
+static void rcar_canfd_global_error(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 ch = priv->channel;
+	u32 gerfl, sts;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	gerfl = rcar_canfd_read(priv, RCANFD_GERFL);
+	if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
+		netdev_dbg(ndev, "Ch0: ECC Error flag\n");
+		stats->tx_dropped++;
+	}
+	if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
+		netdev_dbg(ndev, "Ch1: ECC Error flag\n");
+		stats->tx_dropped++;
+	}
+	if (gerfl & RCANFD_GERFL_MES) {
+		sts = rcar_canfd_read(priv,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		if (sts & RCANFD_CMFIFO_CFMLT) {
+			netdev_dbg(ndev, "Tx Message Lost flag\n");
+			stats->tx_dropped++;
+			rcar_canfd_write(priv,
+					 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
+					 sts & ~RCANFD_CMFIFO_CFMLT);
+		}
+
+		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
+		if (sts & RCANFD_RFFIFO_RFMLT) {
+			netdev_dbg(ndev, "Rx Message Lost flag\n");
+			stats->rx_dropped++;
+			rcar_canfd_write(priv, RCANFD_RFSTS(ridx),
+					 sts & ~RCANFD_RFFIFO_RFMLT);
+		}
+	}
+	if (gerfl & RCANFD_GERFL_CMPOF) {
+		/* Message Lost flag will be set for respective channel
+		 * when this condition happens with counters and flags
+		 * already updated.
+		 */
+		netdev_dbg(ndev, "global payload overflow interrupt\n");
+	}
+
+	/* Clear all global error interrupts. Only affected channels bits
+	 * get cleared
+	 */
+	rcar_canfd_write(priv, RCANFD_GERFL, 0);
+}
+
+static void rcar_canfd_error(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	struct can_frame *cf;
+	struct sk_buff *skb;
+	u32 cerfl, csts;
+	u32 txerr = 0, rxerr = 0;
+	u32 ch = priv->channel;
+
+	/* Propagate the error condition to the CAN stack */
+	skb = alloc_can_err_skb(ndev, &cf);
+	if (!skb) {
+		stats->rx_dropped++;
+		return;
+	}
+
+	/* Channel error interrupt */
+	cerfl = rcar_canfd_read(priv, RCANFD_CERFL(ch));
+	csts = rcar_canfd_read(priv, RCANFD_CSTS(ch));
+	txerr = RCANFD_CSTS_TECCNT(csts);
+	rxerr = RCANFD_CSTS_RECCNT(csts);
+
+	netdev_dbg(ndev, "ch erfl %x sts %x txerr %u rxerr %u\n",
+		   cerfl, csts, txerr, rxerr);
+
+	if (cerfl & RCANFD_CERFL_BEF) {
+		netdev_dbg(ndev, "Bus error\n");
+		cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
+		cf->data[2] = CAN_ERR_PROT_UNSPEC;
+		priv->can.can_stats.bus_error++;
+	}
+	if (cerfl & RCANFD_CERFL_ADEF) {
+		netdev_dbg(ndev, "ACK Delimiter Error\n");
+		stats->tx_errors++;
+		cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
+	}
+	if (cerfl & RCANFD_CERFL_B0EF) {
+		netdev_dbg(ndev, "Bit Error (dominant)\n");
+		stats->tx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_BIT0;
+	}
+	if (cerfl & RCANFD_CERFL_B1EF) {
+		netdev_dbg(ndev, "Bit Error (recessive)\n");
+		stats->tx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_BIT1;
+	}
+	if (cerfl & RCANFD_CERFL_CEF) {
+		netdev_dbg(ndev, "CRC Error\n");
+		stats->rx_errors++;
+		cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
+	}
+	if (cerfl & RCANFD_CERFL_AEF) {
+		netdev_dbg(ndev, "ACK Error\n");
+		stats->tx_errors++;
+		cf->can_id |= CAN_ERR_ACK;
+		cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
+	}
+	if (cerfl & RCANFD_CERFL_FEF) {
+		netdev_dbg(ndev, "Form Error\n");
+		stats->rx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_FORM;
+	}
+	if (cerfl & RCANFD_CERFL_SEF) {
+		netdev_dbg(ndev, "Stuff Error\n");
+		stats->rx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_STUFF;
+	}
+	if (cerfl & RCANFD_CERFL_ALEF) {
+		netdev_dbg(ndev, "Arbitration lost Error\n");
+		priv->can.can_stats.arbitration_lost++;
+		cf->can_id |= CAN_ERR_LOSTARB;
+		cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
+	}
+	if (cerfl & RCANFD_CERFL_BLEF) {
+		netdev_dbg(ndev, "Bus Lock Error\n");
+		stats->rx_errors++;
+		cf->can_id |= CAN_ERR_BUSERROR;
+	}
+	if (cerfl & RCANFD_CERFL_EWEF) {
+		netdev_dbg(ndev, "Error warning interrupt\n");
+		priv->can.state = CAN_STATE_ERROR_WARNING;
+		priv->can.can_stats.error_warning++;
+		cf->can_id |= CAN_ERR_CRTL;
+		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
+			CAN_ERR_CRTL_RX_WARNING;
+		cf->data[6] = txerr;
+		cf->data[7] = rxerr;
+	}
+	if (cerfl & RCANFD_CERFL_EPEF) {
+		netdev_dbg(ndev, "Error passive interrupt\n");
+		priv->can.state = CAN_STATE_ERROR_PASSIVE;
+		priv->can.can_stats.error_passive++;
+		cf->can_id |= CAN_ERR_CRTL;
+		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
+			CAN_ERR_CRTL_RX_PASSIVE;
+		cf->data[6] = txerr;
+		cf->data[7] = rxerr;
+	}
+	if (cerfl & RCANFD_CERFL_BOEEF) {
+		netdev_dbg(ndev, "Bus-off entry interrupt\n");
+		rcar_canfd_tx_failure_cleanup(ndev);
+		priv->can.state = CAN_STATE_BUS_OFF;
+		priv->can.can_stats.bus_off++;
+		can_bus_off(ndev);
+		cf->can_id |= CAN_ERR_BUSOFF;
+	}
+	if (cerfl & RCANFD_CERFL_OLEF) {
+		netdev_dbg(ndev,
+			   "Overload Frame Transmission error interrupt\n");
+		stats->tx_errors++;
+		cf->can_id |= CAN_ERR_PROT;
+		cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
+	}
+
+	/* Clear all channel error interrupts */
+	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
+	stats->rx_packets++;
+	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
+}
+
+static void rcar_canfd_tx_done(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 sts;
+	unsigned long flags;
+	u32 ch = priv->channel;
+
+	do {
+		u8 unsent, sent;
+
+		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
+		stats->tx_packets++;
+		stats->tx_bytes += priv->tx_len[sent];
+		priv->tx_len[sent] = 0;
+		can_get_echo_skb(ndev, sent);
+
+		spin_lock_irqsave(&priv->tx_lock, flags);
+		priv->tx_tail++;
+		sts = rcar_canfd_read(priv,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		unsent = RCANFD_CMFIFO_CFMC(sts);
+
+		/* Wake producer only when there is room */
+		if (unsent != RCANFD_FIFO_DEPTH)
+			netif_wake_queue(ndev);
+
+		if (priv->tx_head - priv->tx_tail <= unsent) {
+			spin_unlock_irqrestore(&priv->tx_lock, flags);
+			break;
+		}
+		spin_unlock_irqrestore(&priv->tx_lock, flags);
+
+	} while (1);
+
+	/* Clear interrupt */
+	rcar_canfd_write(priv, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
+			 sts & ~RCANFD_CMFIFO_CFTXIF);
+	can_led_event(ndev, CAN_LED_EVENT_TX);
+}
+
+static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
+{
+	struct rcar_canfd_global *gpriv = dev_id;
+	struct net_device *ndev;
+	struct rcar_canfd_channel *priv;
+	u32 sts, gerfl;
+	u32 ch, ridx;
+
+	/* Global error interrupts still indicate a condition specific
+	 * to a channel. RxFIFO interrupt is a global interrupt.
+	 */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		ndev = priv->ndev;
+		ridx = ch + RCANFD_RFFIFO_IDX;
+
+		/* Global error interrupts */
+		gerfl = rcar_canfd_read(priv, RCANFD_GERFL);
+		if (RCANFD_GERFL_ERR(gerfl))
+			rcar_canfd_global_error(ndev);
+
+		/* Handle Rx interrupts */
+		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
+		if (sts & RCANFD_RFFIFO_RFIF) {
+			if (napi_schedule_prep(&priv->napi)) {
+				/* Disable Rx FIFO interrupts */
+				rcar_canfd_clear_bit(priv,
+						     RCANFD_RFCC(ridx),
+						     RCANFD_RFFIFO_RFIE);
+				__napi_schedule(&priv->napi);
+			}
+		}
+	}
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
+{
+	struct rcar_canfd_global *gpriv = dev_id;
+	struct net_device *ndev;
+	struct rcar_canfd_channel *priv;
+	u32 sts, cerfl, ch;
+
+	/* Common FIFO is a per channel resource */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		ndev = priv->ndev;
+
+		/* Channel error interrupts */
+		cerfl = rcar_canfd_read(priv, RCANFD_CERFL(ch));
+		if (RCANFD_CERFL_ERR(cerfl))
+			rcar_canfd_error(ndev);
+
+		/* Handle Tx interrupts */
+		sts = rcar_canfd_read(priv,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		if (sts & RCANFD_CMFIFO_CFTXIF)
+			rcar_canfd_tx_done(ndev);
+	}
+	return IRQ_HANDLED;
+}
+
+static void rcar_canfd_set_bittiming(struct net_device *dev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(dev);
+	const struct can_bittiming *bt = &priv->can.bittiming;
+	const struct can_bittiming *dbt = &priv->can.data_bittiming;
+	u16 brp, sjw, tseg1, tseg2;
+	u32 cfg;
+	u32 ch = priv->channel;
+
+	/* Nominal bit timing settings */
+	brp = bt->brp - 1;
+	sjw = bt->sjw - 1;
+	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
+	tseg2 = bt->phase_seg2 - 1;
+
+	cfg = (RCANFD_NR_TSEG1(tseg1) | RCANFD_NR_BRP(brp) |
+	       RCANFD_NR_SJW(sjw) | RCANFD_NR_TSEG2(tseg2));
+
+	rcar_canfd_write(priv, RCANFD_CCFG(ch), cfg);
+	netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
+		   brp, sjw, tseg1, tseg2);
+
+	/* Data bit timing settings */
+	brp = dbt->brp - 1;
+	sjw = dbt->sjw - 1;
+	tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
+	tseg2 = dbt->phase_seg2 - 1;
+
+	cfg = (RCANFD_DR_TSEG1(tseg1) | RCANFD_DR_BRP(brp) |
+	       RCANFD_DR_SJW(sjw) | RCANFD_DR_TSEG2(tseg2));
+
+	rcar_canfd_write(priv, RCANFD_F_CDFG(ch), cfg);
+	netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
+		   brp, sjw, tseg1, tseg2);
+}
+
+static int rcar_canfd_start(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	int err = -EOPNOTSUPP;
+	u32 sts, ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	rcar_canfd_set_bittiming(ndev);
+
+	rcar_canfd_enable_channel_interrupts(priv);
+
+	/* Set channel to Operational mode */
+	rcar_canfd_update_bit(priv, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_COPM);
+
+	/* Verify channel mode change */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_COM), 2, 500000);
+	if (err) {
+		netdev_err(ndev, "channel %u communication state failed\n", ch);
+		goto fail_mode_change;
+	}
+
+	/* Enable Common & Rx FIFO */
+	rcar_canfd_set_bit(priv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
+			   RCANFD_CMFIFO_CFE);
+	rcar_canfd_set_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFE);
+
+	priv->can.state = CAN_STATE_ERROR_ACTIVE;
+	return 0;
+
+fail_mode_change:
+	rcar_canfd_disable_channel_interrupts(priv);
+	return err;
+}
+
+static int rcar_canfd_open(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct rcar_canfd_global *gpriv = priv->gpriv;
+	int err;
+
+	/* Peripheral clock is already enabled in probe */
+	err = clk_prepare_enable(gpriv->can_clk);
+	if (err) {
+		netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
+		goto out_clock;
+	}
+
+	err = open_candev(ndev);
+	if (err) {
+		netdev_err(ndev, "open_candev() failed, error %d\n", err);
+		goto out_can_clock;
+	}
+
+	napi_enable(&priv->napi);
+	err = rcar_canfd_start(ndev);
+	if (err)
+		goto out_close;
+	netif_start_queue(ndev);
+	can_led_event(ndev, CAN_LED_EVENT_OPEN);
+	return 0;
+out_close:
+	napi_disable(&priv->napi);
+	close_candev(ndev);
+out_can_clock:
+	clk_disable_unprepare(gpriv->can_clk);
+out_clock:
+	return err;
+}
+
+static void rcar_canfd_stop(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	int err;
+	u32 sts, ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	/* Transition to channel reset mode  */
+	rcar_canfd_update_bit(priv, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_CRESET);
+
+	/* Check Channel reset mode */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_RESET), 2, 500000);
+	if (err)
+		netdev_err(ndev, "channel %u reset failed\n", ch);
+
+	rcar_canfd_disable_channel_interrupts(priv);
+
+	/* Disable Common & Rx FIFO */
+	rcar_canfd_clear_bit(priv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
+			     RCANFD_CMFIFO_CFE);
+	rcar_canfd_clear_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFE);
+
+	/* Set the state as STOPPED */
+	priv->can.state = CAN_STATE_STOPPED;
+}
+
+static int rcar_canfd_close(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct rcar_canfd_global *gpriv = priv->gpriv;
+
+	netif_stop_queue(ndev);
+	rcar_canfd_stop(ndev);
+	napi_disable(&priv->napi);
+	clk_disable_unprepare(gpriv->can_clk);
+	close_candev(ndev);
+	can_led_event(ndev, CAN_LED_EVENT_STOP);
+	return 0;
+}
+
+static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
+					 struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
+	u32 sts, id, ptr;
+	unsigned long flags;
+	u32 ch = priv->channel;
+
+	if (can_dropped_invalid_skb(ndev, skb))
+		return NETDEV_TX_OK;
+
+	if (cf->can_id & CAN_EFF_FLAG) {
+		id = cf->can_id & CAN_EFF_MASK;
+		id |= RCANFD_CMFIFO_CFIDE;
+	} else {
+		id = cf->can_id & CAN_SFF_MASK;
+	}
+
+	if (cf->can_id & CAN_RTR_FLAG)
+		id |= RCANFD_CMFIFO_CFRTR;
+
+	rcar_canfd_write(priv, RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX),
+			 id);
+	ptr = RCANFD_CMFIFO_CFDLC(can_len2dlc(cf->len));
+	rcar_canfd_write(priv, RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX),
+			 ptr);
+
+	sts = rcar_canfd_read(priv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX));
+	if (can_is_canfd_skb(skb)) {
+		/* CAN FD frame format */
+		sts |= RCANFD_CMFIFO_CFFDF;
+		if (cf->flags & CANFD_BRS)
+			sts |= RCANFD_CMFIFO_CFBRS;
+		else
+			sts &= ~RCANFD_CMFIFO_CFBRS;
+	} else {
+		sts &= ~RCANFD_CMFIFO_CFFDF;
+	}
+	rcar_canfd_write(priv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), sts);
+
+	rcar_canfd_put_data(cf, priv,
+			    RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
+
+	priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
+	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
+
+	spin_lock_irqsave(&priv->tx_lock, flags);
+	priv->tx_head++;
+
+	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
+	 * pointer for the Common FIFO
+	 */
+	rcar_canfd_write(priv, RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
+
+	/* Stop the queue if we've filled all FIFO entries */
+	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
+		netif_stop_queue(ndev);
+
+	spin_unlock_irqrestore(&priv->tx_lock, flags);
+	return NETDEV_TX_OK;
+}
+
+static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
+{
+	struct net_device_stats *stats = &priv->ndev->stats;
+	struct canfd_frame *cf;
+	struct sk_buff *skb;
+	u32 sts = 0, id, ptr;
+	u32 ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	id = rcar_canfd_read(priv, RCANFD_F_RFID(ridx));
+	ptr = rcar_canfd_read(priv, RCANFD_F_RFPTR(ridx));
+
+	sts = rcar_canfd_read(priv, RCANFD_F_RFFDSTS(ridx));
+	if (sts & RCANFD_RFFIFO_RFFDF)
+		skb = alloc_canfd_skb(priv->ndev, &cf);
+	else
+		skb = alloc_can_skb(priv->ndev,
+				    (struct can_frame **)&cf);
+
+	if (!skb) {
+		stats->rx_dropped++;
+		return;
+	}
+
+	if (sts & RCANFD_RFFIFO_RFFDF)
+		cf->len = can_dlc2len(RCANFD_RFFIFO_RFDLC(ptr));
+	else
+		cf->len = get_can_dlc(RCANFD_RFFIFO_RFDLC(ptr));
+
+	if (sts & RCANFD_RFFIFO_RFESI) {
+		cf->flags |= CANFD_ESI;
+		netdev_dbg(priv->ndev, "ESI Error\n");
+	}
+
+	if (id & RCANFD_RFFIFO_RFIDE)
+		cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+	else
+		cf->can_id = id & CAN_SFF_MASK;
+
+	if (!(sts & RCANFD_RFFIFO_RFFDF) && (id & RCANFD_RFFIFO_RFRTR)) {
+		cf->can_id |= CAN_RTR_FLAG;
+	} else {
+		if (sts & RCANFD_RFFIFO_RFBRS)
+			cf->flags |= CANFD_BRS;
+
+		rcar_canfd_get_data(cf, priv, RCANFD_F_RFDF(ridx, 0));
+	}
+
+	/* Write 0xff to RFPC to increment the CPU-side
+	 * pointer of the Rx FIFO
+	 */
+	rcar_canfd_write(priv, RCANFD_RFPCTR(ridx), 0xff);
+
+	can_led_event(priv->ndev, CAN_LED_EVENT_RX);
+
+	stats->rx_bytes += cf->len;
+	stats->rx_packets++;
+	netif_receive_skb(skb);
+}
+
+static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
+{
+	struct rcar_canfd_channel *priv =
+		container_of(napi, struct rcar_canfd_channel, napi);
+	int num_pkts;
+	u32 sts;
+	u32 ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
+		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
+		/* Clear interrupt bit */
+		if (sts & RCANFD_RFFIFO_RFIF)
+			rcar_canfd_write(priv, RCANFD_RFSTS(ridx),
+					 sts & ~RCANFD_RFFIFO_RFIF);
+
+		/* Check FIFO empty condition */
+		if (sts & RCANFD_RFFIFO_RFEMP)
+			break;
+
+		rcar_canfd_rx_pkt(priv);
+	}
+
+	/* All packets processed */
+	if (num_pkts < quota) {
+		napi_complete(napi);
+		/* Enable Rx FIFO interrupts */
+		rcar_canfd_set_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFIE);
+	}
+	return num_pkts;
+}
+
+static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
+{
+	int err;
+
+	switch (mode) {
+	case CAN_MODE_START:
+		err = rcar_canfd_start(ndev);
+		if (err)
+			return err;
+		netif_wake_queue(ndev);
+		return 0;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int rcar_canfd_get_berr_counter(const struct net_device *dev,
+				       struct can_berr_counter *bec)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(dev);
+	u32 val, ch = priv->channel;
+
+	/* Peripheral clock is already enabled in probe */
+	val = rcar_canfd_read(priv, RCANFD_CSTS(ch));
+	bec->txerr = RCANFD_CSTS_TECCNT(val);
+	bec->rxerr = RCANFD_CSTS_RECCNT(val);
+	return 0;
+}
+
+static const struct net_device_ops rcar_canfd_netdev_ops = {
+	.ndo_open = rcar_canfd_open,
+	.ndo_stop = rcar_canfd_close,
+	.ndo_start_xmit = rcar_canfd_start_xmit,
+	.ndo_change_mtu = can_change_mtu,
+};
+
+static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	struct platform_device *pdev = gpriv->pdev;
+	struct rcar_canfd_channel *priv;
+	struct net_device *ndev;
+	int err = -ENODEV;
+
+	ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
+	if (!ndev) {
+		dev_err(&pdev->dev, "alloc_candev() failed\n");
+		err = -ENOMEM;
+		goto fail;
+	}
+	priv = netdev_priv(ndev);
+
+	ndev->netdev_ops = &rcar_canfd_netdev_ops;
+	ndev->flags |= IFF_ECHO;
+	priv->ndev = ndev;
+	priv->base = gpriv->base;
+	priv->channel = ch;
+	priv->can.clock.freq = gpriv->freq;
+	dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
+
+	priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
+	priv->can.data_bittiming_const =
+		&rcar_canfd_data_bittiming_const;
+
+	/* Controller starts in CAN FD only mode */
+	can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
+	priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
+
+	priv->can.do_set_mode = rcar_canfd_do_set_mode;
+	priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
+	priv->gpriv = gpriv;
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+
+	netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
+		       RCANFD_NAPI_WEIGHT);
+	err = register_candev(ndev);
+	if (err) {
+		dev_err(&pdev->dev,
+			"register_candev() failed, error %d\n", err);
+		goto fail_candev;
+	}
+	spin_lock_init(&priv->tx_lock);
+	devm_can_led_init(ndev);
+	gpriv->ch[priv->channel] = priv;
+	dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
+	return 0;
+
+fail_candev:
+	netif_napi_del(&priv->napi);
+	free_candev(ndev);
+fail:
+	return err;
+}
+
+static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	struct rcar_canfd_channel *priv = gpriv->ch[ch];
+
+	if (priv) {
+		unregister_candev(priv->ndev);
+		netif_napi_del(&priv->napi);
+		free_candev(priv->ndev);
+	}
+}
+
+static int rcar_canfd_probe(struct platform_device *pdev)
+{
+	struct resource *mem;
+	void __iomem *addr;
+	u32 sts, ch;
+	struct rcar_canfd_global *gpriv;
+	struct device_node *of_child;
+	unsigned long channels_mask = 0;
+	int err, ch_irq, g_irq;
+
+	of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
+	if (of_child && of_device_is_available(of_child))
+		channels_mask |= BIT(0);	/* Channel 0 */
+
+	of_child = of_get_child_by_name(pdev->dev.of_node, "channel1");
+	if (of_child && of_device_is_available(of_child))
+		channels_mask |= BIT(1);	/* Channel 1 */
+
+	ch_irq = platform_get_irq(pdev, 0);
+	if (ch_irq < 0) {
+		dev_err(&pdev->dev, "no Channel IRQ resource\n");
+		err = ch_irq;
+		goto fail_dev;
+	}
+
+	g_irq = platform_get_irq(pdev, 1);
+	if (g_irq < 0) {
+		dev_err(&pdev->dev, "no Global IRQ resource\n");
+		err = g_irq;
+		goto fail_dev;
+	}
+
+	/* Global controller context */
+	gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
+	if (!gpriv) {
+		err = -ENOMEM;
+		goto fail_dev;
+	}
+	gpriv->pdev = pdev;
+	gpriv->channels_mask = channels_mask;
+
+	/* Peripheral clock */
+	gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
+	if (IS_ERR(gpriv->clkp)) {
+		err = PTR_ERR(gpriv->clkp);
+		dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
+			err);
+		goto fail_dev;
+	}
+
+	/* fCAN clock: Pick External clock. If not available fallback to
+	 * CANFD clock
+	 */
+	gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
+	if (IS_ERR(gpriv->can_clk)) {
+		gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
+		if (IS_ERR(gpriv->can_clk)) {
+			err = PTR_ERR(gpriv->can_clk);
+			dev_err(&pdev->dev,
+				"cannot get canfd clock, error %d\n", err);
+			goto fail_dev;
+		}
+		gpriv->clock_select = RCANFD_CANFDCLK;
+
+	} else {
+		gpriv->clock_select = RCANFD_EXTCLK;
+	}
+	gpriv->freq = clk_get_rate(gpriv->can_clk);
+
+	if (gpriv->clock_select == RCANFD_CANFDCLK)
+		/* CANFD clock is further divided by (1/2) within the IP */
+		gpriv->freq /= 2;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	addr = devm_ioremap_resource(&pdev->dev, mem);
+	if (IS_ERR(addr)) {
+		err = PTR_ERR(addr);
+		goto fail_dev;
+	}
+	gpriv->base = addr;
+
+	/* Request IRQ that's common for both channels */
+	err = devm_request_irq(&pdev->dev, ch_irq,
+			       rcar_canfd_channel_interrupt, 0,
+			       "canfd.chn", gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+			ch_irq, err);
+		goto fail_dev;
+	}
+	err = devm_request_irq(&pdev->dev, g_irq,
+			       rcar_canfd_global_interrupt, 0,
+			       "canfd.gbl", gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+			g_irq, err);
+		goto fail_dev;
+	}
+
+	/* Enable peripheral clock for register access */
+	err = clk_prepare_enable(gpriv->clkp);
+	if (err) {
+		dev_err(&pdev->dev,
+			"failed to enable peripheral clock, error %d\n", err);
+		goto fail_dev;
+	}
+
+	err = rcar_canfd_reset_controller(gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "reset controller failed\n");
+		goto fail_clk;
+	}
+
+	/* Controller in Global reset & Channel reset mode */
+	rcar_canfd_configure_controller(gpriv);
+
+	/* Configure per channel attributes */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		/* Configure Channel's Rx fifo */
+		rcar_canfd_configure_rx(gpriv, ch);
+
+		/* Configure Channel's Tx (Common) fifo */
+		rcar_canfd_configure_tx(gpriv, ch);
+
+		/* Configure receive rules */
+		rcar_canfd_configure_afl_rules(gpriv, ch);
+	}
+
+	/* Configure common interrupts */
+	rcar_canfd_enable_global_interrupts(gpriv);
+
+	/* Start Global operation mode */
+	rcar_canfd_update_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_MODEMASK,
+			      RCANFD_GCTR_GOPM);
+
+	/* Verify mode change */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
+	if (err) {
+		dev_err(&pdev->dev, "global operational mode failed\n");
+		goto fail_mode;
+	}
+
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		err = rcar_canfd_channel_probe(gpriv, ch);
+		if (err)
+			goto fail_channel;
+	}
+
+	platform_set_drvdata(pdev, gpriv);
+	dev_info(&pdev->dev, "global operational state (clk %d)\n",
+		 gpriv->clock_select);
+	return 0;
+
+fail_channel:
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+		rcar_canfd_channel_remove(gpriv, ch);
+fail_mode:
+	rcar_canfd_disable_global_interrupts(gpriv);
+fail_clk:
+	clk_disable_unprepare(gpriv->clkp);
+fail_dev:
+	return err;
+}
+
+static int rcar_canfd_remove(struct platform_device *pdev)
+{
+	struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
+	struct rcar_canfd_channel *priv;
+	u32 ch;
+
+	rcar_canfd_reset_controller(gpriv);
+	rcar_canfd_disable_global_interrupts(gpriv);
+
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		if (priv) {
+			rcar_canfd_disable_channel_interrupts(priv);
+			unregister_candev(priv->ndev);
+			netif_napi_del(&priv->napi);
+			free_candev(priv->ndev);
+		}
+	}
+
+	/* Enter global sleep mode */
+	rcar_canfd_set_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_SLPR);
+	clk_disable_unprepare(gpriv->clkp);
+	return 0;
+}
+
+static int __maybe_unused rcar_canfd_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int __maybe_unused rcar_canfd_resume(struct device *dev)
+{
+	return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
+			 rcar_canfd_resume);
+
+static const struct of_device_id rcar_canfd_of_table[] = {
+	{ .compatible = "renesas,rcar-gen3-canfd" },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
+
+static struct platform_driver rcar_canfd_driver = {
+	.driver = {
+		.name = RCANFD_DRV_NAME,
+		.of_match_table = of_match_ptr(rcar_canfd_of_table),
+		.pm = &rcar_canfd_pm_ops,
+	},
+	.probe = rcar_canfd_probe,
+	.remove = rcar_canfd_remove,
+};
+
+module_platform_driver(rcar_canfd_driver);
+
+MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
+MODULE_ALIAS("platform:" RCANFD_DRV_NAME);
-- 
1.9.1

[PATCH 2/2] can: rcar_can: Move Renesas CAN driver to rcar dir

[Ramesh Shanmugasundaram]

This patch clubs the Renesas controller drivers in one rcar dir.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
---
 drivers/net/can/Kconfig               | 10 ----------
 drivers/net/can/Makefile              |  1 -
 drivers/net/can/rcar/Kconfig          | 10 ++++++++++
 drivers/net/can/rcar/Makefile         |  3 ++-
 drivers/net/can/{ => rcar}/rcar_can.c |  0
 5 files changed, 12 insertions(+), 12 deletions(-)
 rename drivers/net/can/{ => rcar}/rcar_can.c (100%)

diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 13003a9..22570ea 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -104,16 +104,6 @@ config CAN_JANZ_ICAN3
 	  This driver can also be built as a module. If so, the module will be
 	  called janz-ican3.ko.
 
-config CAN_RCAR
-	tristate "Renesas R-Car CAN controller"
-	depends on ARCH_RENESAS || ARM
-	---help---
-	  Say Y here if you want to use CAN controller found on Renesas R-Car
-	  SoCs.
-
-	  To compile this driver as a module, choose M here: the module will
-	  be called rcar_can.
-
 config CAN_SUN4I
 	tristate "Allwinner A10 CAN controller"
 	depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index 226d5b5..26ba4b7 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_CAN_IFI_CANFD)	+= ifi_canfd/
 obj-$(CONFIG_CAN_JANZ_ICAN3)	+= janz-ican3.o
 obj-$(CONFIG_CAN_MSCAN)		+= mscan/
 obj-$(CONFIG_CAN_M_CAN)		+= m_can/
-obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
 obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
 obj-$(CONFIG_CAN_SUN4I)		+= sun4i_can.o
 obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
diff --git a/drivers/net/can/rcar/Kconfig b/drivers/net/can/rcar/Kconfig
index 6ea64d1..7b03a3a 100644
--- a/drivers/net/can/rcar/Kconfig
+++ b/drivers/net/can/rcar/Kconfig
@@ -1,3 +1,13 @@
+config CAN_RCAR
+	tristate "Renesas R-Car CAN controller"
+	depends on ARCH_RENESAS || ARM
+	---help---
+	  Say Y here if you want to use CAN controller found on Renesas R-Car
+	  SoCs.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called rcar_can.
+
 config CAN_RCAR_CANFD
 	tristate "Renesas R-Car CAN FD controller"
 	depends on ARCH_RENESAS || ARM
diff --git a/drivers/net/can/rcar/Makefile b/drivers/net/can/rcar/Makefile
index cbaf498e..08de36a 100644
--- a/drivers/net/can/rcar/Makefile
+++ b/drivers/net/can/rcar/Makefile
@@ -1,5 +1,6 @@
 #
-#  Makefile for the Renesas R-Car CAN FD controller driver
+#  Makefile for the Renesas R-Car CAN & CAN FD controller drivers
 #
 
+obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
 obj-$(CONFIG_CAN_RCAR_CANFD)	+= rcar_canfd.o
diff --git a/drivers/net/can/rcar_can.c b/drivers/net/can/rcar/rcar_can.c
similarity index 100%
rename from drivers/net/can/rcar_can.c
rename to drivers/net/can/rcar/rcar_can.c
-- 
1.9.1

Re: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Marc Kleine-Budde]

[-- Attachment #1.1: Type: text/plain, Size: 62051 bytes --]

On 03/03/2016 04:38 PM, Ramesh Shanmugasundaram wrote:
> This patch adds support for the CAN FD controller found in Renesas R-Car
> SoCs. The controller operates in CAN FD mode by default.
> 
> CAN FD mode supports both Classical CAN & CAN FD frame formats. The
> controller supports ISO 11898-1:2015 CAN FD format only.
> 
> This controller supports two channels and the driver can enable either
> or both of the channels.
> 
> Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs (one
> per channel) for transmission. Rx filter rules are configured to the
> minimum (one per channel) and it accepts Standard, Extended, Data &
> Remote Frame combinations.
> 
> Note: There are few documentation errors in R-Car Gen3 Hardware User
> Manual v0.5E with respect to CAN FD controller. They are listed below:
> 
> 1. CAN FD interrupt numbers 29 & 30 are listed as per channel
> interrupts. However, they are common to both channels (i.e.) they are
> global and channel interrupts respectively.
> 
> 2. CANFD clock is derived from PLL1. This is not documented.
> 
> 3. CANFD clock is further divided by (1/2) within the CAN FD controller.
> This is not documented.
> 
> 4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
> is mentioned 4 Tq in the manual.
> 
> 5. The maximum number of message RAM area the controller can use is 3584
> bytes. It is specified 10752 bytes in the manual.
> 
> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
> ---
> Changes since v1:
> 	* Removed testmodes & debugfs code (suggested by Oliver H)
> 	* Fixed tx path race issue by introducing lock (suggested by Marc K)
> 	* Removed __maybe_unused attribute of rcar_canfd_of_table
> 
> Thanks,
> Ramesh
> ---
>  .../devicetree/bindings/net/can/rcar_canfd.txt     |   86 ++
>  drivers/net/can/Kconfig                            |   10 +
>  drivers/net/can/Makefile                           |    1 +
>  drivers/net/can/rcar_canfd.c                       | 1624 ++++++++++++++++++++
>  4 files changed, 1721 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
>  create mode 100644 drivers/net/can/rcar_canfd.c
> 
> diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> new file mode 100644
> index 0000000..4299bd8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
> @@ -0,0 +1,86 @@
> +Renesas R-Car CAN FD controller Device Tree Bindings
> +----------------------------------------------------
> +
> +Required properties:
> +- compatible: Must contain one or more of the following:
> +  - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
> +  - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
> +
> +  When compatible with the generic version, nodes must list the
> +  SoC-specific version corresponding to the platform first, followed by the
> +  family-specific and/or generic versions.
> +
> +- reg: physical base address and size of the R-Car CAN FD register map.
> +- interrupts: interrupt specifier for the Global & Channel interrupts
> +- clocks: phandles and clock specifiers for 3 clock inputs.
> +- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
> +- pinctrl-0: pin control group to be used for this controller.
> +- pinctrl-names: must be "default".
> +
> +Required properties for "renesas,r8a7795-canfd" compatible:
> +In R8A7795 SoC, canfd clock is a div6 clock and can be used by both CAN
> +and CAN FD controller at the same time. It needs to be scaled to maximum
> +frequency if any of these controllers use it. This is done using the
> +below properties.
> +
> +- assigned-clocks: phandle of canfd clock.
> +- assigned-clock-rates: maximum frequency of this clock.
> +
> +Each channel is represented as a child node. They can be enabled/disabled
> +using "status" property.
> +
> +Example
> +-------
> +
> +SoC common .dtsi file:
> +
> +		canfd: canfd@e66c0000 {
> +			compatible = "renesas,r8a7795-canfd",
> +				     "renesas,rcar-gen3-canfd";
> +			reg = <0 0xe66c0000 0 0x8000>;
> +			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> +				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 914>,
> +			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
> +			       <&can_clk>;
> +			clock-names = "fck", "canfd", "can_clk";
> +			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
> +			assigned-clock-rates = <40000000>;
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +
> +			channel0 {
> +				status = "disabled";
> +			};
> +
> +			channel1 {
> +				status = "disabled";
> +			};
> +		};
> +
> +Board specific .dts file:
> +
> +E.g. below enables Channel 1 alone in the board.
> +
> +&canfd {
> +        pinctrl-0 = <&canfd1_pins>;
> +        pinctrl-names = "default";
> +        status = "okay";
> +
> +	channel1 {
> +		status = "okay";
> +	};
> +};
> +
> +E.g. below enables Channel 0 alone in the board using External clock
> +as fCAN clock.
> +
> +&canfd {
> +        pinctrl-0 = <&canfd0_pins &can_clk_pins>;
> +        pinctrl-names = "default";
> +        status = "okay";
> +
> +	channel0 {
> +		status = "okay";
> +	};
> +};
> diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
> index 0d40aef..0ecb4fe 100644
> --- a/drivers/net/can/Kconfig
> +++ b/drivers/net/can/Kconfig
> @@ -114,6 +114,16 @@ config CAN_RCAR
>  	  To compile this driver as a module, choose M here: the module will
>  	  be called rcar_can.
>  
> +config CANFD_RCAR
> +	tristate "Renesas R-Car CAN FD controller"
> +	depends on ARCH_RENESAS || ARM
> +	---help---
> +	  Say Y here if you want to use CAN FD controller found on
> +	  Renesas R-Car SoCs.
> +
> +	  To compile this driver as a module, choose M here: the module will
> +	  be called rcar_canfd.
> +
>  config CAN_SUN4I
>  	tristate "Allwinner A10 CAN controller"
>  	depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
> diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
> index e3db0c8..401b150 100644
> --- a/drivers/net/can/Makefile
> +++ b/drivers/net/can/Makefile
> @@ -25,6 +25,7 @@ obj-$(CONFIG_CAN_JANZ_ICAN3)	+= janz-ican3.o
>  obj-$(CONFIG_CAN_MSCAN)		+= mscan/
>  obj-$(CONFIG_CAN_M_CAN)		+= m_can/
>  obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
> +obj-$(CONFIG_CANFD_RCAR)	+= rcar_canfd.o
>  obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
>  obj-$(CONFIG_CAN_SUN4I)		+= sun4i_can.o
>  obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
> diff --git a/drivers/net/can/rcar_canfd.c b/drivers/net/can/rcar_canfd.c
> new file mode 100644
> index 0000000..56e089d
> --- /dev/null
> +++ b/drivers/net/can/rcar_canfd.c
> @@ -0,0 +1,1624 @@
> +/* Renesas R-Car CAN FD device driver
> + *
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/interrupt.h>
> +#include <linux/errno.h>
> +#include <linux/netdevice.h>
> +#include <linux/platform_device.h>
> +#include <linux/can/led.h>
> +#include <linux/can/dev.h>
> +#include <linux/clk.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/bitmap.h>
> +#include <linux/bitops.h>
> +#include <linux/iopoll.h>
> +
> +#define RCANFD_DRV_NAME			"rcar_canfd"
> +
> +#define RCANFD_FIFO_DEPTH		8	/* Tx FIFO depth */
> +#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
> +
> +#define RCANFD_NUM_CHANNELS		2
> +#define RCANFD_CHANNELS_MASK		0x3	/* Two channels max */

(BIT(RCANFD_NUM_CHANNELS) - 1

> +
> +/* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
> + * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
> + * number is added to RFFIFO index.
> + */
> +#define RCANFD_RFFIFO_IDX		0
> +
> +/* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
> + * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
> + */
> +#define RCANFD_CFFIFO_IDX		0
> +
> +/* Global register bits */
> +#define RCANFD_GINTF_CANFD		BIT(0)
> +
> +#define RCANFD_GCFG_TPRI		BIT(0)
> +#define RCANFD_GCFG_DCE			BIT(1)
> +#define RCANFD_GCFG_DCS			BIT(4)
> +#define RCANFD_GCFG_CMPOC		BIT(5)
> +#define RCANFD_GCFG_EEFE		BIT(6)
> +
> +#define RCANFD_GCTR_SLPR		BIT(2)
> +#define RCANFD_GCTR_MODEMASK		(0x3)
> +#define RCANFD_GCTR_GOPM		(0x0)
> +#define RCANFD_GCTR_GRESET		(0x1)
> +#define RCANFD_GCTR_GHLT		(0x2)
> +
> +#define RCANFD_GCTR_DEIE		BIT(8)
> +#define RCANFD_GCTR_MEIE		BIT(9)
> +#define RCANFD_GCTR_THLEIE		BIT(10)
> +#define RCANFD_GCTR_CFMPOFIE		BIT(11)
> +#define RCANFD_GCTR_TSRST		BIT(16)
> +
> +#define RCANFD_GSTS_RAMINIT		BIT(3)
> +#define RCANFD_GSTS_SLP			BIT(2)
> +#define RCANFD_GSTS_HLT			BIT(1)
> +#define RCANFD_GSTS_RESET		BIT(0)
> +
> +#define RCANFD_GSTS_GNOPM		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
> +
> +/* Channel register bits */
> +#define RCANFD_CCTR_CSLPR		BIT(2)
> +#define RCANFD_CCTR_MODEMASK		(0x3)
> +#define RCANFD_CCTR_COPM		(0x0)
> +#define RCANFD_CCTR_CRESET		(0x1)
> +#define RCANFD_CCTR_CHLT		(0x2)
> +#define RCANFD_CCTR_CTMASK		(0x3 << 25)
> +#define RCANFD_CCTR_CTMS_ILB		(0x3 << 25)
> +#define RCANFD_CCTR_CTME		BIT(24)
> +#define RCANFD_CCTR_ERRD		BIT(23)
> +#define RCANFD_CCTR_BOMMASK		(0x3 << 21)
> +#define RCANFD_CCTR_BOM_ENTRY		(0x1 << 21)
> +#define RCANFD_CCTR_TDCVFIE		BIT(19)
> +#define RCANFD_CCTR_SOCOIE		BIT(18)
> +#define RCANFD_CCTR_EOCOIE		BIT(17)
> +#define RCANFD_CCTR_TAIE		BIT(16)
> +#define RCANFD_CCTR_ALIE		BIT(15)
> +#define RCANFD_CCTR_BLIE		BIT(14)
> +#define RCANFD_CCTR_OLIE		BIT(13)
> +#define RCANFD_CCTR_BORIE		BIT(12)
> +#define RCANFD_CCTR_BOEIE		BIT(11)
> +#define RCANFD_CCTR_EPIE		BIT(10)
> +#define RCANFD_CCTR_EWIE		BIT(9)
> +#define RCANFD_CCTR_BEIE		BIT(8)
> +
> +#define RCANFD_CSTS_COM			BIT(7)
> +#define RCANFD_CSTS_REC			BIT(6)
> +#define RCANFD_CSTS_TRM			BIT(5)
> +#define RCANFD_CSTS_BO			BIT(4)
> +#define RCANFD_CSTS_EP			BIT(3)
> +#define RCANFD_CSTS_SLP			BIT(2)
> +#define RCANFD_CSTS_HALT		BIT(1)
> +#define RCANFD_CSTS_RESET		BIT(0)
> +
> +#define RCANFD_CSTS_TECCNT(x)		(((x) >> 24) & 0xff)
> +#define RCANFD_CSTS_RECCNT(x)		(((x) >> 16) & 0xff)
> +
> +/* Bit Configuration register */
> +#define RCANFD_BRP(x)			(((x) & 0x3ff) << 0)
> +#define RCANFD_SJW(x)			(((x) & 0x3) << 24)
> +#define RCANFD_TSEG1(x)			(((x) & 0xf) << 16)
> +#define RCANFD_TSEG2(x)			(((x) & 0x7) << 20)
> +
> +#define RCANFD_NR_BRP(x)		(((x) & 0x3ff) << 0)
> +#define RCANFD_NR_SJW(x)		(((x) & 0x1f) << 11)
> +#define RCANFD_NR_TSEG1(x)		(((x) & 0x7f) << 16)
> +#define RCANFD_NR_TSEG2(x)		(((x) & 0x1f) << 24)
> +
> +#define RCANFD_DR_BRP(x)		(((x) & 0xff) << 0)
> +#define RCANFD_DR_SJW(x)		(((x) & 0x7) << 24)
> +#define RCANFD_DR_TSEG1(x)		(((x) & 0xf) << 16)
> +#define RCANFD_DR_TSEG2(x)		(((x) & 0x7) << 20)
> +
> +/* Global Error flag bits */
> +#define RCANFD_GERFL_EEF1		BIT(17)
> +#define RCANFD_GERFL_EEF0		BIT(16)
> +#define RCANFD_GERFL_CMPOF		BIT(3)
> +#define RCANFD_GERFL_THLES		BIT(2)
> +#define RCANFD_GERFL_MES		BIT(1)
> +#define RCANFD_GERFL_DEF		BIT(0)
> +
> +#define RCANFD_GERFL_ERR(x)		((x) & (RCANFD_GERFL_EEF1 |\
> +						RCANFD_GERFL_EEF0 |\
> +						RCANFD_GERFL_MES |\
> +						RCANFD_GERFL_CMPOF))
> +
> +/* Channel Error flag bits */
> +#define RCANFD_CERFL_ADEF		BIT(14)
> +#define RCANFD_CERFL_B0EF		BIT(13)
> +#define RCANFD_CERFL_B1EF		BIT(12)
> +#define RCANFD_CERFL_CEF		BIT(11)
> +#define RCANFD_CERFL_AEF		BIT(10)
> +#define RCANFD_CERFL_FEF		BIT(9)
> +#define RCANFD_CERFL_SEF		BIT(8)
> +#define RCANFD_CERFL_ALEF		BIT(7)
> +#define RCANFD_CERFL_BLEF		BIT(6)
> +#define RCANFD_CERFL_OLEF		BIT(5)
> +#define RCANFD_CERFL_BOREF		BIT(4)
> +#define RCANFD_CERFL_BOEEF		BIT(3)
> +#define RCANFD_CERFL_EPEF		BIT(2)
> +#define RCANFD_CERFL_EWEF		BIT(1)
> +#define RCANFD_CERFL_BEF		BIT(0)
> +
> +#define RCANFD_CERFL_ERR(x)		((x) & (0x7fff)) /* above bits 14:0 */
> +
> +/* CAN FD specific registers */
> +#define RCANFD_DCFG_TDCE		BIT(9)
> +#define RCANFD_DCFG_TDCOC		BIT(8)
> +#define RCANFD_DCFG_TDCO(x)		(((x) & 0x7f) >> 16)
> +
> +#define RCANFD_DCSTS_TDCR(x)		(((x) >> 0) & 0x7f)
> +#define RCANFD_DCSTS_SOCCNT(x)		(((x) >> 24) & 0xff)
> +#define RCANFD_DCSTS_EOCCNT(x)		(((x) >> 16) & 0xff)
> +
> +#define RCANFD_DCSTS_TDCVF		BIT(7)
> +#define RCANFD_DCSTS_EOCO		BIT(8)
> +#define RCANFD_DCSTS_SOCO		BIT(9)
> +
> +/* Rx FIFO bits */
> +#define RCANFD_RFFIFO_RFIF		BIT(3)
> +#define RCANFD_RFFIFO_RFMLT		BIT(2)
> +#define RCANFD_RFFIFO_RFFLL		BIT(1)
> +#define RCANFD_RFFIFO_RFEMP		BIT(0)
> +
> +#define RCANFD_RFFIFO_RFESI		BIT(0)
> +#define RCANFD_RFFIFO_RFBRS		BIT(1)
> +#define RCANFD_RFFIFO_RFFDF		BIT(2)
> +
> +#define RCANFD_RFFIFO_RFIDE		BIT(31)
> +#define RCANFD_RFFIFO_RFRTR		BIT(30)
> +
> +#define RCANFD_RFFIFO_RFDLC(x)		(((x) >> 28) & 0xf)
> +#define RCANFD_RFFIFO_RFPTR(x)		(((x) >> 16) & 0xfff)
> +#define RCANFD_RFFIFO_RFTS(x)		(((x) >> 0) & 0xff)
> +
> +#define RCANFD_RFFIFO_RFIM		BIT(12)
> +#define RCANFD_RFFIFO_RFDC(x)		(((x) & 0x7) << 8)
> +#define RCANFD_RFFIFO_RFPLS(x)		(((x) & 0x7) << 4)
> +#define RCANFD_RFFIFO_RFIE		BIT(1)
> +#define RCANFD_RFFIFO_RFE		BIT(0)
> +
> +/* Common FIFO bits */
> +#define RCANFD_CMFIFO_TML(x)		(((x) & 0xf) << 20)
> +#define RCANFD_CMFIFO_M(x)		(((x) & 0x3) << 16)
> +#define RCANFD_CMFIFO_CFIM		BIT(12)
> +#define RCANFD_CMFIFO_DC(x)		(((x) & 0x7) << 8)
> +#define RCANFD_CMFIFO_PLS(x)		(((x) & 0x7) << 4)
> +#define RCANFD_CMFIFO_CFTXIE		BIT(2)
> +#define RCANFD_CMFIFO_CFE		BIT(0)
> +
> +#define RCANFD_CMFIFO_CFTXIF		BIT(4)
> +#define RCANFD_CMFIFO_CFMLT		BIT(2)
> +#define RCANFD_CMFIFO_CFFLL		BIT(1)
> +#define RCANFD_CMFIFO_CFEMP		BIT(0)
> +#define RCANFD_CMFIFO_CFMC(x)		(((x) >> 8) & 0xff)
> +
> +#define RCANFD_CMFIFO_CFESI		BIT(0)
> +#define RCANFD_CMFIFO_CFBRS		BIT(1)
> +#define RCANFD_CMFIFO_CFFDF		BIT(2)
> +
> +#define RCANFD_CMFIFO_CFIDE		BIT(31)
> +#define RCANFD_CMFIFO_CFRTR		BIT(30)
> +#define RCANFD_CMFIFO_CFID(x)		((x) & 0x1fffffff)
> +
> +#define RCANFD_CMFIFO_CFDLC(x)		(((x) & 0xf) << 28)
> +#define RCANFD_CMFIFO_CFPTR(x)		(((x) & 0xfff) << 16)
> +#define RCANFD_CMFIFO_CFTS(x)		(((x) & 0xff) << 0)
> +
> +/* Global Test Config register */
> +#define RCANFD_GTSTCFG_C0CBCE		BIT(0)
> +#define RCANFD_GTSTCFG_C1CBCE		BIT(1)
> +
> +#define RCANFD_GTSTCTR_ICBCTME		BIT(0)
> +
> +/* AFL Rx rules registers */
> +#define RCANFD_AFLCFG_SETRNC0(x)	(((x) & 0xff) << 24)
> +#define RCANFD_AFLCFG_SETRNC1(x)	(((x) & 0xff) << 16)

What about something like:

#define RCANFD_AFLCFG_SETRNC(n, x)	(((x) & 0xff) << (24 - n * 8))

This will save some if()s in the code

> +#define RCANFD_AFLCFG_GETRNC0(x)	(((x) >> 24) & 0xff)
> +#define RCANFD_AFLCFG_GETRNC1(x)	(((x) >> 16) & 0xff)
> +
> +#define RCANFD_AFL_PAGENUM(entry)	((entry) / 16)
> +
> +#define RCANFD_AFLCTR_AFLDAE		BIT(8)
> +#define RCANFD_AFLCTR_AFLPN(x)		((x) & 0x1f)
> +#define RCANFD_CHANNEL_NUMRULES		1	/* only one rule per channel */
> +#define RCANFD_AFLID_GAFLLB		BIT(29)
> +#define RCANFD_AFLPTR1_RFFIFO(x)	(1 << (x))
> +
> +/* Common register map offsets */
> +
> +/* Nominal rate registers */
> +#define RCANFD_CCFG(m)			(0x0000 + (0x10 * (m)))
> +#define RCANFD_CCTR(m)			(0x0004 + (0x10 * (m)))
> +#define RCANFD_CSTS(m)			(0x0008 + (0x10 * (m)))
> +#define RCANFD_CERFL(m)			(0x000C + (0x10 * (m)))
> +
> +/* Global registers */
> +#define RCANFD_GCFG			(0x0084)
> +#define RCANFD_GCTR			(0x0088)
> +#define RCANFD_GSTS			(0x008c)
> +#define RCANFD_GERFL			(0x0090)
> +#define RCANFD_GTSC			(0x0094)
> +#define RCANFD_GAFLECTR			(0x0098)
> +#define RCANFD_GAFLCFG0			(0x009c)
> +#define RCANFD_GAFLCFG1			(0x00a0)
> +#define RCANFD_RMNB			(0x00a4)
> +
> +#define RCANFD_RMND(y)			(0x00a8 + (0x04 * (y)))
> +
> +/* Rx FIFO Control registers */
> +#define RCANFD_RFCC(x)			(0x00b8 + (0x04 * (x)))
> +#define RCANFD_RFSTS(x)			(0x00d8 + (0x04 * (x)))
> +#define RCANFD_RFPCTR(x)		(0x00f8 + (0x04 * (x)))
> +
> +/* Common FIFO Control registers */
> +#define RCANFD_CFCC(ch, idx)		(0x0118 + (0x0c * (ch)) + \
> +					 (0x04 * (idx)))
> +#define RCANFD_CFSTS(ch, idx)		(0x0178 + (0x0c * (ch)) + \
> +					 (0x04 * (idx)))
> +#define RCANFD_CFPCTR(ch, idx)		(0x01d8 + (0x0c * (ch)) + \
> +					 (0x04 * (idx)))
> +
> +#define RCANFD_FESTS			(0x0238)
> +#define RCANFD_FFSTS			(0x023c)
> +#define RCANFD_FMSTS			(0x0240)
> +#define RCANFD_RFISTS			(0x0244)
> +#define RCANFD_CFRISTS			(0x0248)
> +#define RCANFD_CFTISTS			(0x024c)
> +
> +#define RCANFD_TMC(p)			(0x0250 + (0x01 * (p)))
> +#define RCANFD_TMSTS(p)			(0x02d0 + (0x01 * (p)))
> +
> +#define RCANFD_TMTRSTS(y)		(0x0350 + (0x04 * (y)))
> +#define RCANFD_TMTARSTS(y)		(0x0360 + (0x04 * (y)))
> +#define RCANFD_TMTCSTS(y)		(0x0370 + (0x04 * (y)))
> +#define RCANFD_TMTASTS(y)		(0x0380 + (0x04 * (y)))
> +#define RCANFD_TMIEC(y)			(0x0390 + (0x04 * (y)))
> +
> +#define RCANFD_TXQCC(m)			(0x03a0 + (0x04 * (m)))
> +#define RCANFD_TXQSTS(m)		(0x03c0 + (0x04 * (m)))
> +#define RCANFD_TXQPCTR(m)		(0x03e0 + (0x04 * (m)))
> +
> +#define RCANFD_THLCC(m)			(0x0400 + (0x04 * (m)))
> +#define RCANFD_THLSTS(m)		(0x0420 + (0x04 * (m)))
> +#define RCANFD_THLPCTR(m)		(0x0440 + (0x04 * (m)))
> +
> +#define RCANFD_GTINTSTS0		(0x0460)
> +#define RCANFD_GTINTSTS1		(0x0464)
> +#define RCANFD_GTSTCFG			(0x0468)
> +#define RCANFD_GTSTCTR			(0x046c)
> +#define RCANFD_GLOCKK			(0x047c)
> +#define RCANFD_GRMCFG			(0x04fc)
> +
> +/* Receive rule registers */
> +#define RCANFD_GAFLID(offset, j)	((offset) + (0x10 * (j)))
> +#define RCANFD_GAFLM(offset, j)		((offset) + 0x04 + (0x10 * (j)))
> +#define RCANFD_GAFLP0(offset, j)	((offset) + 0x08 + (0x10 * (j)))
> +#define RCANFD_GAFLP1(offset, j)	((offset) + 0x0c + (0x10 * (j)))
> +
> +/* CAN FD mode specific regsiter map */
> +
> +/* Data bitrate registers */
> +#define RCANFD_F_CDFG(m)		(0x0500 + (0x20 * (m)))
> +#define RCANFD_F_CFDCFG(m)		(0x0504 + (0x20 * (m)))
> +#define RCANFD_F_CFDCTR(m)		(0x0508 + (0x20 * (m)))
> +#define RCANFD_F_CFDSTS(m)		(0x050c + (0x20 * (m)))
> +#define RCANFD_F_CFDCRC(m)		(0x0510 + (0x20 * (m)))
> +
> +#define RCANFD_F_GAFL_OFFSET		(0x1000)
> +
> +#define RCANFD_F_RMID(q)		(0x2000 + (0x10 * (q)))
> +#define RCANFD_F_RMPTR(q)		(0x2004 + (0x10 * (q)))
> +#define RCANFD_F_RMFDSTS(q)		(0x2008 + (0x10 * (q)))
> +#define RCANFD_F_RMDF(q, b)		(0x200c + (0x04 * (b)) + (0x20 * (q)))
> +
> +/* Rx FIFO data registers */
> +#define RCANFD_F_RFOFFSET		(0x3000)
> +#define RCANFD_F_RFID(x)		(RCANFD_F_RFOFFSET + (0x80 * (x)))
> +#define RCANFD_F_RFPTR(x)		(RCANFD_F_RFOFFSET + 0x04 + \
> +					 (0x80 * (x)))
> +#define RCANFD_F_RFFDSTS(x)		(RCANFD_F_RFOFFSET + 0x08 + \
> +					 (0x80 * (x)))
> +#define RCANFD_F_RFDF(x, df)		(RCANFD_F_RFOFFSET + 0x0c + \
> +					 (0x80 * (x)) + (0x04 * (df)))
> +
> +/* Common FIFO data registers */
> +#define RCANFD_F_CFOFFSET		(0x3400)
> +#define RCANFD_F_CFID(ch, idx)		(RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
> +					 (0x80 * (idx)))
> +#define RCANFD_F_CFPTR(ch, idx)		(RCANFD_F_CFOFFSET + 0x04 + \
> +					 (0x180 * (ch)) + (0x80 * (idx)))
> +#define RCANFD_F_CFFDCSTS(ch, idx)	(RCANFD_F_CFOFFSET + 0x08 + \
> +					 (0x180 * (ch)) + (0x80 * (idx)))
> +#define RCANFD_F_CFDF(ch, idx, df)	(RCANFD_F_CFOFFSET + 0x0c + \
> +					 (0x180 * (ch)) + (0x80 * (idx)) + \
> +					 (0x04 * (df)))
> +
> +#define RCANFD_F_TMID(p)		(0x4000 + (0x20 * (p)))
> +#define RCANFD_F_TMPTR(p)		(0x4004 + (0x20 * (p)))
> +#define RCANFD_F_TMFDCTR(p)		(0x4008 + (0x20 * (p)))
> +#define RCANFD_F_TMDF(p, b)		(0x400c + (0x20 * (p)) + (0x04 * (b)))
> +
> +#define RCANFD_F_THLACC(m)		(0x6000 + (0x04 * (m)))
> +#define RCANFD_F_RPGACC(r)		(0x6400 + (0x04 * (r)))
> +
> +struct rcar_canfd_global;
> +
> +/* Channel priv data */
> +struct rcar_canfd_channel {
> +	struct can_priv can;			/* Must be the first member */
> +	struct net_device *ndev;
> +	struct rcar_canfd_global *gpriv;	/* Controller reference */
> +	void __iomem *base;			/* Register base address */
> +#ifdef CONFIG_DEBUG_FS
> +	struct dentry *dev_root;
> +#endif /* CONFIG_DEBUG_FS */
> +	struct napi_struct napi;
> +	u8  tx_len[RCANFD_FIFO_DEPTH];		/* For net stats */
> +	u32 tx_head;				/* Incremented on xmit */
> +	u32 tx_tail;				/* Incremented on xmit done */
> +	u32 channel;				/* Channel number */
> +	spinlock_t tx_lock;			/* To protect tx path */
> +};
> +
> +/* Global priv data */
> +struct rcar_canfd_global {
> +	struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
> +	void __iomem *base;		/* Register base address */
> +	struct platform_device *pdev;	/* Respective platform device */
> +	struct clk *clkp;		/* Peripheral clock */
> +	struct clk *can_clk;		/* fCAN clock */
> +	int clock_select;		/* CANFD or Ext clock */
        ^^^
please give the corresponding enum a proper name and use it here.

> +	unsigned long channels_mask;	/* Enabled channels mask */
> +	u32 freq;			/* fCAN clock frequency in Hz */

This value is not used outside of the probe function. You can pass the
freq to the individual channels via an argument.

> +};
> +
> +/* CAN FD mode nominal rate constants */
> +static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
> +	.name = RCANFD_DRV_NAME,
> +	.tseg1_min = 2,
> +	.tseg1_max = 128,
> +	.tseg2_min = 2,
> +	.tseg2_max = 32,
> +	.sjw_max = 32,
> +	.brp_min = 1,
> +	.brp_max = 1024,
> +	.brp_inc = 1,
> +};
> +
> +/* CAN FD mode data rate constants */
> +static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
> +	.name = RCANFD_DRV_NAME,
> +	.tseg1_min = 2,
> +	.tseg1_max = 16,
> +	.tseg2_min = 2,
> +	.tseg2_max = 8,
> +	.sjw_max = 8,
> +	.brp_min = 1,
> +	.brp_max = 256,
> +	.brp_inc = 1,
> +};
> +
> +/* fCAN clock select register settings */
> +enum {
> +	RCANFD_CANFDCLK = 0,	/* CANFD clock */
> +	RCANFD_EXTCLK,		/* Externally input clock */
> +};
> +
> +/* Helper functions */
> +static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
> +{
> +	u32 data = readl(reg);
> +
> +	data &= ~mask;
> +	data |= (val & mask);
> +	writel(data, reg);
> +}
> +
> +#define rcar_canfd_read(priv, offset)			\
> +	readl(priv->base + (offset))
> +#define rcar_canfd_write(priv, offset, val)		\
> +	writel(val, priv->base + (offset))
> +#define rcar_canfd_set_bit(priv, reg, val)		\
> +	rcar_canfd_update(val, val, priv->base + (reg))
> +#define rcar_canfd_clear_bit(priv, reg, val)		\
> +	rcar_canfd_update(val, 0, priv->base + (reg))
> +#define rcar_canfd_update_bit(priv, reg, mask, val)	\
> +	rcar_canfd_update(mask, val, priv->base + (reg))

please use static inline functions instead of defines.

> +
> +static void rcar_canfd_get_data(struct canfd_frame *cf,
> +				struct rcar_canfd_channel *priv, u32 off)

Please use "struct rcar_canfd_channel *priv" as first argument, struct
canfd_frame *cf as second. Remove off, as the offset is already defined
by the channel.

> +{
> +	u32 i, lwords;
> +
> +	lwords = cf->len / sizeof(u32);
> +	if (cf->len % sizeof(u32))
> +		lwords++;

Use DIV_ROUND_UP() instead of open coding it.

> +	for (i = 0; i < lwords; i++)
> +		*((u32 *)cf->data + i) =
> +			rcar_canfd_read(priv, off + (i * sizeof(u32)));
> +}
> +
> +static void rcar_canfd_put_data(struct canfd_frame *cf,
> +				struct rcar_canfd_channel *priv, u32 off)

same here

> +{
> +	u32 i, j, lwords, leftover;
> +	u32 data = 0;
> +
> +	lwords = cf->len / sizeof(u32);
> +	leftover = cf->len % sizeof(u32);
> +	for (i = 0; i < lwords; i++)
> +		rcar_canfd_write(priv, off + (i * sizeof(u32)),
> +				 *((u32 *)cf->data + i));

Here you don't convert the endianess...
> +
> +	if (leftover) {
> +		u8 *p = (u8 *)((u32 *)cf->data + i);
> +
> +		for (j = 0; j < leftover; j++)
> +			data |= p[j] << (j * 8);

...here you do an implicit endianess conversion. "data" is little
endian, while p[j] is big endian.

> +		rcar_canfd_write(priv, off + (i * sizeof(u32)), data);
> +	}

Have you tested to send CAN frames with len != n*4 against a different
controller?

> +}
> +
> +static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
> +{
> +	u32 i;
> +
> +	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
> +		can_free_echo_skb(ndev, i);
> +}
> +
> +static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
> +{
> +	u32 sts, ch;
> +	int err;
> +
> +	/* Check RAMINIT flag as CAN RAM initialization takes place
> +	 * after the MCU reset
> +	 */
> +	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
> +				 !(sts & RCANFD_GSTS_RAMINIT), 2, 500000);
> +	if (err) {
> +		dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
> +		return err;
> +	}
> +
> +	/* Transition to Global Reset mode */
> +	rcar_canfd_clear_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_SLPR);
> +	rcar_canfd_update_bit(gpriv, RCANFD_GCTR,
> +			      RCANFD_GCTR_MODEMASK, RCANFD_GCTR_GRESET);
> +
> +	/* Ensure Global reset mode */
> +	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
> +				 (sts & RCANFD_GSTS_RESET), 2, 500000);
> +	if (err) {
> +		dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
> +		return err;
> +	}
> +
> +	/* Reset Global error flags */
> +	rcar_canfd_write(gpriv, RCANFD_GERFL, 0x0);
> +
> +	/* Set the controller into FD mode */
> +	rcar_canfd_set_bit(gpriv, RCANFD_GRMCFG, RCANFD_GINTF_CANFD);
> +
> +	/* Transition all Channels to reset mode */
> +	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
> +		rcar_canfd_clear_bit(gpriv, RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
> +
> +		rcar_canfd_update_bit(gpriv, RCANFD_CCTR(ch),
> +				      RCANFD_CCTR_MODEMASK,
> +				      RCANFD_CCTR_CRESET);
> +
> +		/* Ensure Channel reset mode */
> +		err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
> +					 (sts & RCANFD_CSTS_RESET), 2, 500000);
> +		if (err) {
> +			dev_dbg(&gpriv->pdev->dev,
> +				"channel %u reset failed\n", ch);
> +			return err;
> +		}
> +	}
> +	return 0;
> +}
> +
> +static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
> +{
> +	u32 cfg, ch;
> +
> +	/* Global Configuration settings */
> +	cfg = RCANFD_GCFG_EEFE;		/* ECC error flag enabled */
> +
> +	/* Set External Clock if selected */
> +	if (gpriv->clock_select != RCANFD_CANFDCLK)
> +		cfg |= RCANFD_GCFG_DCS;
> +
> +	/* Truncate payload to configured message size RFPLS */
> +	cfg |= RCANFD_GCFG_CMPOC;
> +
> +	rcar_canfd_set_bit(gpriv, RCANFD_GCFG, cfg);
> +
> +	/* Channel configuration settings */
> +	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
> +		rcar_canfd_set_bit(gpriv, RCANFD_CCTR(ch), RCANFD_CCTR_ERRD);
> +		rcar_canfd_update_bit(gpriv, RCANFD_CCTR(ch),
> +				      RCANFD_CCTR_BOMMASK,
> +				      RCANFD_CCTR_BOM_ENTRY);
> +	}
> +}
> +
> +static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
> +					   u32 ch)
> +{
> +	u32 cfg;
> +	int start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
> +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
> +
> +	if (ch == 0) {
> +		start = 0; /* Start from 0th rule */
> +	} else {
> +		/* Get number of existing rules and adjust */
> +		cfg = rcar_canfd_read(gpriv, RCANFD_GAFLCFG0);
> +		start = RCANFD_AFLCFG_GETRNC0(cfg);
> +	}
> +
> +	/* Enable write access to entry */
> +	page = RCANFD_AFL_PAGENUM(start);
> +	rcar_canfd_set_bit(gpriv, RCANFD_GAFLECTR,
> +			   (RCANFD_AFLCTR_AFLPN(page) | RCANFD_AFLCTR_AFLDAE));
> +
> +	/* Write number of rules for channel */
> +	if (ch == 0)
> +		rcar_canfd_set_bit(gpriv, RCANFD_GAFLCFG0,
> +				   RCANFD_AFLCFG_SETRNC0(num_rules));
> +	else
> +		rcar_canfd_set_bit(gpriv, RCANFD_GAFLCFG0,
> +				   RCANFD_AFLCFG_SETRNC1(num_rules));
> +
> +	/* Accept all IDs */
> +	rcar_canfd_write(gpriv, RCANFD_GAFLID(RCANFD_F_GAFL_OFFSET, start), 0);
> +	/* IDE or RTR is not considered for matching */
> +	rcar_canfd_write(gpriv, RCANFD_GAFLM(RCANFD_F_GAFL_OFFSET, start), 0);
> +	/* Any data length accepted */
> +	rcar_canfd_write(gpriv, RCANFD_GAFLP0(RCANFD_F_GAFL_OFFSET, start), 0);
> +	/* Place the msg in corresponding Rx FIFO entry */
> +	rcar_canfd_write(gpriv, RCANFD_GAFLP1(RCANFD_F_GAFL_OFFSET, start),
> +			 RCANFD_AFLPTR1_RFFIFO(ridx));
> +
> +	/* Disable write access to page */
> +	rcar_canfd_clear_bit(gpriv, RCANFD_GAFLECTR, RCANFD_AFLCTR_AFLDAE);
> +}
> +
> +static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
> +{
> +	/* Rx FIFO is used for reception */
> +	u32 cfg;
> +	u16 rfdc, rfpls;
> +
> +	/* Select Rx FIFO based on channel */
> +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
> +
> +	rfdc = 2;		/* b010 - 8 messages Rx FIFO depth */
> +	rfpls = 7;		/* b111 - Max 64 bytes payload */
> +
> +	cfg = (RCANFD_RFFIFO_RFIM | RCANFD_RFFIFO_RFDC(rfdc) |
> +		RCANFD_RFFIFO_RFPLS(rfpls) | RCANFD_RFFIFO_RFIE);
> +	rcar_canfd_write(gpriv, RCANFD_RFCC(ridx), cfg);
> +}
> +
> +static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
> +{
> +	/* Tx/Rx(Common) FIFO configured in Tx mode is
> +	 * used for transmission
> +	 *
> +	 * Each channel has 3 Common FIFO dedicated to them.
> +	 * Use the 1st (index 0) out of 3
> +	 */
> +	u32 cfg;
> +	u16 cftml, cfm, cfdc, cfpls;
> +
> +	cftml = 0;		/* 0th buffer */
> +	cfm = 1;		/* b01 - Transmit mode */
> +	cfdc = 2;		/* b010 - 8 messages Tx FIFO depth */
> +	cfpls = 7;		/* b111 - Max 64 bytes payload */
> +
> +	cfg = (RCANFD_CMFIFO_TML(cftml) | RCANFD_CMFIFO_M(cfm) |
> +		RCANFD_CMFIFO_CFIM | RCANFD_CMFIFO_DC(cfdc) |
> +		RCANFD_CMFIFO_PLS(cfpls) | RCANFD_CMFIFO_CFTXIE);
> +	rcar_canfd_write(gpriv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
> +
> +	/* Clear FD mode specific control/status register */
> +	rcar_canfd_write(gpriv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
> +}
> +
> +static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
> +{
> +	u32 ctr;
> +
> +	/* Clear any stray error interrupt flags */
> +	rcar_canfd_write(gpriv, RCANFD_GERFL, 0);
> +
> +	/* Global interrupts setup */
> +	ctr = RCANFD_GCTR_MEIE;
> +	ctr |= RCANFD_GCTR_CFMPOFIE;
> +
> +	rcar_canfd_set_bit(gpriv, RCANFD_GCTR, ctr);
> +}
> +
> +static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
> +						 *gpriv)
> +{
> +	/* Disable all interrupts */
> +	rcar_canfd_write(gpriv, RCANFD_GCTR, 0);
> +
> +	/* Clear any stray error interrupt flags */
> +	rcar_canfd_write(gpriv, RCANFD_GERFL, 0);
> +}
> +
> +static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
> +						 *priv)
> +{
> +	u32 ctr, ch = priv->channel;
> +
> +	/* Clear any stray error flags */
> +	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
> +
> +	/* Channel interrupts setup */
> +	ctr = (RCANFD_CCTR_TAIE |
> +	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
> +	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
> +	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
> +	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
> +	rcar_canfd_set_bit(priv, RCANFD_CCTR(ch), ctr);
> +}
> +
> +static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
> +						  *priv)
> +{
> +	u32 ctr, ch = priv->channel;
> +
> +	ctr = (RCANFD_CCTR_TAIE |
> +	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
> +	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
> +	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
> +	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
> +	rcar_canfd_clear_bit(priv, RCANFD_CCTR(ch), ctr);
> +
> +	/* Clear any stray error flags */
> +	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
> +}
> +
> +static void rcar_canfd_global_error(struct net_device *ndev)
> +{
> +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
> +	struct net_device_stats *stats = &ndev->stats;
> +	u32 ch = priv->channel;
> +	u32 gerfl, sts;
> +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
> +
> +	gerfl = rcar_canfd_read(priv, RCANFD_GERFL);
> +	if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
> +		netdev_dbg(ndev, "Ch0: ECC Error flag\n");
> +		stats->tx_dropped++;
> +	}
> +	if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
> +		netdev_dbg(ndev, "Ch1: ECC Error flag\n");
> +		stats->tx_dropped++;
> +	}
> +	if (gerfl & RCANFD_GERFL_MES) {
> +		sts = rcar_canfd_read(priv,
> +				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
> +		if (sts & RCANFD_CMFIFO_CFMLT) {
> +			netdev_dbg(ndev, "Tx Message Lost flag\n");
> +			stats->tx_dropped++;
> +			rcar_canfd_write(priv,
> +					 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
> +					 sts & ~RCANFD_CMFIFO_CFMLT);
> +		}
> +
> +		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
> +		if (sts & RCANFD_RFFIFO_RFMLT) {
> +			netdev_dbg(ndev, "Rx Message Lost flag\n");
> +			stats->rx_dropped++;
> +			rcar_canfd_write(priv, RCANFD_RFSTS(ridx),
> +					 sts & ~RCANFD_RFFIFO_RFMLT);
> +		}
> +	}
> +	if (gerfl & RCANFD_GERFL_CMPOF) {
> +		/* Message Lost flag will be set for respective channel
> +		 * when this condition happens with counters and flags
> +		 * already updated.
> +		 */
> +		netdev_dbg(ndev, "global payload overflow interrupt\n");
> +	}
> +
> +	/* Clear all global error interrupts. Only affected channels bits
> +	 * get cleared
> +	 */
> +	rcar_canfd_write(priv, RCANFD_GERFL, 0);
> +}
> +
> +static void rcar_canfd_error(struct net_device *ndev)
> +{
> +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
> +	struct net_device_stats *stats = &ndev->stats;
> +	struct can_frame *cf;
> +	struct sk_buff *skb;
> +	u32 cerfl, csts;
> +	u32 txerr = 0, rxerr = 0;
> +	u32 ch = priv->channel;
> +
> +	/* Propagate the error condition to the CAN stack */
> +	skb = alloc_can_err_skb(ndev, &cf);
> +	if (!skb) {
> +		stats->rx_dropped++;
> +		return;
> +	}
> +
> +	/* Channel error interrupt */
> +	cerfl = rcar_canfd_read(priv, RCANFD_CERFL(ch));
> +	csts = rcar_canfd_read(priv, RCANFD_CSTS(ch));
> +	txerr = RCANFD_CSTS_TECCNT(csts);
> +	rxerr = RCANFD_CSTS_RECCNT(csts);
> +
> +	netdev_dbg(ndev, "ch erfl %x sts %x txerr %u rxerr %u\n",
> +		   cerfl, csts, txerr, rxerr);
> +
> +	if (cerfl & RCANFD_CERFL_BEF) {
> +		netdev_dbg(ndev, "Bus error\n");
> +		cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
> +		cf->data[2] = CAN_ERR_PROT_UNSPEC;
> +		priv->can.can_stats.bus_error++;
> +	}
> +	if (cerfl & RCANFD_CERFL_ADEF) {
> +		netdev_dbg(ndev, "ACK Delimiter Error\n");
> +		stats->tx_errors++;
> +		cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
> +	}
> +	if (cerfl & RCANFD_CERFL_B0EF) {
> +		netdev_dbg(ndev, "Bit Error (dominant)\n");
> +		stats->tx_errors++;
> +		cf->data[2] |= CAN_ERR_PROT_BIT0;
> +	}
> +	if (cerfl & RCANFD_CERFL_B1EF) {
> +		netdev_dbg(ndev, "Bit Error (recessive)\n");
> +		stats->tx_errors++;
> +		cf->data[2] |= CAN_ERR_PROT_BIT1;
> +	}
> +	if (cerfl & RCANFD_CERFL_CEF) {
> +		netdev_dbg(ndev, "CRC Error\n");
> +		stats->rx_errors++;
> +		cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
> +	}
> +	if (cerfl & RCANFD_CERFL_AEF) {
> +		netdev_dbg(ndev, "ACK Error\n");
> +		stats->tx_errors++;
> +		cf->can_id |= CAN_ERR_ACK;
> +		cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
> +	}
> +	if (cerfl & RCANFD_CERFL_FEF) {
> +		netdev_dbg(ndev, "Form Error\n");
> +		stats->rx_errors++;
> +		cf->data[2] |= CAN_ERR_PROT_FORM;
> +	}
> +	if (cerfl & RCANFD_CERFL_SEF) {
> +		netdev_dbg(ndev, "Stuff Error\n");
> +		stats->rx_errors++;
> +		cf->data[2] |= CAN_ERR_PROT_STUFF;
> +	}
> +	if (cerfl & RCANFD_CERFL_ALEF) {
> +		netdev_dbg(ndev, "Arbitration lost Error\n");
> +		priv->can.can_stats.arbitration_lost++;
> +		cf->can_id |= CAN_ERR_LOSTARB;
> +		cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
> +	}
> +	if (cerfl & RCANFD_CERFL_BLEF) {
> +		netdev_dbg(ndev, "Bus Lock Error\n");
> +		stats->rx_errors++;
> +		cf->can_id |= CAN_ERR_BUSERROR;
> +	}
> +	if (cerfl & RCANFD_CERFL_EWEF) {
> +		netdev_dbg(ndev, "Error warning interrupt\n");
> +		priv->can.state = CAN_STATE_ERROR_WARNING;
> +		priv->can.can_stats.error_warning++;
> +		cf->can_id |= CAN_ERR_CRTL;
> +		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
> +			CAN_ERR_CRTL_RX_WARNING;
> +		cf->data[6] = txerr;
> +		cf->data[7] = rxerr;
> +	}
> +	if (cerfl & RCANFD_CERFL_EPEF) {
> +		netdev_dbg(ndev, "Error passive interrupt\n");
> +		priv->can.state = CAN_STATE_ERROR_PASSIVE;
> +		priv->can.can_stats.error_passive++;
> +		cf->can_id |= CAN_ERR_CRTL;
> +		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
> +			CAN_ERR_CRTL_RX_PASSIVE;
> +		cf->data[6] = txerr;
> +		cf->data[7] = rxerr;
> +	}
> +	if (cerfl & RCANFD_CERFL_BOEEF) {
> +		netdev_dbg(ndev, "Bus-off entry interrupt\n");
> +		rcar_canfd_tx_failure_cleanup(ndev);
> +		priv->can.state = CAN_STATE_BUS_OFF;
> +		priv->can.can_stats.bus_off++;
> +		can_bus_off(ndev);
> +		cf->can_id |= CAN_ERR_BUSOFF;
> +	}
> +	if (cerfl & RCANFD_CERFL_OLEF) {
> +		netdev_dbg(ndev,
> +			   "Overload Frame Transmission error interrupt\n");
> +		stats->tx_errors++;
> +		cf->can_id |= CAN_ERR_PROT;
> +		cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
> +	}
> +
> +	/* Clear all channel error interrupts */
> +	rcar_canfd_write(priv, RCANFD_CERFL(ch), 0);
> +	stats->rx_packets++;
> +	stats->rx_bytes += cf->can_dlc;
> +	netif_rx(skb);
> +}
> +
> +static void rcar_canfd_tx_done(struct net_device *ndev)
> +{
> +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
> +	struct net_device_stats *stats = &ndev->stats;
> +	u32 sts;
> +	unsigned long flags;
> +	u32 ch = priv->channel;
> +
> +	do {

You should iterare over all pending CAN frames:

> 	for (/* nix */; (priv->tx_head - priv->tx_tail) > 0; priv->tx_tail++) {


> +		u8 unsent, sent;
> +
> +		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;

and check here, if that packet has really been tramsitted. Exit the loop
otherweise.

> +		stats->tx_packets++;
> +		stats->tx_bytes += priv->tx_len[sent];
> +		priv->tx_len[sent] = 0;
> +		can_get_echo_skb(ndev, sent);
> +
> +		spin_lock_irqsave(&priv->tx_lock, flags);

What does the tx_lock protect? The tx path is per channel, isn't it?

> +		priv->tx_tail++;
> +		sts = rcar_canfd_read(priv,
> +				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
> +		unsent = RCANFD_CMFIFO_CFMC(sts);
> +
> +		/* Wake producer only when there is room */
> +		if (unsent != RCANFD_FIFO_DEPTH)
> +			netif_wake_queue(ndev);

Move the netif_wake_queue() out of the loop.

> +
> +		if (priv->tx_head - priv->tx_tail <= unsent) {
> +			spin_unlock_irqrestore(&priv->tx_lock, flags);
> +			break;
> +		}
> +		spin_unlock_irqrestore(&priv->tx_lock, flags);
> +
> +	} while (1);
> +
> +	/* Clear interrupt */
> +	rcar_canfd_write(priv, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
> +			 sts & ~RCANFD_CMFIFO_CFTXIF);
> +	can_led_event(ndev, CAN_LED_EVENT_TX);
> +}
> +
> +static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
> +{
> +	struct rcar_canfd_global *gpriv = dev_id;
> +	struct net_device *ndev;
> +	struct rcar_canfd_channel *priv;
> +	u32 sts, gerfl;
> +	u32 ch, ridx;
> +
> +	/* Global error interrupts still indicate a condition specific
> +	 * to a channel. RxFIFO interrupt is a global interrupt.
> +	 */
> +	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
> +		priv = gpriv->ch[ch];
> +		ndev = priv->ndev;
> +		ridx = ch + RCANFD_RFFIFO_IDX;
> +
> +		/* Global error interrupts */
> +		gerfl = rcar_canfd_read(priv, RCANFD_GERFL);
> +		if (RCANFD_GERFL_ERR(gerfl))
> +			rcar_canfd_global_error(ndev);
> +
> +		/* Handle Rx interrupts */
> +		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
> +		if (sts & RCANFD_RFFIFO_RFIF) {
> +			if (napi_schedule_prep(&priv->napi)) {
> +				/* Disable Rx FIFO interrupts */
> +				rcar_canfd_clear_bit(priv,
> +						     RCANFD_RFCC(ridx),
> +						     RCANFD_RFFIFO_RFIE);
> +				__napi_schedule(&priv->napi);
> +			}
> +		}
> +	}
> +	return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
> +{
> +	struct rcar_canfd_global *gpriv = dev_id;
> +	struct net_device *ndev;
> +	struct rcar_canfd_channel *priv;
> +	u32 sts, cerfl, ch;
> +
> +	/* Common FIFO is a per channel resource */
> +	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
> +		priv = gpriv->ch[ch];
> +		ndev = priv->ndev;
> +
> +		/* Channel error interrupts */
> +		cerfl = rcar_canfd_read(priv, RCANFD_CERFL(ch));
> +		if (RCANFD_CERFL_ERR(cerfl))
> +			rcar_canfd_error(ndev);
> +
> +		/* Handle Tx interrupts */
> +		sts = rcar_canfd_read(priv,
> +				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
> +		if (sts & RCANFD_CMFIFO_CFTXIF)
> +			rcar_canfd_tx_done(ndev);
> +	}
> +	return IRQ_HANDLED;
> +}
> +
> +static void rcar_canfd_set_bittiming(struct net_device *dev)
> +{
> +	struct rcar_canfd_channel *priv = netdev_priv(dev);
> +	const struct can_bittiming *bt = &priv->can.bittiming;
> +	const struct can_bittiming *dbt = &priv->can.data_bittiming;
> +	u16 brp, sjw, tseg1, tseg2;
> +	u32 cfg;
> +	u32 ch = priv->channel;
> +
> +	/* Nominal bit timing settings */
> +	brp = bt->brp - 1;
> +	sjw = bt->sjw - 1;
> +	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
> +	tseg2 = bt->phase_seg2 - 1;
> +
> +	cfg = (RCANFD_NR_TSEG1(tseg1) | RCANFD_NR_BRP(brp) |
> +	       RCANFD_NR_SJW(sjw) | RCANFD_NR_TSEG2(tseg2));
> +
> +	rcar_canfd_write(priv, RCANFD_CCFG(ch), cfg);
> +	netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
> +		   brp, sjw, tseg1, tseg2);
> +
> +	/* Data bit timing settings */
> +	brp = dbt->brp - 1;
> +	sjw = dbt->sjw - 1;
> +	tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
> +	tseg2 = dbt->phase_seg2 - 1;
> +
> +	cfg = (RCANFD_DR_TSEG1(tseg1) | RCANFD_DR_BRP(brp) |
> +	       RCANFD_DR_SJW(sjw) | RCANFD_DR_TSEG2(tseg2));
> +
> +	rcar_canfd_write(priv, RCANFD_F_CDFG(ch), cfg);
> +	netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
> +		   brp, sjw, tseg1, tseg2);
> +}
> +
> +static int rcar_canfd_start(struct net_device *ndev)
> +{
> +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
> +	int err = -EOPNOTSUPP;
> +	u32 sts, ch = priv->channel;
> +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
> +
> +	/* Ensure channel starts in FD mode */
> +	if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
> +		netdev_err(ndev, "enable can fd mode for channel %d\n", ch);
> +		goto fail_mode;
> +	}
> +
> +	rcar_canfd_set_bittiming(ndev);
> +
> +	rcar_canfd_enable_channel_interrupts(priv);
> +
> +	/* Set channel to Operational mode */
> +	rcar_canfd_update_bit(priv, RCANFD_CCTR(ch),
> +			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_COPM);
> +
> +	/* Verify channel mode change */
> +	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
> +				 (sts & RCANFD_CSTS_COM), 2, 500000);
> +	if (err) {
> +		netdev_err(ndev, "channel %u communication state failed\n", ch);
> +		goto fail_mode_change;
> +	}
> +
> +	/* Enable Common & Rx FIFO */
> +	rcar_canfd_set_bit(priv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
> +			   RCANFD_CMFIFO_CFE);
> +	rcar_canfd_set_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFE);
> +
> +	priv->can.state = CAN_STATE_ERROR_ACTIVE;
> +	return 0;
> +
> +fail_mode_change:
> +	rcar_canfd_disable_channel_interrupts(priv);
> +fail_mode:
> +	return err;
> +}
> +
> +static int rcar_canfd_open(struct net_device *ndev)
> +{
> +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
> +	struct rcar_canfd_global *gpriv = priv->gpriv;
> +	int err;
> +
> +	/* Peripheral clock is already enabled in probe */
> +	err = clk_prepare_enable(gpriv->can_clk);
> +	if (err) {
> +		netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
> +		goto out_clock;
> +	}
> +
> +	err = open_candev(ndev);
> +	if (err) {
> +		netdev_err(ndev, "open_candev() failed, error %d\n", err);
> +		goto out_can_clock;
> +	}
> +
> +	napi_enable(&priv->napi);
> +	err = rcar_canfd_start(ndev);
> +	if (err)
> +		goto out_close;
> +	netif_start_queue(ndev);
> +	can_led_event(ndev, CAN_LED_EVENT_OPEN);
> +	return 0;
> +out_close:
> +	napi_disable(&priv->napi);
> +	close_candev(ndev);
> +out_can_clock:
> +	clk_disable_unprepare(gpriv->can_clk);
> +out_clock:
> +	return err;
> +}
> +
> +static void rcar_canfd_stop(struct net_device *ndev)
> +{
> +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
> +	int err;
> +	u32 sts, ch = priv->channel;
> +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
> +
> +	/* Transition to channel reset mode  */
> +	rcar_canfd_update_bit(priv, RCANFD_CCTR(ch),
> +			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_CRESET);
> +
> +	/* Check Channel reset mode */
> +	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
> +				 (sts & RCANFD_CSTS_RESET), 2, 500000);
> +	if (err)
> +		netdev_err(ndev, "channel %u reset failed\n", ch);
> +
> +	rcar_canfd_disable_channel_interrupts(priv);
> +
> +	/* Disable Common & Rx FIFO */
> +	rcar_canfd_clear_bit(priv, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
> +			     RCANFD_CMFIFO_CFE);
> +	rcar_canfd_clear_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFE);
> +
> +	/* Set the state as STOPPED */
> +	priv->can.state = CAN_STATE_STOPPED;
> +}
> +
> +static int rcar_canfd_close(struct net_device *ndev)
> +{
> +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
> +	struct rcar_canfd_global *gpriv = priv->gpriv;
> +
> +	netif_stop_queue(ndev);
> +	rcar_canfd_stop(ndev);
> +	napi_disable(&priv->napi);
> +	clk_disable_unprepare(gpriv->can_clk);
> +	close_candev(ndev);
> +	can_led_event(ndev, CAN_LED_EVENT_STOP);
> +	return 0;
> +}
> +
> +static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
> +					 struct net_device *ndev)
> +{
> +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
> +	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
> +	u32 sts, id, ptr;
> +	unsigned long flags;
> +	u32 ch = priv->channel;
> +
> +	if (can_dropped_invalid_skb(ndev, skb))
> +		return NETDEV_TX_OK;
> +
> +	if (cf->can_id & CAN_EFF_FLAG) {
> +		id = cf->can_id & CAN_EFF_MASK;
> +		id |= RCANFD_CMFIFO_CFIDE;
> +	} else {
> +		id = cf->can_id & CAN_SFF_MASK;
> +	}
> +
> +	if (cf->can_id & CAN_RTR_FLAG)
> +		id |= RCANFD_CMFIFO_CFRTR;
> +
> +	rcar_canfd_write(priv, RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX),
> +			 id);
> +	ptr = RCANFD_CMFIFO_CFDLC(can_len2dlc(cf->len));

ptr usually means pointer, better call it dlc.

> +	rcar_canfd_write(priv, RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX),
> +			 ptr);
> +
> +	sts = rcar_canfd_read(priv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX));
> +	if (can_is_canfd_skb(skb)) {
> +		/* CAN FD frame format */
> +		sts |= RCANFD_CMFIFO_CFFDF;
> +		if (cf->flags & CANFD_BRS)
> +			sts |= RCANFD_CMFIFO_CFBRS;
> +		else
> +			sts &= ~RCANFD_CMFIFO_CFBRS;
> +	} else {
> +		sts &= ~RCANFD_CMFIFO_CFFDF;
> +	}
> +	rcar_canfd_write(priv, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), sts);
> +
> +	rcar_canfd_put_data(cf, priv,
> +			    RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
> +
> +	priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
> +	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
> +
> +	spin_lock_irqsave(&priv->tx_lock, flags);
> +	priv->tx_head++;
> +
> +	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
> +	 * pointer for the Common FIFO
> +	 */
> +	rcar_canfd_write(priv, RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
> +
> +	/* Stop the queue if we've filled all FIFO entries */
> +	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
> +		netif_stop_queue(ndev);

Please move the check of stop_queue, before starting the send.

> +
> +	spin_unlock_irqrestore(&priv->tx_lock, flags);
> +	return NETDEV_TX_OK;
> +}
> +
> +static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
> +{
> +	struct net_device_stats *stats = &priv->ndev->stats;
> +	struct canfd_frame *cf;
> +	struct sk_buff *skb;
> +	u32 sts = 0, id, ptr;
> +	u32 ch = priv->channel;
> +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
> +
> +	id = rcar_canfd_read(priv, RCANFD_F_RFID(ridx));
> +	ptr = rcar_canfd_read(priv, RCANFD_F_RFPTR(ridx));
> +
> +	sts = rcar_canfd_read(priv, RCANFD_F_RFFDSTS(ridx));
> +	if (sts & RCANFD_RFFIFO_RFFDF)
> +		skb = alloc_canfd_skb(priv->ndev, &cf);
> +	else
> +		skb = alloc_can_skb(priv->ndev,
> +				    (struct can_frame **)&cf);
> +
> +	if (!skb) {
> +		stats->rx_dropped++;
> +		return;
> +	}
> +
> +	if (sts & RCANFD_RFFIFO_RFFDF)
> +		cf->len = can_dlc2len(RCANFD_RFFIFO_RFDLC(ptr));
> +	else
> +		cf->len = get_can_dlc(RCANFD_RFFIFO_RFDLC(ptr));
> +
> +	if (sts & RCANFD_RFFIFO_RFESI) {
> +		cf->flags |= CANFD_ESI;
> +		netdev_dbg(priv->ndev, "ESI Error\n");
> +	}
> +
> +	if (id & RCANFD_RFFIFO_RFIDE)
> +		cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
> +	else
> +		cf->can_id = id & CAN_SFF_MASK;
> +
> +	if (!(sts & RCANFD_RFFIFO_RFFDF) && (id & RCANFD_RFFIFO_RFRTR)) {
> +		cf->can_id |= CAN_RTR_FLAG;
> +	} else {
> +		if (sts & RCANFD_RFFIFO_RFBRS)
> +			cf->flags |= CANFD_BRS;
> +
> +		rcar_canfd_get_data(cf, priv, RCANFD_F_RFDF(ridx, 0));
> +	}
> +
> +	/* Write 0xff to RFPC to increment the CPU-side
> +	 * pointer of the Rx FIFO
> +	 */
> +	rcar_canfd_write(priv, RCANFD_RFPCTR(ridx), 0xff);
> +
> +	can_led_event(priv->ndev, CAN_LED_EVENT_RX);
> +
> +	stats->rx_bytes += cf->len;
> +	stats->rx_packets++;
> +	netif_receive_skb(skb);
> +}
> +
> +static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
> +{
> +	struct rcar_canfd_channel *priv =
> +		container_of(napi, struct rcar_canfd_channel, napi);
> +	int num_pkts;
> +	u32 sts;
> +	u32 ch = priv->channel;
> +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
> +
> +	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
> +		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
> +		/* Clear interrupt bit */
> +		if (sts & RCANFD_RFFIFO_RFIF)
> +			rcar_canfd_write(priv, RCANFD_RFSTS(ridx),
> +					 sts & ~RCANFD_RFFIFO_RFIF);
> +
> +		/* Check FIFO empty condition */
> +		if (sts & RCANFD_RFFIFO_RFEMP)
> +			break;
> +
> +		rcar_canfd_rx_pkt(priv);

This sequence looks strange. You first conditionally ack the interrupt
then you check for empty fifo, then read the CAN frame. I would assume
that you first check if there's a CAN frame, read it and then clear the
interrupt.

> +	}
> +
> +	/* All packets processed */
> +	if (num_pkts < quota) {
> +		napi_complete(napi);
> +		/* Enable Rx FIFO interrupts */
> +		rcar_canfd_set_bit(priv, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFIE);
> +	}
> +	return num_pkts;
> +}
> +
> +static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
> +{
> +	int err;
> +
> +	switch (mode) {
> +	case CAN_MODE_START:
> +		err = rcar_canfd_start(ndev);
> +		if (err)
> +			return err;
> +		netif_wake_queue(ndev);
> +		return 0;
> +	default:
> +		return -EOPNOTSUPP;
> +	}
> +}
> +
> +static int rcar_canfd_get_berr_counter(const struct net_device *dev,
> +				       struct can_berr_counter *bec)
> +{
> +	struct rcar_canfd_channel *priv = netdev_priv(dev);
> +	u32 val, ch = priv->channel;
> +
> +	/* Peripheral clock is already enabled in probe */
> +	val = rcar_canfd_read(priv, RCANFD_CSTS(ch));
> +	bec->txerr = RCANFD_CSTS_TECCNT(val);
> +	bec->rxerr = RCANFD_CSTS_RECCNT(val);
> +	return 0;
> +}
> +
> +static const struct net_device_ops rcar_canfd_netdev_ops = {
> +	.ndo_open = rcar_canfd_open,
> +	.ndo_stop = rcar_canfd_close,
> +	.ndo_start_xmit = rcar_canfd_start_xmit,
> +	.ndo_change_mtu = can_change_mtu,
> +};
> +
> +static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch)
> +{
> +	struct platform_device *pdev = gpriv->pdev;
> +	struct rcar_canfd_channel *priv;
> +	struct net_device *ndev;
> +	int err = -ENODEV;
> +
> +	ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
> +	if (!ndev) {
> +		dev_err(&pdev->dev, "alloc_candev() failed\n");
> +		err = -ENOMEM;
> +		goto fail;
> +	}
> +	priv = netdev_priv(ndev);
> +
> +	ndev->netdev_ops = &rcar_canfd_netdev_ops;
> +	ndev->flags |= IFF_ECHO;
> +	priv->ndev = ndev;
> +	priv->base = gpriv->base;
> +	priv->channel = ch;
> +	priv->can.clock.freq = gpriv->freq;
> +	dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
> +
> +	priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
> +	priv->can.data_bittiming_const =
> +		&rcar_canfd_data_bittiming_const;
> +
> +	/* Controller starts in CAN FD mode, which supports classical CAN and
> +	 * CAN FD frames. For classical CAN frames only configurations, data
> +	 * bitrate should be configured the same as nominal bitrate.
> +	 */
> +	priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
> +		CAN_CTRLMODE_FD;
> +
> +	priv->can.do_set_mode = rcar_canfd_do_set_mode;
> +	priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
> +	priv->gpriv = gpriv;
> +	SET_NETDEV_DEV(ndev, &pdev->dev);
> +
> +	netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
> +		       RCANFD_NAPI_WEIGHT);
> +	err = register_candev(ndev);
> +	if (err) {
> +		dev_err(&pdev->dev,
> +			"register_candev() failed, error %d\n", err);
> +		goto fail_candev;
> +	}
> +	spin_lock_init(&priv->tx_lock);
> +	devm_can_led_init(ndev);
> +	gpriv->ch[priv->channel] = priv;
> +	dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
> +	return 0;
> +
> +fail_candev:
> +	netif_napi_del(&priv->napi);
> +	free_candev(ndev);
> +fail:
> +	return err;
> +}
> +
> +static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
> +{
> +	struct rcar_canfd_channel *priv = gpriv->ch[ch];
> +
> +	if (priv) {
> +		unregister_candev(priv->ndev);
> +		netif_napi_del(&priv->napi);
> +		free_candev(priv->ndev);
> +	}
> +}
> +
> +static int rcar_canfd_probe(struct platform_device *pdev)
> +{
> +	struct resource *mem;
> +	void __iomem *addr;
> +	u32 sts, ch;
> +	struct rcar_canfd_global *gpriv;
> +	struct device_node *of_child;
> +	unsigned long channels_mask = 0;
> +	int err, ch_irq, g_irq;
> +
> +	of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
> +	if (of_child && of_device_is_available(of_child))
> +		channels_mask |= BIT(0);	/* Channel 0 */
> +
> +	of_child = of_get_child_by_name(pdev->dev.of_node, "channel1");
> +	if (of_child && of_device_is_available(of_child))
> +		channels_mask |= BIT(1);	/* Channel 1 */
> +
> +	ch_irq = platform_get_irq(pdev, 0);
> +	if (ch_irq < 0) {
> +		dev_err(&pdev->dev, "no Channel IRQ resource\n");
> +		err = ch_irq;
> +		goto fail_dev;
> +	}
> +
> +	g_irq = platform_get_irq(pdev, 1);
> +	if (g_irq < 0) {
> +		dev_err(&pdev->dev, "no Global IRQ resource\n");
> +		err = g_irq;
> +		goto fail_dev;
> +	}
> +
> +	/* Global controller context */
> +	gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
> +	if (!gpriv) {
> +		err = -ENOMEM;
> +		goto fail_dev;
> +	}
> +	gpriv->pdev = pdev;
> +	gpriv->channels_mask = channels_mask;
> +
> +	/* Peripheral clock */
> +	gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
> +	if (IS_ERR(gpriv->clkp)) {
> +		err = PTR_ERR(gpriv->clkp);
> +		dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
> +			err);
> +		goto fail_dev;
> +	}
> +
> +	/* fCAN clock: Pick External clock. If not available fallback to
> +	 * CANFD clock
> +	 */
> +	gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
> +	if (IS_ERR(gpriv->can_clk)) {
> +		gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
> +		if (IS_ERR(gpriv->can_clk)) {
> +			err = PTR_ERR(gpriv->can_clk);
> +			dev_err(&pdev->dev,
> +				"cannot get canfd clock, error %d\n", err);
> +			goto fail_dev;
> +		}
> +		gpriv->clock_select = RCANFD_CANFDCLK;
> +
> +	} else {
> +		gpriv->clock_select = RCANFD_EXTCLK;
> +	}
> +	gpriv->freq = clk_get_rate(gpriv->can_clk);
> +
> +	if (gpriv->clock_select == RCANFD_CANFDCLK)
> +		/* CANFD clock is further divided by (1/2) within the IP */
> +		gpriv->freq /= 2;
> +
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	addr = devm_ioremap_resource(&pdev->dev, mem);
> +	if (IS_ERR(addr)) {
> +		err = PTR_ERR(addr);
> +		goto fail_dev;
> +	}
> +	gpriv->base = addr;
> +
> +	/* Request IRQ that's common for both channels */
> +	err = devm_request_irq(&pdev->dev, ch_irq,
> +			       rcar_canfd_channel_interrupt, 0,
> +			       "canfd.chn", gpriv);
> +	if (err) {
> +		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
> +			ch_irq, err);
> +		goto fail_dev;
> +	}
> +	err = devm_request_irq(&pdev->dev, g_irq,
> +			       rcar_canfd_global_interrupt, 0,
> +			       "canfd.gbl", gpriv);
> +	if (err) {
> +		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
> +			g_irq, err);
> +		goto fail_dev;
> +	}
> +
> +	/* Enable peripheral clock for register access */
> +	err = clk_prepare_enable(gpriv->clkp);
> +	if (err) {
> +		dev_err(&pdev->dev,
> +			"failed to enable peripheral clock, error %d\n", err);
> +		goto fail_dev;
> +	}
> +
> +	err = rcar_canfd_reset_controller(gpriv);
> +	if (err) {
> +		dev_err(&pdev->dev, "reset controller failed\n");
> +		goto fail_clk;
> +	}
> +
> +	/* Controller in Global reset & Channel reset mode */
> +	rcar_canfd_configure_controller(gpriv);
> +
> +	/* Configure per channel attributes */
> +	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
> +		/* Configure Channel's Rx fifo */
> +		rcar_canfd_configure_rx(gpriv, ch);
> +
> +		/* Configure Channel's Tx (Common) fifo */
> +		rcar_canfd_configure_tx(gpriv, ch);
> +
> +		/* Configure receive rules */
> +		rcar_canfd_configure_afl_rules(gpriv, ch);
> +	}
> +
> +	/* Configure common interrupts */
> +	rcar_canfd_enable_global_interrupts(gpriv);
> +
> +	/* Start Global operation mode */
> +	rcar_canfd_update_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_MODEMASK,
> +			      RCANFD_GCTR_GOPM);
> +
> +	/* Verify mode change */
> +	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
> +				 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
> +	if (err) {
> +		dev_err(&pdev->dev, "global operational mode failed\n");
> +		goto fail_mode;
> +	}
> +
> +	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
> +		err = rcar_canfd_channel_probe(gpriv, ch);
> +		if (err)
> +			goto fail_channel;
> +	}

Should the CAN IP core be clocked the whole time? What about shuting
down the clock and enabling it on ifup?

> +
> +	platform_set_drvdata(pdev, gpriv);
> +	dev_info(&pdev->dev, "global operational state (clk %d)\n",
> +		 gpriv->clock_select);
> +	return 0;
> +
> +fail_channel:
> +	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
> +		rcar_canfd_channel_remove(gpriv, ch);
> +fail_mode:
> +	rcar_canfd_disable_global_interrupts(gpriv);
> +fail_clk:
> +	clk_disable_unprepare(gpriv->clkp);
> +fail_dev:
> +	return err;
> +}
> +
> +static int rcar_canfd_remove(struct platform_device *pdev)
> +{
> +	struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
> +	struct rcar_canfd_channel *priv;
> +	u32 ch;
> +
> +	rcar_canfd_reset_controller(gpriv);
> +	rcar_canfd_disable_global_interrupts(gpriv);
> +
> +	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
> +		priv = gpriv->ch[ch];
> +		if (priv) {

This should always be true.

> +			rcar_canfd_disable_channel_interrupts(priv);
> +			unregister_candev(priv->ndev);
> +			netif_napi_del(&priv->napi);
> +			free_candev(priv->ndev);

Please make use of rcar_canfd_channel_remove(), as you already have the
function.

> +		}
> +	}
> +
> +	/* Enter global sleep mode */
> +	rcar_canfd_set_bit(gpriv, RCANFD_GCTR, RCANFD_GCTR_SLPR);
> +	clk_disable_unprepare(gpriv->clkp);
> +	return 0;
> +}
> +
> +static int __maybe_unused rcar_canfd_suspend(struct device *dev)
> +{
> +	return 0;
> +}
> +
> +static int __maybe_unused rcar_canfd_resume(struct device *dev)
> +{
> +	return 0;
> +}
> +
> +static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
> +			 rcar_canfd_resume);
> +
> +static const struct of_device_id rcar_canfd_of_table[] = {
> +	{ .compatible = "renesas,rcar-gen3-canfd" },
> +	{ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
> +
> +static struct platform_driver rcar_canfd_driver = {
> +	.driver = {
> +		.name = RCANFD_DRV_NAME,
> +		.of_match_table = of_match_ptr(rcar_canfd_of_table),
> +		.pm = &rcar_canfd_pm_ops,
> +	},
> +	.probe = rcar_canfd_probe,
> +	.remove = rcar_canfd_remove,
> +};
> +
> +module_platform_driver(rcar_canfd_driver);
> +
> +MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
> +MODULE_ALIAS("platform:" RCANFD_DRV_NAME);

regards,
Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |




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RE: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Marc,

Thanks for your time & review comments.

> -----Original Message-----
(...)
> > +#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
> > +
> > +#define RCANFD_NUM_CHANNELS		2
> > +#define RCANFD_CHANNELS_MASK		0x3	/* Two channels max */
> 
> (BIT(RCANFD_NUM_CHANNELS) - 1

OK

> 
> > +
> > +/* Rx FIFO is a global resource of the controller. There are 8 such
> FIFOs
> > + * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
(...)
> > +#define RCANFD_CMFIFO_CFDLC(x)		(((x) & 0xf) << 28)
> > +#define RCANFD_CMFIFO_CFPTR(x)		(((x) & 0xfff) << 16)
> > +#define RCANFD_CMFIFO_CFTS(x)		(((x) & 0xff) << 0)
> > +
> > +/* Global Test Config register */
> > +#define RCANFD_GTSTCFG_C0CBCE		BIT(0)
> > +#define RCANFD_GTSTCFG_C1CBCE		BIT(1)
> > +
> > +#define RCANFD_GTSTCTR_ICBCTME		BIT(0)
> > +
> > +/* AFL Rx rules registers */
> > +#define RCANFD_AFLCFG_SETRNC0(x)	(((x) & 0xff) << 24)
> > +#define RCANFD_AFLCFG_SETRNC1(x)	(((x) & 0xff) << 16)
> 
> What about something like:
> 
> #define RCANFD_AFLCFG_SETRNC(n, x)	(((x) & 0xff) << (24 - n * 8))
> 
> This will save some if()s in the code

Nice :-). Will update.

> 
> > +#define RCANFD_AFLCFG_GETRNC0(x)	(((x) >> 24) & 0xff)
> > +#define RCANFD_AFLCFG_GETRNC1(x)	(((x) >> 16) & 0xff)
> > +
> > +#define RCANFD_AFL_PAGENUM(entry)	((entry) / 16)
(...)
> > +#define rcar_canfd_read(priv, offset)			\
> > +	readl(priv->base + (offset))
> > +#define rcar_canfd_write(priv, offset, val)		\
> > +	writel(val, priv->base + (offset))
> > +#define rcar_canfd_set_bit(priv, reg, val)		\
> > +	rcar_canfd_update(val, val, priv->base + (reg))
> > +#define rcar_canfd_clear_bit(priv, reg, val)		\
> > +	rcar_canfd_update(val, 0, priv->base + (reg))
> > +#define rcar_canfd_update_bit(priv, reg, mask, val)	\
> > +	rcar_canfd_update(mask, val, priv->base + (reg))
> 
> please use static inline functions instead of defines.

OK.

> 
> > +
> > +static void rcar_canfd_get_data(struct canfd_frame *cf,
> > +				struct rcar_canfd_channel *priv, u32 off)
> 
> Please use "struct rcar_canfd_channel *priv" as first argument, struct
> canfd_frame *cf as second. Remove off, as the offset is already defined
> by the channel.

I'll re-order priv, cf as you mentioned. I'll leave "off" arg as it is because it is based on FIFO number of channel + mode (CAN only or CANFD only). Otherwise, I will have to add another check inside this function for mode.
 
> > +{
> > +	u32 i, lwords;
> > +
> > +	lwords = cf->len / sizeof(u32);
> > +	if (cf->len % sizeof(u32))
> > +		lwords++;
> 
> Use DIV_ROUND_UP() instead of open coding it.

Agreed. Thanks.

> 
> > +	for (i = 0; i < lwords; i++)
> > +		*((u32 *)cf->data + i) =
> > +			rcar_canfd_read(priv, off + (i * sizeof(u32)));
> > +}
> > +
> > +static void rcar_canfd_put_data(struct canfd_frame *cf,
> > +				struct rcar_canfd_channel *priv, u32 off)
> 
> same here

Yes (same as _get_data)
 
> 
> > +{
> > +	u32 i, j, lwords, leftover;
> > +	u32 data = 0;
> > +
> > +	lwords = cf->len / sizeof(u32);
> > +	leftover = cf->len % sizeof(u32);
> > +	for (i = 0; i < lwords; i++)
> > +		rcar_canfd_write(priv, off + (i * sizeof(u32)),
> > +				 *((u32 *)cf->data + i));
> 
> Here you don't convert the endianess...

Yes

> > +
> > +	if (leftover) {
> > +		u8 *p = (u8 *)((u32 *)cf->data + i);
> > +
> > +		for (j = 0; j < leftover; j++)
> > +			data |= p[j] << (j * 8);
> 
> ...here you do an implicit endianess conversion. "data" is little
> endian, while p[j] is big endian.

Not sure I got the question correctly.
Controller expectation of data bytes in 32bit register is bits[7:0] = byte0, bits[15:8] = byte1 and so on - little endian.
For e.g. if cf->data points to byte stream H'112233445566 (cf->data[0] = 0x11), first rcar_canfd_write will write 0x44332211 value to register. Yes the host cpu is assumed little endian. In leftover case, data will be 0x00006655 - again little endian. 
I think I should remove this leftover logic and just mask the unused bits to zero as cf->data is pre-allocated for max length anyway.

p[j] is a byte?? Am I missing something?

> 
> > +		rcar_canfd_write(priv, off + (i * sizeof(u32)), data);
> > +	}
> 
> Have you tested to send CAN frames with len != n*4 against a different
> controller?

Yes, with Vector VN1630A.

> > +}
> > +
> > +static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
> > +{
> > +	u32 i;
> > +
> > +	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
> > +		can_free_echo_skb(ndev, i);
> > +}
> > +
(...)
> > +static void rcar_canfd_tx_done(struct net_device *ndev)
> > +{
> > +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
> > +	struct net_device_stats *stats = &ndev->stats;
> > +	u32 sts;
> > +	unsigned long flags;
> > +	u32 ch = priv->channel;
> > +
> > +	do {
> 
> You should iterare over all pending CAN frames:
> 
> > 	for (/* nix */; (priv->tx_head - priv->tx_tail) > 0; priv-
> >tx_tail++) {
> 

Yes, current code does iterate over pending tx'ed frames. If we use this for loop semantics, we may have to protect the whole loop with no real benefit. 

> 
> > +		u8 unsent, sent;
> > +
> > +		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
> 
> and check here, if that packet has really been tramsitted. Exit the loop
> otherweise.

We are here because of tx_done and hence no need to check tx done again for the first iteration. Hence the do-while loop. Checks further down takes care of the need for more iterations/pending tx'ed frames.

> 
> > +		stats->tx_packets++;
> > +		stats->tx_bytes += priv->tx_len[sent];
> > +		priv->tx_len[sent] = 0;
> > +		can_get_echo_skb(ndev, sent);
> > +
> > +		spin_lock_irqsave(&priv->tx_lock, flags);
> 
> What does the tx_lock protect? The tx path is per channel, isn't it?

You are right - tx path is per channel. In tx path, head & tail are also used to determine when to stop/wakeup netif queue. They are incremented & compared in different contexts to make this decision. Per channel tx_lock protects this critical section.

> 
> > +		priv->tx_tail++;
> > +		sts = rcar_canfd_read(priv,
> > +				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
> > +		unsent = RCANFD_CMFIFO_CFMC(sts);
> > +
> > +		/* Wake producer only when there is room */
> > +		if (unsent != RCANFD_FIFO_DEPTH)
> > +			netif_wake_queue(ndev);
> 
> Move the netif_wake_queue() out of the loop.

With the tx logic mentioned above, I think keeping it in the loop seems better. For e.g. say cpu1 pumps 8 frames from an app loop and cpu0 handles tx_done interrupt handling: cpu1 would have stopped the queue because FIFO is full -> cpu0 gets tx_done interrupt and by the time it checks "unsent" there could be one or more frames transmitted by device (i.e.) there would be more space in fifo. It is better to wakeup the netif queue then and there so that app running on cpu1 can pump more. If we move it out of the loop we wake up the queue only in the end. Have I missed anything?

> 
> > +
> > +		if (priv->tx_head - priv->tx_tail <= unsent) {
> > +			spin_unlock_irqrestore(&priv->tx_lock, flags);
> > +			break;
> > +		}
> > +		spin_unlock_irqrestore(&priv->tx_lock, flags);
> > +
> > +	} while (1);
> > +
> > +	/* Clear interrupt */
> > +	rcar_canfd_write(priv, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
> > +			 sts & ~RCANFD_CMFIFO_CFTXIF);
> > +	can_led_event(ndev, CAN_LED_EVENT_TX);
> > +}
> > +
> > +	if (cf->can_id & CAN_RTR_FLAG)
> > +		id |= RCANFD_CMFIFO_CFRTR;
> > +
> > +	rcar_canfd_write(priv, RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX),
> > +			 id);
> > +	ptr = RCANFD_CMFIFO_CFDLC(can_len2dlc(cf->len));
> 
> ptr usually means pointer, better call it dlc.

I used the register name "ptr". OK, will change it do dlc.

> 
> > +	rcar_canfd_write(priv, RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX),
> > +			 ptr);
> > +
(...)
> > +	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
> > +
> > +	spin_lock_irqsave(&priv->tx_lock, flags);
> > +	priv->tx_head++;
> > +
> > +	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
> > +	 * pointer for the Common FIFO
> > +	 */
> > +	rcar_canfd_write(priv, RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
> > +
> > +	/* Stop the queue if we've filled all FIFO entries */
> > +	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
> > +		netif_stop_queue(ndev);
> 
> Please move the check of stop_queue, before starting the send.

OK. 

> 
> > +
> > +	spin_unlock_irqrestore(&priv->tx_lock, flags);
> > +	return NETDEV_TX_OK;
> > +}
> > +
(...)
> > +{
> > +	struct rcar_canfd_channel *priv =
> > +		container_of(napi, struct rcar_canfd_channel, napi);
> > +	int num_pkts;
> > +	u32 sts;
> > +	u32 ch = priv->channel;
> > +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
> > +
> > +	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
> > +		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
> > +		/* Clear interrupt bit */
> > +		if (sts & RCANFD_RFFIFO_RFIF)
> > +			rcar_canfd_write(priv, RCANFD_RFSTS(ridx),
> > +					 sts & ~RCANFD_RFFIFO_RFIF);
> > +
> > +		/* Check FIFO empty condition */
> > +		if (sts & RCANFD_RFFIFO_RFEMP)
> > +			break;
> > +
> > +		rcar_canfd_rx_pkt(priv);
> 
> This sequence looks strange. You first conditionally ack the interrupt
> then you check for empty fifo, then read the CAN frame. I would assume
> that you first check if there's a CAN frame, read it and then clear the
> interrupt.

Yes, I shall re-arrange the sequence as you mentioned.
 
> 
> > +	}
> > +
> > +	/* All packets processed */
> > +	if (num_pkts < quota) {
> > +		napi_complete(napi);
> > +		/* Enable Rx FIFO interrupts */
> > +		rcar_canfd_set_bit(priv, RCANFD_RFCC(ridx),
> RCANFD_RFFIFO_RFIE);
(...)
> > +	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
> > +		err = rcar_canfd_channel_probe(gpriv, ch);
> > +		if (err)
> > +			goto fail_channel;
> > +	}
> 
> Should the CAN IP core be clocked the whole time? What about shuting
> down the clock and enabling it on ifup?

The fCAN clock is enabled only on ifup of one of the channels. However, the peripheral clock is enabled during probe to bring the controller to Global Operational mode. This clock cannot be turned off with the register values & mode retained.

> > +
> > +	platform_set_drvdata(pdev, gpriv);
> > +	dev_info(&pdev->dev, "global operational state (clk %d)\n",
> > +		 gpriv->clock_select);
(...)
> > +	rcar_canfd_reset_controller(gpriv);
> > +	rcar_canfd_disable_global_interrupts(gpriv);
> > +
> > +	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
> > +		priv = gpriv->ch[ch];
> > +		if (priv) {
> 
> This should always be true.

I agree. I thought I cleaned this up but it's in my local commits :-(

> 
> > +			rcar_canfd_disable_channel_interrupts(priv);
> > +			unregister_candev(priv->ndev);
> > +			netif_napi_del(&priv->napi);
> > +			free_candev(priv->ndev);
> 
> Please make use of rcar_canfd_channel_remove(), as you already have the
> function.

Yes.

Thanks,
Ramesh

RE: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

HI Marc,

Gentle reminder!
Are you happy with the open comment's disposition? I can send a next version of patch if we have a closure on current set of comments.

Thanks,
Ramesh

> -----Original Message-----
> From: Ramesh Shanmugasundaram
> Sent: 01 April 2016 13:49
> To: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>;
> wg@grandegger.com; robh+dt@kernel.org; pawel.moll@arm.com;
> mark.rutland@arm.com; ijc+devicetree@hellion.org.uk; galak@codeaurora.org;
> corbet@lwn.net
> Cc: linux-renesas-soc@vger.kernel.org; devicetree@vger.kernel.org; linux-
> can@vger.kernel.org; netdev@vger.kernel.org; linux-doc@vger.kernel.org;
> geert+renesas@glider.be; Chris Paterson <Chris.Paterson2@renesas.com>
> Subject: RE: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver
> 
> Hi Marc,
> 
> Thanks for your time & review comments.
> 
> > -----Original Message-----
> (...)
> > > +#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
> > > +
> > > +#define RCANFD_NUM_CHANNELS		2
> > > +#define RCANFD_CHANNELS_MASK		0x3	/* Two channels max */
> >
> > (BIT(RCANFD_NUM_CHANNELS) - 1
> 
> OK
> 
> >
> > > +
> > > +/* Rx FIFO is a global resource of the controller. There are 8 such
> > FIFOs
> > > + * available. Each channel gets a dedicated Rx FIFO (i.e.) the
> > > + channel
> (...)
> > > +#define RCANFD_CMFIFO_CFDLC(x)		(((x) & 0xf) << 28)
> > > +#define RCANFD_CMFIFO_CFPTR(x)		(((x) & 0xfff) << 16)
> > > +#define RCANFD_CMFIFO_CFTS(x)		(((x) & 0xff) << 0)
> > > +
> > > +/* Global Test Config register */
> > > +#define RCANFD_GTSTCFG_C0CBCE		BIT(0)
> > > +#define RCANFD_GTSTCFG_C1CBCE		BIT(1)
> > > +
> > > +#define RCANFD_GTSTCTR_ICBCTME		BIT(0)
> > > +
> > > +/* AFL Rx rules registers */
> > > +#define RCANFD_AFLCFG_SETRNC0(x)	(((x) & 0xff) << 24)
> > > +#define RCANFD_AFLCFG_SETRNC1(x)	(((x) & 0xff) << 16)
> >
> > What about something like:
> >
> > #define RCANFD_AFLCFG_SETRNC(n, x)	(((x) & 0xff) << (24 - n * 8))
> >
> > This will save some if()s in the code
> 
> Nice :-). Will update.
> 
> >
> > > +#define RCANFD_AFLCFG_GETRNC0(x)	(((x) >> 24) & 0xff)
> > > +#define RCANFD_AFLCFG_GETRNC1(x)	(((x) >> 16) & 0xff)
> > > +
> > > +#define RCANFD_AFL_PAGENUM(entry)	((entry) / 16)
> (...)
> > > +#define rcar_canfd_read(priv, offset)			\
> > > +	readl(priv->base + (offset))
> > > +#define rcar_canfd_write(priv, offset, val)		\
> > > +	writel(val, priv->base + (offset))
> > > +#define rcar_canfd_set_bit(priv, reg, val)		\
> > > +	rcar_canfd_update(val, val, priv->base + (reg))
> > > +#define rcar_canfd_clear_bit(priv, reg, val)		\
> > > +	rcar_canfd_update(val, 0, priv->base + (reg))
> > > +#define rcar_canfd_update_bit(priv, reg, mask, val)	\
> > > +	rcar_canfd_update(mask, val, priv->base + (reg))
> >
> > please use static inline functions instead of defines.
> 
> OK.
> 
> >
> > > +
> > > +static void rcar_canfd_get_data(struct canfd_frame *cf,
> > > +				struct rcar_canfd_channel *priv, u32 off)
> >
> > Please use "struct rcar_canfd_channel *priv" as first argument, struct
> > canfd_frame *cf as second. Remove off, as the offset is already
> > defined by the channel.
> 
> I'll re-order priv, cf as you mentioned. I'll leave "off" arg as it is
> because it is based on FIFO number of channel + mode (CAN only or CANFD
> only). Otherwise, I will have to add another check inside this function
> for mode.
> 
> > > +{
> > > +	u32 i, lwords;
> > > +
> > > +	lwords = cf->len / sizeof(u32);
> > > +	if (cf->len % sizeof(u32))
> > > +		lwords++;
> >
> > Use DIV_ROUND_UP() instead of open coding it.
> 
> Agreed. Thanks.
> 
> >
> > > +	for (i = 0; i < lwords; i++)
> > > +		*((u32 *)cf->data + i) =
> > > +			rcar_canfd_read(priv, off + (i * sizeof(u32))); }
> > > +
> > > +static void rcar_canfd_put_data(struct canfd_frame *cf,
> > > +				struct rcar_canfd_channel *priv, u32 off)
> >
> > same here
> 
> Yes (same as _get_data)
> 
> >
> > > +{
> > > +	u32 i, j, lwords, leftover;
> > > +	u32 data = 0;
> > > +
> > > +	lwords = cf->len / sizeof(u32);
> > > +	leftover = cf->len % sizeof(u32);
> > > +	for (i = 0; i < lwords; i++)
> > > +		rcar_canfd_write(priv, off + (i * sizeof(u32)),
> > > +				 *((u32 *)cf->data + i));
> >
> > Here you don't convert the endianess...
> 
> Yes
> 
> > > +
> > > +	if (leftover) {
> > > +		u8 *p = (u8 *)((u32 *)cf->data + i);
> > > +
> > > +		for (j = 0; j < leftover; j++)
> > > +			data |= p[j] << (j * 8);
> >
> > ...here you do an implicit endianess conversion. "data" is little
> > endian, while p[j] is big endian.
> 
> Not sure I got the question correctly.
> Controller expectation of data bytes in 32bit register is bits[7:0] =
> byte0, bits[15:8] = byte1 and so on - little endian.
> For e.g. if cf->data points to byte stream H'112233445566 (cf->data[0] =
> 0x11), first rcar_canfd_write will write 0x44332211 value to register. Yes
> the host cpu is assumed little endian. In leftover case, data will be
> 0x00006655 - again little endian.
> I think I should remove this leftover logic and just mask the unused bits
> to zero as cf->data is pre-allocated for max length anyway.
> 
> p[j] is a byte?? Am I missing something?
> 
> >
> > > +		rcar_canfd_write(priv, off + (i * sizeof(u32)), data);
> > > +	}
> >
> > Have you tested to send CAN frames with len != n*4 against a different
> > controller?
> 
> Yes, with Vector VN1630A.
> 
> > > +}
> > > +
> > > +static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
> > > +{
> > > +	u32 i;
> > > +
> > > +	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
> > > +		can_free_echo_skb(ndev, i);
> > > +}
> > > +
> (...)
> > > +static void rcar_canfd_tx_done(struct net_device *ndev) {
> > > +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
> > > +	struct net_device_stats *stats = &ndev->stats;
> > > +	u32 sts;
> > > +	unsigned long flags;
> > > +	u32 ch = priv->channel;
> > > +
> > > +	do {
> >
> > You should iterare over all pending CAN frames:
> >
> > > 	for (/* nix */; (priv->tx_head - priv->tx_tail) > 0; priv-
> > >tx_tail++) {
> >
> 
> Yes, current code does iterate over pending tx'ed frames. If we use this
> for loop semantics, we may have to protect the whole loop with no real
> benefit.
> 
> >
> > > +		u8 unsent, sent;
> > > +
> > > +		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
> >
> > and check here, if that packet has really been tramsitted. Exit the
> > loop otherweise.
> 
> We are here because of tx_done and hence no need to check tx done again
> for the first iteration. Hence the do-while loop. Checks further down
> takes care of the need for more iterations/pending tx'ed frames.
> 
> >
> > > +		stats->tx_packets++;
> > > +		stats->tx_bytes += priv->tx_len[sent];
> > > +		priv->tx_len[sent] = 0;
> > > +		can_get_echo_skb(ndev, sent);
> > > +
> > > +		spin_lock_irqsave(&priv->tx_lock, flags);
> >
> > What does the tx_lock protect? The tx path is per channel, isn't it?
> 
> You are right - tx path is per channel. In tx path, head & tail are also
> used to determine when to stop/wakeup netif queue. They are incremented &
> compared in different contexts to make this decision. Per channel tx_lock
> protects this critical section.
> 
> >
> > > +		priv->tx_tail++;
> > > +		sts = rcar_canfd_read(priv,
> > > +				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
> > > +		unsent = RCANFD_CMFIFO_CFMC(sts);
> > > +
> > > +		/* Wake producer only when there is room */
> > > +		if (unsent != RCANFD_FIFO_DEPTH)
> > > +			netif_wake_queue(ndev);
> >
> > Move the netif_wake_queue() out of the loop.
> 
> With the tx logic mentioned above, I think keeping it in the loop seems
> better. For e.g. say cpu1 pumps 8 frames from an app loop and cpu0 handles
> tx_done interrupt handling: cpu1 would have stopped the queue because FIFO
> is full -> cpu0 gets tx_done interrupt and by the time it checks "unsent"
> there could be one or more frames transmitted by device (i.e.) there would
> be more space in fifo. It is better to wakeup the netif queue then and
> there so that app running on cpu1 can pump more. If we move it out of the
> loop we wake up the queue only in the end. Have I missed anything?
> 
> >
> > > +
> > > +		if (priv->tx_head - priv->tx_tail <= unsent) {
> > > +			spin_unlock_irqrestore(&priv->tx_lock, flags);
> > > +			break;
> > > +		}
> > > +		spin_unlock_irqrestore(&priv->tx_lock, flags);
> > > +
> > > +	} while (1);
> > > +
> > > +	/* Clear interrupt */
> > > +	rcar_canfd_write(priv, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
> > > +			 sts & ~RCANFD_CMFIFO_CFTXIF);
> > > +	can_led_event(ndev, CAN_LED_EVENT_TX); }
> > > +
> > > +	if (cf->can_id & CAN_RTR_FLAG)
> > > +		id |= RCANFD_CMFIFO_CFRTR;
> > > +
> > > +	rcar_canfd_write(priv, RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX),
> > > +			 id);
> > > +	ptr = RCANFD_CMFIFO_CFDLC(can_len2dlc(cf->len));
> >
> > ptr usually means pointer, better call it dlc.
> 
> I used the register name "ptr". OK, will change it do dlc.
> 
> >
> > > +	rcar_canfd_write(priv, RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX),
> > > +			 ptr);
> > > +
> (...)
> > > +	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
> > > +
> > > +	spin_lock_irqsave(&priv->tx_lock, flags);
> > > +	priv->tx_head++;
> > > +
> > > +	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
> > > +	 * pointer for the Common FIFO
> > > +	 */
> > > +	rcar_canfd_write(priv, RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX),
> > > +0xff);
> > > +
> > > +	/* Stop the queue if we've filled all FIFO entries */
> > > +	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
> > > +		netif_stop_queue(ndev);
> >
> > Please move the check of stop_queue, before starting the send.
> 
> OK.
> 
> >
> > > +
> > > +	spin_unlock_irqrestore(&priv->tx_lock, flags);
> > > +	return NETDEV_TX_OK;
> > > +}
> > > +
> (...)
> > > +{
> > > +	struct rcar_canfd_channel *priv =
> > > +		container_of(napi, struct rcar_canfd_channel, napi);
> > > +	int num_pkts;
> > > +	u32 sts;
> > > +	u32 ch = priv->channel;
> > > +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
> > > +
> > > +	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
> > > +		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
> > > +		/* Clear interrupt bit */
> > > +		if (sts & RCANFD_RFFIFO_RFIF)
> > > +			rcar_canfd_write(priv, RCANFD_RFSTS(ridx),
> > > +					 sts & ~RCANFD_RFFIFO_RFIF);
> > > +
> > > +		/* Check FIFO empty condition */
> > > +		if (sts & RCANFD_RFFIFO_RFEMP)
> > > +			break;
> > > +
> > > +		rcar_canfd_rx_pkt(priv);
> >
> > This sequence looks strange. You first conditionally ack the interrupt
> > then you check for empty fifo, then read the CAN frame. I would assume
> > that you first check if there's a CAN frame, read it and then clear
> > the interrupt.
> 
> Yes, I shall re-arrange the sequence as you mentioned.
> 
> >
> > > +	}
> > > +
> > > +	/* All packets processed */
> > > +	if (num_pkts < quota) {
> > > +		napi_complete(napi);
> > > +		/* Enable Rx FIFO interrupts */
> > > +		rcar_canfd_set_bit(priv, RCANFD_RFCC(ridx),
> > RCANFD_RFFIFO_RFIE);
> (...)
> > > +	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
> > > +		err = rcar_canfd_channel_probe(gpriv, ch);
> > > +		if (err)
> > > +			goto fail_channel;
> > > +	}
> >
> > Should the CAN IP core be clocked the whole time? What about shuting
> > down the clock and enabling it on ifup?
> 
> The fCAN clock is enabled only on ifup of one of the channels. However,
> the peripheral clock is enabled during probe to bring the controller to
> Global Operational mode. This clock cannot be turned off with the register
> values & mode retained.
> 
> > > +
> > > +	platform_set_drvdata(pdev, gpriv);
> > > +	dev_info(&pdev->dev, "global operational state (clk %d)\n",
> > > +		 gpriv->clock_select);
> (...)
> > > +	rcar_canfd_reset_controller(gpriv);
> > > +	rcar_canfd_disable_global_interrupts(gpriv);
> > > +
> > > +	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
> > > +		priv = gpriv->ch[ch];
> > > +		if (priv) {
> >
> > This should always be true.
> 
> I agree. I thought I cleaned this up but it's in my local commits :-(
> 
> >
> > > +			rcar_canfd_disable_channel_interrupts(priv);
> > > +			unregister_candev(priv->ndev);
> > > +			netif_napi_del(&priv->napi);
> > > +			free_candev(priv->ndev);
> >
> > Please make use of rcar_canfd_channel_remove(), as you already have
> > the function.
> 
> Yes.
> 
> Thanks,
> Ramesh

Re: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Oliver Hartkopp]

Hello Ramesh,

please send out a new v3 patchset to trigger the process again :-)

Best regards,
Oliver

On 04/13/2016 08:25 AM, Ramesh Shanmugasundaram wrote:
> HI Marc,
>
> Gentle reminder!
> Are you happy with the open comment's disposition? I can send a next version of patch if we have a closure on current set of comments.
>
> Thanks,
> Ramesh
>
>> -----Original Message-----
>> From: Ramesh Shanmugasundaram
>> Sent: 01 April 2016 13:49
>> To: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>;
>> wg@grandegger.com; robh+dt@kernel.org; pawel.moll@arm.com;
>> mark.rutland@arm.com; ijc+devicetree@hellion.org.uk; galak@codeaurora.org;
>> corbet@lwn.net
>> Cc: linux-renesas-soc@vger.kernel.org; devicetree@vger.kernel.org; linux-
>> can@vger.kernel.org; netdev@vger.kernel.org; linux-doc@vger.kernel.org;
>> geert+renesas@glider.be; Chris Paterson <Chris.Paterson2@renesas.com>
>> Subject: RE: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver
>>
>> Hi Marc,
>>
>> Thanks for your time & review comments.
>>
>>> -----Original Message-----
>> (...)
>>>> +#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
>>>> +
>>>> +#define RCANFD_NUM_CHANNELS		2
>>>> +#define RCANFD_CHANNELS_MASK		0x3	/* Two channels max */
>>>
>>> (BIT(RCANFD_NUM_CHANNELS) - 1
>>
>> OK
>>
>>>
>>>> +
>>>> +/* Rx FIFO is a global resource of the controller. There are 8 such
>>> FIFOs
>>>> + * available. Each channel gets a dedicated Rx FIFO (i.e.) the
>>>> + channel
>> (...)
>>>> +#define RCANFD_CMFIFO_CFDLC(x)		(((x) & 0xf) << 28)
>>>> +#define RCANFD_CMFIFO_CFPTR(x)		(((x) & 0xfff) << 16)
>>>> +#define RCANFD_CMFIFO_CFTS(x)		(((x) & 0xff) << 0)
>>>> +
>>>> +/* Global Test Config register */
>>>> +#define RCANFD_GTSTCFG_C0CBCE		BIT(0)
>>>> +#define RCANFD_GTSTCFG_C1CBCE		BIT(1)
>>>> +
>>>> +#define RCANFD_GTSTCTR_ICBCTME		BIT(0)
>>>> +
>>>> +/* AFL Rx rules registers */
>>>> +#define RCANFD_AFLCFG_SETRNC0(x)	(((x) & 0xff) << 24)
>>>> +#define RCANFD_AFLCFG_SETRNC1(x)	(((x) & 0xff) << 16)
>>>
>>> What about something like:
>>>
>>> #define RCANFD_AFLCFG_SETRNC(n, x)	(((x) & 0xff) << (24 - n * 8))
>>>
>>> This will save some if()s in the code
>>
>> Nice :-). Will update.
>>
>>>
>>>> +#define RCANFD_AFLCFG_GETRNC0(x)	(((x) >> 24) & 0xff)
>>>> +#define RCANFD_AFLCFG_GETRNC1(x)	(((x) >> 16) & 0xff)
>>>> +
>>>> +#define RCANFD_AFL_PAGENUM(entry)	((entry) / 16)
>> (...)
>>>> +#define rcar_canfd_read(priv, offset)			\
>>>> +	readl(priv->base + (offset))
>>>> +#define rcar_canfd_write(priv, offset, val)		\
>>>> +	writel(val, priv->base + (offset))
>>>> +#define rcar_canfd_set_bit(priv, reg, val)		\
>>>> +	rcar_canfd_update(val, val, priv->base + (reg))
>>>> +#define rcar_canfd_clear_bit(priv, reg, val)		\
>>>> +	rcar_canfd_update(val, 0, priv->base + (reg))
>>>> +#define rcar_canfd_update_bit(priv, reg, mask, val)	\
>>>> +	rcar_canfd_update(mask, val, priv->base + (reg))
>>>
>>> please use static inline functions instead of defines.
>>
>> OK.
>>
>>>
>>>> +
>>>> +static void rcar_canfd_get_data(struct canfd_frame *cf,
>>>> +				struct rcar_canfd_channel *priv, u32 off)
>>>
>>> Please use "struct rcar_canfd_channel *priv" as first argument, struct
>>> canfd_frame *cf as second. Remove off, as the offset is already
>>> defined by the channel.
>>
>> I'll re-order priv, cf as you mentioned. I'll leave "off" arg as it is
>> because it is based on FIFO number of channel + mode (CAN only or CANFD
>> only). Otherwise, I will have to add another check inside this function
>> for mode.
>>
>>>> +{
>>>> +	u32 i, lwords;
>>>> +
>>>> +	lwords = cf->len / sizeof(u32);
>>>> +	if (cf->len % sizeof(u32))
>>>> +		lwords++;
>>>
>>> Use DIV_ROUND_UP() instead of open coding it.
>>
>> Agreed. Thanks.
>>
>>>
>>>> +	for (i = 0; i < lwords; i++)
>>>> +		*((u32 *)cf->data + i) =
>>>> +			rcar_canfd_read(priv, off + (i * sizeof(u32))); }
>>>> +
>>>> +static void rcar_canfd_put_data(struct canfd_frame *cf,
>>>> +				struct rcar_canfd_channel *priv, u32 off)
>>>
>>> same here
>>
>> Yes (same as _get_data)
>>
>>>
>>>> +{
>>>> +	u32 i, j, lwords, leftover;
>>>> +	u32 data = 0;
>>>> +
>>>> +	lwords = cf->len / sizeof(u32);
>>>> +	leftover = cf->len % sizeof(u32);
>>>> +	for (i = 0; i < lwords; i++)
>>>> +		rcar_canfd_write(priv, off + (i * sizeof(u32)),
>>>> +				 *((u32 *)cf->data + i));
>>>
>>> Here you don't convert the endianess...
>>
>> Yes
>>
>>>> +
>>>> +	if (leftover) {
>>>> +		u8 *p = (u8 *)((u32 *)cf->data + i);
>>>> +
>>>> +		for (j = 0; j < leftover; j++)
>>>> +			data |= p[j] << (j * 8);
>>>
>>> ...here you do an implicit endianess conversion. "data" is little
>>> endian, while p[j] is big endian.
>>
>> Not sure I got the question correctly.
>> Controller expectation of data bytes in 32bit register is bits[7:0] =
>> byte0, bits[15:8] = byte1 and so on - little endian.
>> For e.g. if cf->data points to byte stream H'112233445566 (cf->data[0] =
>> 0x11), first rcar_canfd_write will write 0x44332211 value to register. Yes
>> the host cpu is assumed little endian. In leftover case, data will be
>> 0x00006655 - again little endian.
>> I think I should remove this leftover logic and just mask the unused bits
>> to zero as cf->data is pre-allocated for max length anyway.
>>
>> p[j] is a byte?? Am I missing something?
>>
>>>
>>>> +		rcar_canfd_write(priv, off + (i * sizeof(u32)), data);
>>>> +	}
>>>
>>> Have you tested to send CAN frames with len != n*4 against a different
>>> controller?
>>
>> Yes, with Vector VN1630A.
>>
>>>> +}
>>>> +
>>>> +static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
>>>> +{
>>>> +	u32 i;
>>>> +
>>>> +	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
>>>> +		can_free_echo_skb(ndev, i);
>>>> +}
>>>> +
>> (...)
>>>> +static void rcar_canfd_tx_done(struct net_device *ndev) {
>>>> +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
>>>> +	struct net_device_stats *stats = &ndev->stats;
>>>> +	u32 sts;
>>>> +	unsigned long flags;
>>>> +	u32 ch = priv->channel;
>>>> +
>>>> +	do {
>>>
>>> You should iterare over all pending CAN frames:
>>>
>>>> 	for (/* nix */; (priv->tx_head - priv->tx_tail) > 0; priv-
>>>> tx_tail++) {
>>>
>>
>> Yes, current code does iterate over pending tx'ed frames. If we use this
>> for loop semantics, we may have to protect the whole loop with no real
>> benefit.
>>
>>>
>>>> +		u8 unsent, sent;
>>>> +
>>>> +		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
>>>
>>> and check here, if that packet has really been tramsitted. Exit the
>>> loop otherweise.
>>
>> We are here because of tx_done and hence no need to check tx done again
>> for the first iteration. Hence the do-while loop. Checks further down
>> takes care of the need for more iterations/pending tx'ed frames.
>>
>>>
>>>> +		stats->tx_packets++;
>>>> +		stats->tx_bytes += priv->tx_len[sent];
>>>> +		priv->tx_len[sent] = 0;
>>>> +		can_get_echo_skb(ndev, sent);
>>>> +
>>>> +		spin_lock_irqsave(&priv->tx_lock, flags);
>>>
>>> What does the tx_lock protect? The tx path is per channel, isn't it?
>>
>> You are right - tx path is per channel. In tx path, head & tail are also
>> used to determine when to stop/wakeup netif queue. They are incremented &
>> compared in different contexts to make this decision. Per channel tx_lock
>> protects this critical section.
>>
>>>
>>>> +		priv->tx_tail++;
>>>> +		sts = rcar_canfd_read(priv,
>>>> +				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
>>>> +		unsent = RCANFD_CMFIFO_CFMC(sts);
>>>> +
>>>> +		/* Wake producer only when there is room */
>>>> +		if (unsent != RCANFD_FIFO_DEPTH)
>>>> +			netif_wake_queue(ndev);
>>>
>>> Move the netif_wake_queue() out of the loop.
>>
>> With the tx logic mentioned above, I think keeping it in the loop seems
>> better. For e.g. say cpu1 pumps 8 frames from an app loop and cpu0 handles
>> tx_done interrupt handling: cpu1 would have stopped the queue because FIFO
>> is full -> cpu0 gets tx_done interrupt and by the time it checks "unsent"
>> there could be one or more frames transmitted by device (i.e.) there would
>> be more space in fifo. It is better to wakeup the netif queue then and
>> there so that app running on cpu1 can pump more. If we move it out of the
>> loop we wake up the queue only in the end. Have I missed anything?
>>
>>>
>>>> +
>>>> +		if (priv->tx_head - priv->tx_tail <= unsent) {
>>>> +			spin_unlock_irqrestore(&priv->tx_lock, flags);
>>>> +			break;
>>>> +		}
>>>> +		spin_unlock_irqrestore(&priv->tx_lock, flags);
>>>> +
>>>> +	} while (1);
>>>> +
>>>> +	/* Clear interrupt */
>>>> +	rcar_canfd_write(priv, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
>>>> +			 sts & ~RCANFD_CMFIFO_CFTXIF);
>>>> +	can_led_event(ndev, CAN_LED_EVENT_TX); }
>>>> +
>>>> +	if (cf->can_id & CAN_RTR_FLAG)
>>>> +		id |= RCANFD_CMFIFO_CFRTR;
>>>> +
>>>> +	rcar_canfd_write(priv, RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX),
>>>> +			 id);
>>>> +	ptr = RCANFD_CMFIFO_CFDLC(can_len2dlc(cf->len));
>>>
>>> ptr usually means pointer, better call it dlc.
>>
>> I used the register name "ptr". OK, will change it do dlc.
>>
>>>
>>>> +	rcar_canfd_write(priv, RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX),
>>>> +			 ptr);
>>>> +
>> (...)
>>>> +	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
>>>> +
>>>> +	spin_lock_irqsave(&priv->tx_lock, flags);
>>>> +	priv->tx_head++;
>>>> +
>>>> +	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
>>>> +	 * pointer for the Common FIFO
>>>> +	 */
>>>> +	rcar_canfd_write(priv, RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX),
>>>> +0xff);
>>>> +
>>>> +	/* Stop the queue if we've filled all FIFO entries */
>>>> +	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
>>>> +		netif_stop_queue(ndev);
>>>
>>> Please move the check of stop_queue, before starting the send.
>>
>> OK.
>>
>>>
>>>> +
>>>> +	spin_unlock_irqrestore(&priv->tx_lock, flags);
>>>> +	return NETDEV_TX_OK;
>>>> +}
>>>> +
>> (...)
>>>> +{
>>>> +	struct rcar_canfd_channel *priv =
>>>> +		container_of(napi, struct rcar_canfd_channel, napi);
>>>> +	int num_pkts;
>>>> +	u32 sts;
>>>> +	u32 ch = priv->channel;
>>>> +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
>>>> +
>>>> +	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
>>>> +		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
>>>> +		/* Clear interrupt bit */
>>>> +		if (sts & RCANFD_RFFIFO_RFIF)
>>>> +			rcar_canfd_write(priv, RCANFD_RFSTS(ridx),
>>>> +					 sts & ~RCANFD_RFFIFO_RFIF);
>>>> +
>>>> +		/* Check FIFO empty condition */
>>>> +		if (sts & RCANFD_RFFIFO_RFEMP)
>>>> +			break;
>>>> +
>>>> +		rcar_canfd_rx_pkt(priv);
>>>
>>> This sequence looks strange. You first conditionally ack the interrupt
>>> then you check for empty fifo, then read the CAN frame. I would assume
>>> that you first check if there's a CAN frame, read it and then clear
>>> the interrupt.
>>
>> Yes, I shall re-arrange the sequence as you mentioned.
>>
>>>
>>>> +	}
>>>> +
>>>> +	/* All packets processed */
>>>> +	if (num_pkts < quota) {
>>>> +		napi_complete(napi);
>>>> +		/* Enable Rx FIFO interrupts */
>>>> +		rcar_canfd_set_bit(priv, RCANFD_RFCC(ridx),
>>> RCANFD_RFFIFO_RFIE);
>> (...)
>>>> +	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
>>>> +		err = rcar_canfd_channel_probe(gpriv, ch);
>>>> +		if (err)
>>>> +			goto fail_channel;
>>>> +	}
>>>
>>> Should the CAN IP core be clocked the whole time? What about shuting
>>> down the clock and enabling it on ifup?
>>
>> The fCAN clock is enabled only on ifup of one of the channels. However,
>> the peripheral clock is enabled during probe to bring the controller to
>> Global Operational mode. This clock cannot be turned off with the register
>> values & mode retained.
>>
>>>> +
>>>> +	platform_set_drvdata(pdev, gpriv);
>>>> +	dev_info(&pdev->dev, "global operational state (clk %d)\n",
>>>> +		 gpriv->clock_select);
>> (...)
>>>> +	rcar_canfd_reset_controller(gpriv);
>>>> +	rcar_canfd_disable_global_interrupts(gpriv);
>>>> +
>>>> +	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
>>>> +		priv = gpriv->ch[ch];
>>>> +		if (priv) {
>>>
>>> This should always be true.
>>
>> I agree. I thought I cleaned this up but it's in my local commits :-(
>>
>>>
>>>> +			rcar_canfd_disable_channel_interrupts(priv);
>>>> +			unregister_candev(priv->ndev);
>>>> +			netif_napi_del(&priv->napi);
>>>> +			free_candev(priv->ndev);
>>>
>>> Please make use of rcar_canfd_channel_remove(), as you already have
>>> the function.
>>
>> Yes.
>>
>> Thanks,
>> Ramesh

[PATCH v5 0/2] Add CAN FD driver support to r8a7795 SoC

[Ramesh Shanmugasundaram]

Hi All,

   This patch is based on commit "885cc17abad6" of can-next/testing branch

Changes since v4:
	* Rebased to latest can-next/testing branch
	* Addressed Marc K review comments on v2 patch
	* Use clk_get_rate() to find ext clock availability. Refer thread
	(https://lkml.org/lkml/2016/4/8/203)

Changes since v3:
	* Split v3 patch into two (Marc K)
	  (1) Introduce rcar_canfd.c driver in drivers/net/can/rcar dir
	  (2) Move rcar_can.c driver to new drivers/net/can/rcar dir
	* Added Acked-by Rob H for the bindings
	* Added comments on CAN FD only mode in driver & Kconfig (Oliver H)

Changes since v2:
	* Rebased to latest tag (linux-can-next-for-4.6-20160310)
	* Cleaned up leftover debugfs code (Thanks Oliver H)
	* Revised devicetree documentation text (as suggested by Rob H)
	  (https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg01597.html)
	* Used new can subsystem api to set static configuration & removed check in rcar_canfd_start (as suggested by Oliver H)
	  (Refer: http://comments.gmane.org/gmane.linux.can/9126 &
	   https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg01867.html)
	* Clubbed Renesas controller drivers to driver/net/can/rcar dir (as suggested by Oliver H)
	* Updated commit message

Changes since v1:
	* Removed testmodes & debugfs code (suggested by Oliver H)
	* Fixed tx path race issue by introducing lock (suggested by Marc K)
	* Removed __maybe_unused attribute of rcar_canfd_of_table

Ramesh Shanmugasundaram (2):
  can: rcar_canfd: Add Renesas R-Car CAN FD driver
  can: rcar_can: Move Renesas CAN driver to rcar dir

 .../devicetree/bindings/net/can/rcar_canfd.txt     |   89 ++
 drivers/net/can/Kconfig                            |   11 +-
 drivers/net/can/Makefile                           |    2 +-
 drivers/net/can/rcar/Kconfig                       |   21 +
 drivers/net/can/rcar/Makefile                      |    6 +
 drivers/net/can/{ => rcar}/rcar_can.c              |    0
 drivers/net/can/rcar/rcar_canfd.c                  | 1624 ++++++++++++++++++++
 7 files changed, 1742 insertions(+), 11 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
 create mode 100644 drivers/net/can/rcar/Kconfig
 create mode 100644 drivers/net/can/rcar/Makefile
 rename drivers/net/can/{ => rcar}/rcar_can.c (100%)
 create mode 100644 drivers/net/can/rcar/rcar_canfd.c

-- 
1.9.1

[PATCH v5 1/2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

This patch adds support for the CAN FD controller found in Renesas R-Car
SoCs. The controller operates in CAN FD only mode by default.

CAN FD mode supports both Classical CAN & CAN FD frame formats. The
controller supports ISO 11898-1:2015 CAN FD format only.

This controller supports two channels and the driver can enable either
or both of the channels.

Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs (one
per channel) for transmission. Rx filter rules are configured to the
minimum (one per channel) and it accepts Standard, Extended, Data &
Remote Frame combinations.

Note: There are few documentation errors in R-Car Gen3 Hardware User
Manual v0.5E with respect to CAN FD controller. They are listed below:

1. CAN FD interrupt numbers 29 & 30 are listed as per channel
interrupts. However, they are common to both channels (i.e.) they are
global and channel interrupts respectively.

2. CANFD clock is derived from PLL1. This is not documented.

3. CANFD clock is further divided by (1/2) within the CAN FD controller.
This is not documented.

4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
is specified 4 Tq in the manual.

5. The maximum number of message RAM area the controller can use is 3584
bytes. It is specified 10752 bytes in the manual.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
---
 .../devicetree/bindings/net/can/rcar_canfd.txt     |   89 ++
 drivers/net/can/Kconfig                            |    1 +
 drivers/net/can/Makefile                           |    1 +
 drivers/net/can/rcar/Kconfig                       |   11 +
 drivers/net/can/rcar/Makefile                      |    5 +
 drivers/net/can/rcar/rcar_canfd.c                  | 1624 ++++++++++++++++++++
 6 files changed, 1731 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
 create mode 100644 drivers/net/can/rcar/Kconfig
 create mode 100644 drivers/net/can/rcar/Makefile
 create mode 100644 drivers/net/can/rcar/rcar_canfd.c

diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
new file mode 100644
index 0000000..d45182b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
@@ -0,0 +1,89 @@
+Renesas R-Car CAN FD controller Device Tree Bindings
+----------------------------------------------------
+
+Required properties:
+- compatible: Must contain one or more of the following:
+  - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
+  - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
+
+  When compatible with the generic version, nodes must list the
+  SoC-specific version corresponding to the platform first, followed by the
+  family-specific and/or generic versions.
+
+- reg: physical base address and size of the R-Car CAN FD register map.
+- interrupts: interrupt specifier for the Global & Channel interrupts
+- clocks: phandles and clock specifiers for 3 clock inputs.
+- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
+- pinctrl-0: pin control group to be used for this controller.
+- pinctrl-names: must be "default".
+
+Required child nodes:
+The controller supports two channels and each is represented as a child node.
+The name of the child nodes are "channel0" and "channel1" respectively. Each
+child node supports the "status" property only, which is used to
+enable/disable the respective channel.
+
+Required properties for "renesas,r8a7795-canfd" compatible:
+In R8A7795 SoC, canfd clock is a div6 clock and can be used by both CAN
+and CAN FD controller at the same time. It needs to be scaled to maximum
+frequency if any of these controllers use it. This is done using the
+below properties.
+
+- assigned-clocks: phandle of canfd clock.
+- assigned-clock-rates: maximum frequency of this clock.
+
+Example
+-------
+
+SoC common .dtsi file:
+
+		canfd: can@e66c0000 {
+			compatible = "renesas,r8a7795-canfd",
+				     "renesas,rcar-gen3-canfd";
+			reg = <0 0xe66c0000 0 0x8000>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 914>,
+			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
+			       <&can_clk>;
+			clock-names = "fck", "canfd", "can_clk";
+			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
+			assigned-clock-rates = <40000000>;
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			channel0 {
+				status = "disabled";
+			};
+
+			channel1 {
+				status = "disabled";
+			};
+		};
+
+Board specific .dts file:
+
+E.g. below enables Channel 1 alone in the board.
+
+&canfd {
+        pinctrl-0 = <&canfd1_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+	channel1 {
+		status = "okay";
+	};
+};
+
+E.g. below enables Channel 0 alone in the board using External clock
+as fCAN clock.
+
+&canfd {
+        pinctrl-0 = <&canfd0_pins &can_clk_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+	channel0 {
+		status = "okay";
+	};
+};
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 0d40aef..13003a9 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -152,6 +152,7 @@ source "drivers/net/can/cc770/Kconfig"
 source "drivers/net/can/ifi_canfd/Kconfig"
 source "drivers/net/can/m_can/Kconfig"
 source "drivers/net/can/mscan/Kconfig"
+source "drivers/net/can/rcar/Kconfig"
 source "drivers/net/can/sja1000/Kconfig"
 source "drivers/net/can/softing/Kconfig"
 source "drivers/net/can/spi/Kconfig"
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index e3db0c8..226d5b5 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -10,6 +10,7 @@ can-dev-y			:= dev.o
 
 can-dev-$(CONFIG_CAN_LEDS)	+= led.o
 
+obj-y				+= rcar/
 obj-y				+= spi/
 obj-y				+= usb/
 obj-y				+= softing/
diff --git a/drivers/net/can/rcar/Kconfig b/drivers/net/can/rcar/Kconfig
new file mode 100644
index 0000000..6ea64d1
--- /dev/null
+++ b/drivers/net/can/rcar/Kconfig
@@ -0,0 +1,11 @@
+config CAN_RCAR_CANFD
+	tristate "Renesas R-Car CAN FD controller"
+	depends on ARCH_RENESAS || ARM
+	---help---
+	  Say Y here if you want to use CAN FD controller found on
+	  Renesas R-Car SoCs. The driver puts the controller in CAN FD only
+	  mode, which can interoperate with CAN2.0 nodes but does not support
+	  dedicated CAN 2.0 mode.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called rcar_canfd.
diff --git a/drivers/net/can/rcar/Makefile b/drivers/net/can/rcar/Makefile
new file mode 100644
index 0000000..cbaf498e
--- /dev/null
+++ b/drivers/net/can/rcar/Makefile
@@ -0,0 +1,5 @@
+#
+#  Makefile for the Renesas R-Car CAN FD controller driver
+#
+
+obj-$(CONFIG_CAN_RCAR_CANFD)	+= rcar_canfd.o
diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
new file mode 100644
index 0000000..e198732
--- /dev/null
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -0,0 +1,1624 @@
+/* Renesas R-Car CAN FD device driver
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/* The R-Car CAN FD controller can operate in either one of the below two modes
+ *  - CAN FD only mode
+ *  - Classical CAN (CAN 2.0) only mode
+ *
+ * This driver puts the controller in CAN FD only mode by default. In this
+ * mode, the controller acts as a CAN FD node that can also interoperate with
+ * CAN 2.0 nodes.
+ *
+ * As of now, this driver does not support the Classical CAN (CAN 2.0) mode,
+ * which is handled by a different register map compared to CAN FD only mode.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/netdevice.h>
+#include <linux/platform_device.h>
+#include <linux/can/led.h>
+#include <linux/can/dev.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+
+#define RCANFD_DRV_NAME			"rcar_canfd"
+
+#define RCANFD_FIFO_DEPTH		8	/* Tx FIFO depth */
+#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
+
+#define RCANFD_NUM_CHANNELS		2	/* Two channels max */
+#define RCANFD_CHANNELS_MASK		BIT((RCANFD_NUM_CHANNELS) - 1)
+
+/* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
+ * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
+ * number is added to RFFIFO index.
+ */
+#define RCANFD_RFFIFO_IDX		0
+
+/* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
+ * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
+ */
+#define RCANFD_CFFIFO_IDX		0
+
+/* Global register bits */
+#define RCANFD_GINTF_CANFD		BIT(0)
+
+#define RCANFD_GCFG_TPRI		BIT(0)
+#define RCANFD_GCFG_DCE			BIT(1)
+#define RCANFD_GCFG_DCS			BIT(4)
+#define RCANFD_GCFG_CMPOC		BIT(5)
+#define RCANFD_GCFG_EEFE		BIT(6)
+
+#define RCANFD_GCTR_SLPR		BIT(2)
+#define RCANFD_GCTR_MODEMASK		(0x3)
+#define RCANFD_GCTR_GOPM		(0x0)
+#define RCANFD_GCTR_GRESET		(0x1)
+#define RCANFD_GCTR_GHLT		(0x2)
+
+#define RCANFD_GCTR_DEIE		BIT(8)
+#define RCANFD_GCTR_MEIE		BIT(9)
+#define RCANFD_GCTR_THLEIE		BIT(10)
+#define RCANFD_GCTR_CFMPOFIE		BIT(11)
+#define RCANFD_GCTR_TSRST		BIT(16)
+
+#define RCANFD_GSTS_RAMINIT		BIT(3)
+#define RCANFD_GSTS_SLP			BIT(2)
+#define RCANFD_GSTS_HLT			BIT(1)
+#define RCANFD_GSTS_RESET		BIT(0)
+
+#define RCANFD_GSTS_GNOPM		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+/* Channel register bits */
+#define RCANFD_CCTR_CSLPR		BIT(2)
+#define RCANFD_CCTR_MODEMASK		(0x3)
+#define RCANFD_CCTR_COPM		(0x0)
+#define RCANFD_CCTR_CRESET		(0x1)
+#define RCANFD_CCTR_CHLT		(0x2)
+#define RCANFD_CCTR_CTMASK		(0x3 << 25)
+#define RCANFD_CCTR_CTMS_ILB		(0x3 << 25)
+#define RCANFD_CCTR_CTME		BIT(24)
+#define RCANFD_CCTR_ERRD		BIT(23)
+#define RCANFD_CCTR_BOMMASK		(0x3 << 21)
+#define RCANFD_CCTR_BOM_ENTRY		(0x1 << 21)
+#define RCANFD_CCTR_TDCVFIE		BIT(19)
+#define RCANFD_CCTR_SOCOIE		BIT(18)
+#define RCANFD_CCTR_EOCOIE		BIT(17)
+#define RCANFD_CCTR_TAIE		BIT(16)
+#define RCANFD_CCTR_ALIE		BIT(15)
+#define RCANFD_CCTR_BLIE		BIT(14)
+#define RCANFD_CCTR_OLIE		BIT(13)
+#define RCANFD_CCTR_BORIE		BIT(12)
+#define RCANFD_CCTR_BOEIE		BIT(11)
+#define RCANFD_CCTR_EPIE		BIT(10)
+#define RCANFD_CCTR_EWIE		BIT(9)
+#define RCANFD_CCTR_BEIE		BIT(8)
+
+#define RCANFD_CSTS_COM			BIT(7)
+#define RCANFD_CSTS_REC			BIT(6)
+#define RCANFD_CSTS_TRM			BIT(5)
+#define RCANFD_CSTS_BO			BIT(4)
+#define RCANFD_CSTS_EP			BIT(3)
+#define RCANFD_CSTS_SLP			BIT(2)
+#define RCANFD_CSTS_HALT		BIT(1)
+#define RCANFD_CSTS_RESET		BIT(0)
+
+#define RCANFD_CSTS_TECCNT(x)		(((x) >> 24) & 0xff)
+#define RCANFD_CSTS_RECCNT(x)		(((x) >> 16) & 0xff)
+
+/* Bit Configuration register */
+#define RCANFD_BRP(x)			(((x) & 0x3ff) << 0)
+#define RCANFD_SJW(x)			(((x) & 0x3) << 24)
+#define RCANFD_TSEG1(x)			(((x) & 0xf) << 16)
+#define RCANFD_TSEG2(x)			(((x) & 0x7) << 20)
+
+#define RCANFD_NR_BRP(x)		(((x) & 0x3ff) << 0)
+#define RCANFD_NR_SJW(x)		(((x) & 0x1f) << 11)
+#define RCANFD_NR_TSEG1(x)		(((x) & 0x7f) << 16)
+#define RCANFD_NR_TSEG2(x)		(((x) & 0x1f) << 24)
+
+#define RCANFD_DR_BRP(x)		(((x) & 0xff) << 0)
+#define RCANFD_DR_SJW(x)		(((x) & 0x7) << 24)
+#define RCANFD_DR_TSEG1(x)		(((x) & 0xf) << 16)
+#define RCANFD_DR_TSEG2(x)		(((x) & 0x7) << 20)
+
+/* Global Error flag bits */
+#define RCANFD_GERFL_EEF1		BIT(17)
+#define RCANFD_GERFL_EEF0		BIT(16)
+#define RCANFD_GERFL_CMPOF		BIT(3)
+#define RCANFD_GERFL_THLES		BIT(2)
+#define RCANFD_GERFL_MES		BIT(1)
+#define RCANFD_GERFL_DEF		BIT(0)
+
+#define RCANFD_GERFL_ERR(x)		((x) & (RCANFD_GERFL_EEF1 |\
+						RCANFD_GERFL_EEF0 |\
+						RCANFD_GERFL_MES |\
+						RCANFD_GERFL_CMPOF))
+
+/* Channel Error flag bits */
+#define RCANFD_CERFL_ADEF		BIT(14)
+#define RCANFD_CERFL_B0EF		BIT(13)
+#define RCANFD_CERFL_B1EF		BIT(12)
+#define RCANFD_CERFL_CEF		BIT(11)
+#define RCANFD_CERFL_AEF		BIT(10)
+#define RCANFD_CERFL_FEF		BIT(9)
+#define RCANFD_CERFL_SEF		BIT(8)
+#define RCANFD_CERFL_ALEF		BIT(7)
+#define RCANFD_CERFL_BLEF		BIT(6)
+#define RCANFD_CERFL_OLEF		BIT(5)
+#define RCANFD_CERFL_BOREF		BIT(4)
+#define RCANFD_CERFL_BOEEF		BIT(3)
+#define RCANFD_CERFL_EPEF		BIT(2)
+#define RCANFD_CERFL_EWEF		BIT(1)
+#define RCANFD_CERFL_BEF		BIT(0)
+
+#define RCANFD_CERFL_ERR(x)		((x) & (0x7fff)) /* above bits 14:0 */
+
+/* CAN FD specific registers */
+#define RCANFD_DCFG_TDCE		BIT(9)
+#define RCANFD_DCFG_TDCOC		BIT(8)
+#define RCANFD_DCFG_TDCO(x)		(((x) & 0x7f) >> 16)
+
+#define RCANFD_DCSTS_TDCR(x)		(((x) >> 0) & 0x7f)
+#define RCANFD_DCSTS_SOCCNT(x)		(((x) >> 24) & 0xff)
+#define RCANFD_DCSTS_EOCCNT(x)		(((x) >> 16) & 0xff)
+
+#define RCANFD_DCSTS_TDCVF		BIT(7)
+#define RCANFD_DCSTS_EOCO		BIT(8)
+#define RCANFD_DCSTS_SOCO		BIT(9)
+
+/* Rx FIFO bits */
+#define RCANFD_RFFIFO_RFIF		BIT(3)
+#define RCANFD_RFFIFO_RFMLT		BIT(2)
+#define RCANFD_RFFIFO_RFFLL		BIT(1)
+#define RCANFD_RFFIFO_RFEMP		BIT(0)
+
+#define RCANFD_RFFIFO_RFESI		BIT(0)
+#define RCANFD_RFFIFO_RFBRS		BIT(1)
+#define RCANFD_RFFIFO_RFFDF		BIT(2)
+
+#define RCANFD_RFFIFO_RFIDE		BIT(31)
+#define RCANFD_RFFIFO_RFRTR		BIT(30)
+
+#define RCANFD_RFFIFO_RFDLC(x)		(((x) >> 28) & 0xf)
+#define RCANFD_RFFIFO_RFPTR(x)		(((x) >> 16) & 0xfff)
+#define RCANFD_RFFIFO_RFTS(x)		(((x) >> 0) & 0xff)
+
+#define RCANFD_RFFIFO_RFIM		BIT(12)
+#define RCANFD_RFFIFO_RFDC(x)		(((x) & 0x7) << 8)
+#define RCANFD_RFFIFO_RFPLS(x)		(((x) & 0x7) << 4)
+#define RCANFD_RFFIFO_RFIE		BIT(1)
+#define RCANFD_RFFIFO_RFE		BIT(0)
+
+/* Common FIFO bits */
+#define RCANFD_CMFIFO_TML(x)		(((x) & 0xf) << 20)
+#define RCANFD_CMFIFO_M(x)		(((x) & 0x3) << 16)
+#define RCANFD_CMFIFO_CFIM		BIT(12)
+#define RCANFD_CMFIFO_DC(x)		(((x) & 0x7) << 8)
+#define RCANFD_CMFIFO_PLS(x)		(((x) & 0x7) << 4)
+#define RCANFD_CMFIFO_CFTXIE		BIT(2)
+#define RCANFD_CMFIFO_CFE		BIT(0)
+
+#define RCANFD_CMFIFO_CFTXIF		BIT(4)
+#define RCANFD_CMFIFO_CFMLT		BIT(2)
+#define RCANFD_CMFIFO_CFFLL		BIT(1)
+#define RCANFD_CMFIFO_CFEMP		BIT(0)
+#define RCANFD_CMFIFO_CFMC(x)		(((x) >> 8) & 0xff)
+
+#define RCANFD_CMFIFO_CFESI		BIT(0)
+#define RCANFD_CMFIFO_CFBRS		BIT(1)
+#define RCANFD_CMFIFO_CFFDF		BIT(2)
+
+#define RCANFD_CMFIFO_CFIDE		BIT(31)
+#define RCANFD_CMFIFO_CFRTR		BIT(30)
+#define RCANFD_CMFIFO_CFID(x)		((x) & 0x1fffffff)
+
+#define RCANFD_CMFIFO_CFDLC(x)		(((x) & 0xf) << 28)
+#define RCANFD_CMFIFO_CFPTR(x)		(((x) & 0xfff) << 16)
+#define RCANFD_CMFIFO_CFTS(x)		(((x) & 0xff) << 0)
+
+/* Global Test Config register */
+#define RCANFD_GTSTCFG_C0CBCE		BIT(0)
+#define RCANFD_GTSTCFG_C1CBCE		BIT(1)
+
+#define RCANFD_GTSTCTR_ICBCTME		BIT(0)
+
+/* AFL Rx rules registers */
+#define RCANFD_AFLCFG_SETRNC(n, x)	(((x) & 0xff) << (24 - n * 8))
+#define RCANFD_AFLCFG_GETRNC(n, x)	(((x) >> (24 - n * 8)) & 0xff)
+
+#define RCANFD_AFL_PAGENUM(entry)	((entry) / 16)
+
+#define RCANFD_AFLCTR_AFLDAE		BIT(8)
+#define RCANFD_AFLCTR_AFLPN(x)		((x) & 0x1f)
+#define RCANFD_CHANNEL_NUMRULES		1	/* only one rule per channel */
+#define RCANFD_AFLID_GAFLLB		BIT(29)
+#define RCANFD_AFLPTR1_RFFIFO(x)	(1 << (x))
+
+/* Common register map offsets */
+
+/* Nominal rate registers */
+#define RCANFD_CCFG(m)			(0x0000 + (0x10 * (m)))
+#define RCANFD_CCTR(m)			(0x0004 + (0x10 * (m)))
+#define RCANFD_CSTS(m)			(0x0008 + (0x10 * (m)))
+#define RCANFD_CERFL(m)			(0x000C + (0x10 * (m)))
+
+/* Global registers */
+#define RCANFD_GCFG			(0x0084)
+#define RCANFD_GCTR			(0x0088)
+#define RCANFD_GSTS			(0x008c)
+#define RCANFD_GERFL			(0x0090)
+#define RCANFD_GTSC			(0x0094)
+#define RCANFD_GAFLECTR			(0x0098)
+#define RCANFD_GAFLCFG0			(0x009c)
+#define RCANFD_GAFLCFG1			(0x00a0)
+#define RCANFD_RMNB			(0x00a4)
+
+#define RCANFD_RMND(y)			(0x00a8 + (0x04 * (y)))
+
+/* Rx FIFO Control registers */
+#define RCANFD_RFCC(x)			(0x00b8 + (0x04 * (x)))
+#define RCANFD_RFSTS(x)			(0x00d8 + (0x04 * (x)))
+#define RCANFD_RFPCTR(x)		(0x00f8 + (0x04 * (x)))
+
+/* Common FIFO Control registers */
+#define RCANFD_CFCC(ch, idx)		(0x0118 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+#define RCANFD_CFSTS(ch, idx)		(0x0178 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+#define RCANFD_CFPCTR(ch, idx)		(0x01d8 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+
+#define RCANFD_FESTS			(0x0238)
+#define RCANFD_FFSTS			(0x023c)
+#define RCANFD_FMSTS			(0x0240)
+#define RCANFD_RFISTS			(0x0244)
+#define RCANFD_CFRISTS			(0x0248)
+#define RCANFD_CFTISTS			(0x024c)
+
+#define RCANFD_TMC(p)			(0x0250 + (0x01 * (p)))
+#define RCANFD_TMSTS(p)			(0x02d0 + (0x01 * (p)))
+
+#define RCANFD_TMTRSTS(y)		(0x0350 + (0x04 * (y)))
+#define RCANFD_TMTARSTS(y)		(0x0360 + (0x04 * (y)))
+#define RCANFD_TMTCSTS(y)		(0x0370 + (0x04 * (y)))
+#define RCANFD_TMTASTS(y)		(0x0380 + (0x04 * (y)))
+#define RCANFD_TMIEC(y)			(0x0390 + (0x04 * (y)))
+
+#define RCANFD_TXQCC(m)			(0x03a0 + (0x04 * (m)))
+#define RCANFD_TXQSTS(m)		(0x03c0 + (0x04 * (m)))
+#define RCANFD_TXQPCTR(m)		(0x03e0 + (0x04 * (m)))
+
+#define RCANFD_THLCC(m)			(0x0400 + (0x04 * (m)))
+#define RCANFD_THLSTS(m)		(0x0420 + (0x04 * (m)))
+#define RCANFD_THLPCTR(m)		(0x0440 + (0x04 * (m)))
+
+#define RCANFD_GTINTSTS0		(0x0460)
+#define RCANFD_GTINTSTS1		(0x0464)
+#define RCANFD_GTSTCFG			(0x0468)
+#define RCANFD_GTSTCTR			(0x046c)
+#define RCANFD_GLOCKK			(0x047c)
+#define RCANFD_GRMCFG			(0x04fc)
+
+/* Receive rule registers */
+#define RCANFD_GAFLID(offset, j)	((offset) + (0x10 * (j)))
+#define RCANFD_GAFLM(offset, j)		((offset) + 0x04 + (0x10 * (j)))
+#define RCANFD_GAFLP0(offset, j)	((offset) + 0x08 + (0x10 * (j)))
+#define RCANFD_GAFLP1(offset, j)	((offset) + 0x0c + (0x10 * (j)))
+
+/* CAN FD mode specific regsiter map */
+
+/* Data bitrate registers */
+#define RCANFD_F_CDFG(m)		(0x0500 + (0x20 * (m)))
+#define RCANFD_F_CFDCFG(m)		(0x0504 + (0x20 * (m)))
+#define RCANFD_F_CFDCTR(m)		(0x0508 + (0x20 * (m)))
+#define RCANFD_F_CFDSTS(m)		(0x050c + (0x20 * (m)))
+#define RCANFD_F_CFDCRC(m)		(0x0510 + (0x20 * (m)))
+
+#define RCANFD_F_GAFL_OFFSET		(0x1000)
+
+#define RCANFD_F_RMID(q)		(0x2000 + (0x10 * (q)))
+#define RCANFD_F_RMPTR(q)		(0x2004 + (0x10 * (q)))
+#define RCANFD_F_RMFDSTS(q)		(0x2008 + (0x10 * (q)))
+#define RCANFD_F_RMDF(q, b)		(0x200c + (0x04 * (b)) + (0x20 * (q)))
+
+/* Rx FIFO data registers */
+#define RCANFD_F_RFOFFSET		(0x3000)
+#define RCANFD_F_RFID(x)		(RCANFD_F_RFOFFSET + (0x80 * (x)))
+#define RCANFD_F_RFPTR(x)		(RCANFD_F_RFOFFSET + 0x04 + \
+					 (0x80 * (x)))
+#define RCANFD_F_RFFDSTS(x)		(RCANFD_F_RFOFFSET + 0x08 + \
+					 (0x80 * (x)))
+#define RCANFD_F_RFDF(x, df)		(RCANFD_F_RFOFFSET + 0x0c + \
+					 (0x80 * (x)) + (0x04 * (df)))
+
+/* Common FIFO data registers */
+#define RCANFD_F_CFOFFSET		(0x3400)
+#define RCANFD_F_CFID(ch, idx)		(RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
+					 (0x80 * (idx)))
+#define RCANFD_F_CFPTR(ch, idx)		(RCANFD_F_CFOFFSET + 0x04 + \
+					 (0x180 * (ch)) + (0x80 * (idx)))
+#define RCANFD_F_CFFDCSTS(ch, idx)	(RCANFD_F_CFOFFSET + 0x08 + \
+					 (0x180 * (ch)) + (0x80 * (idx)))
+#define RCANFD_F_CFDF(ch, idx, df)	(RCANFD_F_CFOFFSET + 0x0c + \
+					 (0x180 * (ch)) + (0x80 * (idx)) + \
+					 (0x04 * (df)))
+
+#define RCANFD_F_TMID(p)		(0x4000 + (0x20 * (p)))
+#define RCANFD_F_TMPTR(p)		(0x4004 + (0x20 * (p)))
+#define RCANFD_F_TMFDCTR(p)		(0x4008 + (0x20 * (p)))
+#define RCANFD_F_TMDF(p, b)		(0x400c + (0x20 * (p)) + (0x04 * (b)))
+
+#define RCANFD_F_THLACC(m)		(0x6000 + (0x04 * (m)))
+#define RCANFD_F_RPGACC(r)		(0x6400 + (0x04 * (r)))
+
+/* fCAN clock select register settings */
+enum rcar_canfd_fcanclk {
+	RCANFD_CANFDCLK = 0,		/* CANFD clock */
+	RCANFD_EXTCLK,			/* Externally input clock */
+};
+
+struct rcar_canfd_global;
+
+/* Channel priv data */
+struct rcar_canfd_channel {
+	struct can_priv can;			/* Must be the first member */
+	struct net_device *ndev;
+	struct rcar_canfd_global *gpriv;	/* Controller reference */
+	void __iomem *base;			/* Register base address */
+	struct napi_struct napi;
+	u8  tx_len[RCANFD_FIFO_DEPTH];		/* For net stats */
+	u32 tx_head;				/* Incremented on xmit */
+	u32 tx_tail;				/* Incremented on xmit done */
+	u32 channel;				/* Channel number */
+	spinlock_t tx_lock;			/* To protect tx path */
+};
+
+/* Global priv data */
+struct rcar_canfd_global {
+	struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
+	void __iomem *base;		/* Register base address */
+	struct platform_device *pdev;	/* Respective platform device */
+	struct clk *clkp;		/* Peripheral clock */
+	struct clk *can_clk;		/* fCAN clock */
+	enum rcar_canfd_fcanclk fcan;	/* CANFD or Ext clock */
+	unsigned long channels_mask;	/* Enabled channels mask */
+};
+
+/* CAN FD mode nominal rate constants */
+static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
+	.name = RCANFD_DRV_NAME,
+	.tseg1_min = 2,
+	.tseg1_max = 128,
+	.tseg2_min = 2,
+	.tseg2_max = 32,
+	.sjw_max = 32,
+	.brp_min = 1,
+	.brp_max = 1024,
+	.brp_inc = 1,
+};
+
+/* CAN FD mode data rate constants */
+static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
+	.name = RCANFD_DRV_NAME,
+	.tseg1_min = 2,
+	.tseg1_max = 16,
+	.tseg2_min = 2,
+	.tseg2_max = 8,
+	.sjw_max = 8,
+	.brp_min = 1,
+	.brp_max = 256,
+	.brp_inc = 1,
+};
+
+/* Helper functions */
+static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
+{
+	u32 data = readl(reg);
+
+	data &= ~mask;
+	data |= (val & mask);
+	writel(data, reg);
+}
+
+static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
+{
+	return readl(base + (offset));
+}
+
+static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
+{
+	writel(val, base + (offset));
+}
+
+static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
+{
+	rcar_canfd_update(val, val, base + (reg));
+}
+
+static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
+{
+	rcar_canfd_update(val, 0, base + (reg));
+}
+
+static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
+				  u32 mask, u32 val)
+{
+	rcar_canfd_update(mask, val, base + (reg));
+}
+
+static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
+				struct canfd_frame *cf, u32 off)
+{
+	u32 i, lwords;
+
+	lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
+	for (i = 0; i < lwords; i++)
+		*((u32 *)cf->data + i) =
+			rcar_canfd_read(priv->base, off + (i * sizeof(u32)));
+}
+
+static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
+				struct canfd_frame *cf, u32 off)
+{
+	u32 i, lwords;
+
+	lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
+	for (i = 0; i < lwords; i++)
+		rcar_canfd_write(priv->base, off + (i * sizeof(u32)),
+				 *((u32 *)cf->data + i));
+}
+
+static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
+{
+	u32 i;
+
+	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
+		can_free_echo_skb(ndev, i);
+}
+
+static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
+{
+	u32 sts, ch;
+	int err;
+
+	/* Check RAMINIT flag as CAN RAM initialization takes place
+	 * after the MCU reset
+	 */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 !(sts & RCANFD_GSTS_RAMINIT), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
+		return err;
+	}
+
+	/* Transition to Global Reset mode */
+	rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_SLPR);
+	rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
+			      RCANFD_GCTR_MODEMASK, RCANFD_GCTR_GRESET);
+
+	/* Ensure Global reset mode */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 (sts & RCANFD_GSTS_RESET), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
+		return err;
+	}
+
+	/* Reset Global error flags */
+	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
+
+	/* Set the controller into FD mode */
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG, RCANFD_GINTF_CANFD);
+
+	/* Transition all Channels to reset mode */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_clear_bit(gpriv->base,
+				     RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
+
+		rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
+				      RCANFD_CCTR_MODEMASK,
+				      RCANFD_CCTR_CRESET);
+
+		/* Ensure Channel reset mode */
+		err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
+					 (sts & RCANFD_CSTS_RESET), 2, 500000);
+		if (err) {
+			dev_dbg(&gpriv->pdev->dev,
+				"channel %u reset failed\n", ch);
+			return err;
+		}
+	}
+	return 0;
+}
+
+static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
+{
+	u32 cfg, ch;
+
+	/* Global Configuration settings */
+	cfg = RCANFD_GCFG_EEFE;		/* ECC error flag enabled */
+
+	/* Set External Clock if selected */
+	if (gpriv->fcan != RCANFD_CANFDCLK)
+		cfg |= RCANFD_GCFG_DCS;
+
+	/* Truncate payload to configured message size RFPLS */
+	cfg |= RCANFD_GCFG_CMPOC;
+
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
+
+	/* Channel configuration settings */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
+				   RCANFD_CCTR_ERRD);
+		rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
+				      RCANFD_CCTR_BOMMASK,
+				      RCANFD_CCTR_BOM_ENTRY);
+	}
+}
+
+static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
+					   u32 ch)
+{
+	u32 cfg;
+	int start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	if (ch == 0) {
+		start = 0; /* Channel 0 always starts from 0th rule */
+	} else {
+		/* Get number of Channel 0 rules and adjust */
+		cfg = rcar_canfd_read(gpriv->base, RCANFD_GAFLCFG0);
+		start = RCANFD_AFLCFG_GETRNC(0, cfg);
+	}
+
+	/* Enable write access to entry */
+	page = RCANFD_AFL_PAGENUM(start);
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
+			   (RCANFD_AFLCTR_AFLPN(page) | RCANFD_AFLCTR_AFLDAE));
+
+	/* Write number of rules for channel */
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG0,
+			   RCANFD_AFLCFG_SETRNC(ch, num_rules));
+
+	/* Accept all IDs */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_GAFLID(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* IDE or RTR is not considered for matching */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_GAFLM(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* Any data length accepted */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_GAFLP0(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* Place the msg in corresponding Rx FIFO entry */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_GAFLP1(RCANFD_F_GAFL_OFFSET, start),
+			 RCANFD_AFLPTR1_RFFIFO(ridx));
+
+	/* Disable write access to page */
+	rcar_canfd_clear_bit(gpriv->base,
+			     RCANFD_GAFLECTR, RCANFD_AFLCTR_AFLDAE);
+}
+
+static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	/* Rx FIFO is used for reception */
+	u32 cfg;
+	u16 rfdc, rfpls;
+
+	/* Select Rx FIFO based on channel */
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	rfdc = 2;		/* b010 - 8 messages Rx FIFO depth */
+	rfpls = 7;		/* b111 - Max 64 bytes payload */
+
+	cfg = (RCANFD_RFFIFO_RFIM | RCANFD_RFFIFO_RFDC(rfdc) |
+		RCANFD_RFFIFO_RFPLS(rfpls) | RCANFD_RFFIFO_RFIE);
+	rcar_canfd_write(gpriv->base, RCANFD_RFCC(ridx), cfg);
+}
+
+static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	/* Tx/Rx(Common) FIFO configured in Tx mode is
+	 * used for transmission
+	 *
+	 * Each channel has 3 Common FIFO dedicated to them.
+	 * Use the 1st (index 0) out of 3
+	 */
+	u32 cfg;
+	u16 cftml, cfm, cfdc, cfpls;
+
+	cftml = 0;		/* 0th buffer */
+	cfm = 1;		/* b01 - Transmit mode */
+	cfdc = 2;		/* b010 - 8 messages Tx FIFO depth */
+	cfpls = 7;		/* b111 - Max 64 bytes payload */
+
+	cfg = (RCANFD_CMFIFO_TML(cftml) | RCANFD_CMFIFO_M(cfm) |
+		RCANFD_CMFIFO_CFIM | RCANFD_CMFIFO_DC(cfdc) |
+		RCANFD_CMFIFO_PLS(cfpls) | RCANFD_CMFIFO_CFTXIE);
+	rcar_canfd_write(gpriv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
+
+	/* Clear FD mode specific control/status register */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
+}
+
+static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
+{
+	u32 ctr;
+
+	/* Clear any stray error interrupt flags */
+	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
+
+	/* Global interrupts setup */
+	ctr = RCANFD_GCTR_MEIE;
+	ctr |= RCANFD_GCTR_CFMPOFIE;
+
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
+}
+
+static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
+						 *gpriv)
+{
+	/* Disable all interrupts */
+	rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
+
+	/* Clear any stray error interrupt flags */
+	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
+}
+
+static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
+						 *priv)
+{
+	u32 ctr, ch = priv->channel;
+
+	/* Clear any stray error flags */
+	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
+
+	/* Channel interrupts setup */
+	ctr = (RCANFD_CCTR_TAIE |
+	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
+	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
+	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
+	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
+	rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
+}
+
+static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
+						  *priv)
+{
+	u32 ctr, ch = priv->channel;
+
+	ctr = (RCANFD_CCTR_TAIE |
+	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
+	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
+	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
+	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
+	rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
+
+	/* Clear any stray error flags */
+	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
+}
+
+static void rcar_canfd_global_error(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 ch = priv->channel;
+	u32 gerfl, sts;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
+	if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
+		netdev_dbg(ndev, "Ch0: ECC Error flag\n");
+		stats->tx_dropped++;
+	}
+	if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
+		netdev_dbg(ndev, "Ch1: ECC Error flag\n");
+		stats->tx_dropped++;
+	}
+	if (gerfl & RCANFD_GERFL_MES) {
+		sts = rcar_canfd_read(priv->base,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		if (sts & RCANFD_CMFIFO_CFMLT) {
+			netdev_dbg(ndev, "Tx Message Lost flag\n");
+			stats->tx_dropped++;
+			rcar_canfd_write(priv->base,
+					 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
+					 sts & ~RCANFD_CMFIFO_CFMLT);
+		}
+
+		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
+		if (sts & RCANFD_RFFIFO_RFMLT) {
+			netdev_dbg(ndev, "Rx Message Lost flag\n");
+			stats->rx_dropped++;
+			rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
+					 sts & ~RCANFD_RFFIFO_RFMLT);
+		}
+	}
+	if (gerfl & RCANFD_GERFL_CMPOF) {
+		/* Message Lost flag will be set for respective channel
+		 * when this condition happens with counters and flags
+		 * already updated.
+		 */
+		netdev_dbg(ndev, "global payload overflow interrupt\n");
+	}
+
+	/* Clear all global error interrupts. Only affected channels bits
+	 * get cleared
+	 */
+	rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
+}
+
+static void rcar_canfd_error(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	struct can_frame *cf;
+	struct sk_buff *skb;
+	u32 cerfl, csts;
+	u32 txerr = 0, rxerr = 0;
+	u32 ch = priv->channel;
+
+	/* Propagate the error condition to the CAN stack */
+	skb = alloc_can_err_skb(ndev, &cf);
+	if (!skb) {
+		stats->rx_dropped++;
+		return;
+	}
+
+	/* Channel error interrupt */
+	cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
+	csts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
+	txerr = RCANFD_CSTS_TECCNT(csts);
+	rxerr = RCANFD_CSTS_RECCNT(csts);
+
+	netdev_dbg(ndev, "ch erfl %x sts %x txerr %u rxerr %u\n",
+		   cerfl, csts, txerr, rxerr);
+
+	if (cerfl & RCANFD_CERFL_BEF) {
+		netdev_dbg(ndev, "Bus error\n");
+		cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
+		cf->data[2] = CAN_ERR_PROT_UNSPEC;
+		priv->can.can_stats.bus_error++;
+	}
+	if (cerfl & RCANFD_CERFL_ADEF) {
+		netdev_dbg(ndev, "ACK Delimiter Error\n");
+		stats->tx_errors++;
+		cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
+	}
+	if (cerfl & RCANFD_CERFL_B0EF) {
+		netdev_dbg(ndev, "Bit Error (dominant)\n");
+		stats->tx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_BIT0;
+	}
+	if (cerfl & RCANFD_CERFL_B1EF) {
+		netdev_dbg(ndev, "Bit Error (recessive)\n");
+		stats->tx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_BIT1;
+	}
+	if (cerfl & RCANFD_CERFL_CEF) {
+		netdev_dbg(ndev, "CRC Error\n");
+		stats->rx_errors++;
+		cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
+	}
+	if (cerfl & RCANFD_CERFL_AEF) {
+		netdev_dbg(ndev, "ACK Error\n");
+		stats->tx_errors++;
+		cf->can_id |= CAN_ERR_ACK;
+		cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
+	}
+	if (cerfl & RCANFD_CERFL_FEF) {
+		netdev_dbg(ndev, "Form Error\n");
+		stats->rx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_FORM;
+	}
+	if (cerfl & RCANFD_CERFL_SEF) {
+		netdev_dbg(ndev, "Stuff Error\n");
+		stats->rx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_STUFF;
+	}
+	if (cerfl & RCANFD_CERFL_ALEF) {
+		netdev_dbg(ndev, "Arbitration lost Error\n");
+		priv->can.can_stats.arbitration_lost++;
+		cf->can_id |= CAN_ERR_LOSTARB;
+		cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
+	}
+	if (cerfl & RCANFD_CERFL_BLEF) {
+		netdev_dbg(ndev, "Bus Lock Error\n");
+		stats->rx_errors++;
+		cf->can_id |= CAN_ERR_BUSERROR;
+	}
+	if (cerfl & RCANFD_CERFL_EWEF) {
+		netdev_dbg(ndev, "Error warning interrupt\n");
+		priv->can.state = CAN_STATE_ERROR_WARNING;
+		priv->can.can_stats.error_warning++;
+		cf->can_id |= CAN_ERR_CRTL;
+		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
+			CAN_ERR_CRTL_RX_WARNING;
+		cf->data[6] = txerr;
+		cf->data[7] = rxerr;
+	}
+	if (cerfl & RCANFD_CERFL_EPEF) {
+		netdev_dbg(ndev, "Error passive interrupt\n");
+		priv->can.state = CAN_STATE_ERROR_PASSIVE;
+		priv->can.can_stats.error_passive++;
+		cf->can_id |= CAN_ERR_CRTL;
+		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
+			CAN_ERR_CRTL_RX_PASSIVE;
+		cf->data[6] = txerr;
+		cf->data[7] = rxerr;
+	}
+	if (cerfl & RCANFD_CERFL_BOEEF) {
+		netdev_dbg(ndev, "Bus-off entry interrupt\n");
+		rcar_canfd_tx_failure_cleanup(ndev);
+		priv->can.state = CAN_STATE_BUS_OFF;
+		priv->can.can_stats.bus_off++;
+		can_bus_off(ndev);
+		cf->can_id |= CAN_ERR_BUSOFF;
+	}
+	if (cerfl & RCANFD_CERFL_OLEF) {
+		netdev_dbg(ndev,
+			   "Overload Frame Transmission error interrupt\n");
+		stats->tx_errors++;
+		cf->can_id |= CAN_ERR_PROT;
+		cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
+	}
+
+	/* Clear all channel error interrupts */
+	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
+	stats->rx_packets++;
+	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
+}
+
+static void rcar_canfd_tx_done(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 sts;
+	unsigned long flags;
+	u32 ch = priv->channel;
+
+	do {
+		u8 unsent, sent;
+
+		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
+		stats->tx_packets++;
+		stats->tx_bytes += priv->tx_len[sent];
+		priv->tx_len[sent] = 0;
+		can_get_echo_skb(ndev, sent);
+
+		spin_lock_irqsave(&priv->tx_lock, flags);
+		priv->tx_tail++;
+		sts = rcar_canfd_read(priv->base,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		unsent = RCANFD_CMFIFO_CFMC(sts);
+
+		/* Wake producer only when there is room */
+		if (unsent != RCANFD_FIFO_DEPTH)
+			netif_wake_queue(ndev);
+
+		if (priv->tx_head - priv->tx_tail <= unsent) {
+			spin_unlock_irqrestore(&priv->tx_lock, flags);
+			break;
+		}
+		spin_unlock_irqrestore(&priv->tx_lock, flags);
+
+	} while (1);
+
+	/* Clear interrupt */
+	rcar_canfd_write(priv->base, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
+			 sts & ~RCANFD_CMFIFO_CFTXIF);
+	can_led_event(ndev, CAN_LED_EVENT_TX);
+}
+
+static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
+{
+	struct rcar_canfd_global *gpriv = dev_id;
+	struct net_device *ndev;
+	struct rcar_canfd_channel *priv;
+	u32 sts, gerfl;
+	u32 ch, ridx;
+
+	/* Global error interrupts still indicate a condition specific
+	 * to a channel. RxFIFO interrupt is a global interrupt.
+	 */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		ndev = priv->ndev;
+		ridx = ch + RCANFD_RFFIFO_IDX;
+
+		/* Global error interrupts */
+		gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
+		if (RCANFD_GERFL_ERR(gerfl))
+			rcar_canfd_global_error(ndev);
+
+		/* Handle Rx interrupts */
+		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
+		if (sts & RCANFD_RFFIFO_RFIF) {
+			if (napi_schedule_prep(&priv->napi)) {
+				/* Disable Rx FIFO interrupts */
+				rcar_canfd_clear_bit(priv->base,
+						     RCANFD_RFCC(ridx),
+						     RCANFD_RFFIFO_RFIE);
+				__napi_schedule(&priv->napi);
+			}
+		}
+	}
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
+{
+	struct rcar_canfd_global *gpriv = dev_id;
+	struct net_device *ndev;
+	struct rcar_canfd_channel *priv;
+	u32 sts, cerfl, ch;
+
+	/* Common FIFO is a per channel resource */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		ndev = priv->ndev;
+
+		/* Channel error interrupts */
+		cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
+		if (RCANFD_CERFL_ERR(cerfl))
+			rcar_canfd_error(ndev);
+
+		/* Handle Tx interrupts */
+		sts = rcar_canfd_read(priv->base,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		if (sts & RCANFD_CMFIFO_CFTXIF)
+			rcar_canfd_tx_done(ndev);
+	}
+	return IRQ_HANDLED;
+}
+
+static void rcar_canfd_set_bittiming(struct net_device *dev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(dev);
+	const struct can_bittiming *bt = &priv->can.bittiming;
+	const struct can_bittiming *dbt = &priv->can.data_bittiming;
+	u16 brp, sjw, tseg1, tseg2;
+	u32 cfg;
+	u32 ch = priv->channel;
+
+	/* Nominal bit timing settings */
+	brp = bt->brp - 1;
+	sjw = bt->sjw - 1;
+	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
+	tseg2 = bt->phase_seg2 - 1;
+
+	cfg = (RCANFD_NR_TSEG1(tseg1) | RCANFD_NR_BRP(brp) |
+	       RCANFD_NR_SJW(sjw) | RCANFD_NR_TSEG2(tseg2));
+
+	rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
+	netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
+		   brp, sjw, tseg1, tseg2);
+
+	/* Data bit timing settings */
+	brp = dbt->brp - 1;
+	sjw = dbt->sjw - 1;
+	tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
+	tseg2 = dbt->phase_seg2 - 1;
+
+	cfg = (RCANFD_DR_TSEG1(tseg1) | RCANFD_DR_BRP(brp) |
+	       RCANFD_DR_SJW(sjw) | RCANFD_DR_TSEG2(tseg2));
+
+	rcar_canfd_write(priv->base, RCANFD_F_CDFG(ch), cfg);
+	netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
+		   brp, sjw, tseg1, tseg2);
+}
+
+static int rcar_canfd_start(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	int err = -EOPNOTSUPP;
+	u32 sts, ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	rcar_canfd_set_bittiming(ndev);
+
+	rcar_canfd_enable_channel_interrupts(priv);
+
+	/* Set channel to Operational mode */
+	rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_COPM);
+
+	/* Verify channel mode change */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_COM), 2, 500000);
+	if (err) {
+		netdev_err(ndev, "channel %u communication state failed\n", ch);
+		goto fail_mode_change;
+	}
+
+	/* Enable Common & Rx FIFO */
+	rcar_canfd_set_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
+			   RCANFD_CMFIFO_CFE);
+	rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFE);
+
+	priv->can.state = CAN_STATE_ERROR_ACTIVE;
+	return 0;
+
+fail_mode_change:
+	rcar_canfd_disable_channel_interrupts(priv);
+	return err;
+}
+
+static int rcar_canfd_open(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct rcar_canfd_global *gpriv = priv->gpriv;
+	int err;
+
+	/* Peripheral clock is already enabled in probe */
+	err = clk_prepare_enable(gpriv->can_clk);
+	if (err) {
+		netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
+		goto out_clock;
+	}
+
+	err = open_candev(ndev);
+	if (err) {
+		netdev_err(ndev, "open_candev() failed, error %d\n", err);
+		goto out_can_clock;
+	}
+
+	napi_enable(&priv->napi);
+	err = rcar_canfd_start(ndev);
+	if (err)
+		goto out_close;
+	netif_start_queue(ndev);
+	can_led_event(ndev, CAN_LED_EVENT_OPEN);
+	return 0;
+out_close:
+	napi_disable(&priv->napi);
+	close_candev(ndev);
+out_can_clock:
+	clk_disable_unprepare(gpriv->can_clk);
+out_clock:
+	return err;
+}
+
+static void rcar_canfd_stop(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	int err;
+	u32 sts, ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	/* Transition to channel reset mode  */
+	rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_CRESET);
+
+	/* Check Channel reset mode */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_RESET), 2, 500000);
+	if (err)
+		netdev_err(ndev, "channel %u reset failed\n", ch);
+
+	rcar_canfd_disable_channel_interrupts(priv);
+
+	/* Disable Common & Rx FIFO */
+	rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
+			     RCANFD_CMFIFO_CFE);
+	rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFE);
+
+	/* Set the state as STOPPED */
+	priv->can.state = CAN_STATE_STOPPED;
+}
+
+static int rcar_canfd_close(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct rcar_canfd_global *gpriv = priv->gpriv;
+
+	netif_stop_queue(ndev);
+	rcar_canfd_stop(ndev);
+	napi_disable(&priv->napi);
+	clk_disable_unprepare(gpriv->can_clk);
+	close_candev(ndev);
+	can_led_event(ndev, CAN_LED_EVENT_STOP);
+	return 0;
+}
+
+static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
+					 struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
+	u32 sts = 0, id, dlc;
+	unsigned long flags;
+	u32 ch = priv->channel;
+
+	if (can_dropped_invalid_skb(ndev, skb))
+		return NETDEV_TX_OK;
+
+	if (cf->can_id & CAN_EFF_FLAG) {
+		id = cf->can_id & CAN_EFF_MASK;
+		id |= RCANFD_CMFIFO_CFIDE;
+	} else {
+		id = cf->can_id & CAN_SFF_MASK;
+	}
+
+	if (cf->can_id & CAN_RTR_FLAG)
+		id |= RCANFD_CMFIFO_CFRTR;
+
+	rcar_canfd_write(priv->base,
+			 RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX), id);
+	dlc = RCANFD_CMFIFO_CFDLC(can_len2dlc(cf->len));
+	rcar_canfd_write(priv->base,
+			 RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
+
+	if (can_is_canfd_skb(skb)) {
+		/* CAN FD frame format */
+		sts |= RCANFD_CMFIFO_CFFDF;
+		if (cf->flags & CANFD_BRS)
+			sts |= RCANFD_CMFIFO_CFBRS;
+
+		if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
+			sts |= RCANFD_CMFIFO_CFESI;
+	}
+
+	rcar_canfd_write(priv->base, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX),
+			 sts);
+
+	rcar_canfd_put_data(priv, cf,
+			    RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
+
+	priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
+	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
+
+	spin_lock_irqsave(&priv->tx_lock, flags);
+	priv->tx_head++;
+
+	/* Stop the queue if we've filled all FIFO entries */
+	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
+		netif_stop_queue(ndev);
+
+	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
+	 * pointer for the Common FIFO
+	 */
+	rcar_canfd_write(priv->base,
+			 RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
+
+	spin_unlock_irqrestore(&priv->tx_lock, flags);
+	return NETDEV_TX_OK;
+}
+
+static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
+{
+	struct net_device_stats *stats = &priv->ndev->stats;
+	struct canfd_frame *cf;
+	struct sk_buff *skb;
+	u32 sts = 0, id, ptr;
+	u32 ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	id = rcar_canfd_read(priv->base, RCANFD_F_RFID(ridx));
+	ptr = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(ridx));
+
+	sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(ridx));
+	if (sts & RCANFD_RFFIFO_RFFDF)
+		skb = alloc_canfd_skb(priv->ndev, &cf);
+	else
+		skb = alloc_can_skb(priv->ndev,
+				    (struct can_frame **)&cf);
+
+	if (!skb) {
+		stats->rx_dropped++;
+		return;
+	}
+
+	if (sts & RCANFD_RFFIFO_RFFDF)
+		cf->len = can_dlc2len(RCANFD_RFFIFO_RFDLC(ptr));
+	else
+		cf->len = get_can_dlc(RCANFD_RFFIFO_RFDLC(ptr));
+
+	if (sts & RCANFD_RFFIFO_RFESI) {
+		cf->flags |= CANFD_ESI;
+		netdev_dbg(priv->ndev, "ESI Error\n");
+	}
+
+	if (id & RCANFD_RFFIFO_RFIDE)
+		cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+	else
+		cf->can_id = id & CAN_SFF_MASK;
+
+	if (!(sts & RCANFD_RFFIFO_RFFDF) && (id & RCANFD_RFFIFO_RFRTR)) {
+		cf->can_id |= CAN_RTR_FLAG;
+	} else {
+		if (sts & RCANFD_RFFIFO_RFBRS)
+			cf->flags |= CANFD_BRS;
+
+		rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(ridx, 0));
+	}
+
+	/* Write 0xff to RFPC to increment the CPU-side
+	 * pointer of the Rx FIFO
+	 */
+	rcar_canfd_write(priv->base, RCANFD_RFPCTR(ridx), 0xff);
+
+	can_led_event(priv->ndev, CAN_LED_EVENT_RX);
+
+	stats->rx_bytes += cf->len;
+	stats->rx_packets++;
+	netif_receive_skb(skb);
+}
+
+static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
+{
+	struct rcar_canfd_channel *priv =
+		container_of(napi, struct rcar_canfd_channel, napi);
+	int num_pkts;
+	u32 sts;
+	u32 ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
+		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
+		/* Check FIFO empty condition */
+		if (sts & RCANFD_RFFIFO_RFEMP)
+			break;
+
+		rcar_canfd_rx_pkt(priv);
+
+		/* Clear interrupt bit */
+		if (sts & RCANFD_RFFIFO_RFIF)
+			rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
+					 sts & ~RCANFD_RFFIFO_RFIF);
+	}
+
+	/* All packets processed */
+	if (num_pkts < quota) {
+		napi_complete(napi);
+		/* Enable Rx FIFO interrupts */
+		rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx),
+				   RCANFD_RFFIFO_RFIE);
+	}
+	return num_pkts;
+}
+
+static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
+{
+	int err;
+
+	switch (mode) {
+	case CAN_MODE_START:
+		err = rcar_canfd_start(ndev);
+		if (err)
+			return err;
+		netif_wake_queue(ndev);
+		return 0;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int rcar_canfd_get_berr_counter(const struct net_device *dev,
+				       struct can_berr_counter *bec)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(dev);
+	u32 val, ch = priv->channel;
+
+	/* Peripheral clock is already enabled in probe */
+	val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
+	bec->txerr = RCANFD_CSTS_TECCNT(val);
+	bec->rxerr = RCANFD_CSTS_RECCNT(val);
+	return 0;
+}
+
+static const struct net_device_ops rcar_canfd_netdev_ops = {
+	.ndo_open = rcar_canfd_open,
+	.ndo_stop = rcar_canfd_close,
+	.ndo_start_xmit = rcar_canfd_start_xmit,
+	.ndo_change_mtu = can_change_mtu,
+};
+
+static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
+				    u32 fcan_freq)
+{
+	struct platform_device *pdev = gpriv->pdev;
+	struct rcar_canfd_channel *priv;
+	struct net_device *ndev;
+	int err = -ENODEV;
+
+	ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
+	if (!ndev) {
+		dev_err(&pdev->dev, "alloc_candev() failed\n");
+		err = -ENOMEM;
+		goto fail;
+	}
+	priv = netdev_priv(ndev);
+
+	ndev->netdev_ops = &rcar_canfd_netdev_ops;
+	ndev->flags |= IFF_ECHO;
+	priv->ndev = ndev;
+	priv->base = gpriv->base;
+	priv->channel = ch;
+	priv->can.clock.freq = fcan_freq;
+	dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
+
+	priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
+	priv->can.data_bittiming_const =
+		&rcar_canfd_data_bittiming_const;
+
+	/* Controller starts in CAN FD only mode */
+	can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
+	priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
+
+	priv->can.do_set_mode = rcar_canfd_do_set_mode;
+	priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
+	priv->gpriv = gpriv;
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+
+	netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
+		       RCANFD_NAPI_WEIGHT);
+	err = register_candev(ndev);
+	if (err) {
+		dev_err(&pdev->dev,
+			"register_candev() failed, error %d\n", err);
+		goto fail_candev;
+	}
+	spin_lock_init(&priv->tx_lock);
+	devm_can_led_init(ndev);
+	gpriv->ch[priv->channel] = priv;
+	dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
+	return 0;
+
+fail_candev:
+	netif_napi_del(&priv->napi);
+	free_candev(ndev);
+fail:
+	return err;
+}
+
+static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	struct rcar_canfd_channel *priv = gpriv->ch[ch];
+
+	if (priv) {
+		unregister_candev(priv->ndev);
+		netif_napi_del(&priv->napi);
+		free_candev(priv->ndev);
+	}
+}
+
+static int rcar_canfd_probe(struct platform_device *pdev)
+{
+	struct resource *mem;
+	void __iomem *addr;
+	u32 sts, ch, fcan_freq;
+	struct rcar_canfd_global *gpriv;
+	struct device_node *of_child;
+	unsigned long channels_mask = 0;
+	int err, ch_irq, g_irq;
+
+	of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
+	if (of_child && of_device_is_available(of_child))
+		channels_mask |= BIT(0);	/* Channel 0 */
+
+	of_child = of_get_child_by_name(pdev->dev.of_node, "channel1");
+	if (of_child && of_device_is_available(of_child))
+		channels_mask |= BIT(1);	/* Channel 1 */
+
+	ch_irq = platform_get_irq(pdev, 0);
+	if (ch_irq < 0) {
+		dev_err(&pdev->dev, "no Channel IRQ resource\n");
+		err = ch_irq;
+		goto fail_dev;
+	}
+
+	g_irq = platform_get_irq(pdev, 1);
+	if (g_irq < 0) {
+		dev_err(&pdev->dev, "no Global IRQ resource\n");
+		err = g_irq;
+		goto fail_dev;
+	}
+
+	/* Global controller context */
+	gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
+	if (!gpriv) {
+		err = -ENOMEM;
+		goto fail_dev;
+	}
+	gpriv->pdev = pdev;
+	gpriv->channels_mask = channels_mask;
+
+	/* Peripheral clock */
+	gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
+	if (IS_ERR(gpriv->clkp)) {
+		err = PTR_ERR(gpriv->clkp);
+		dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
+			err);
+		goto fail_dev;
+	}
+
+	/* fCAN clock: Pick External clock. If not available fallback to
+	 * CANFD clock
+	 */
+	gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
+	if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
+		gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
+		if (IS_ERR(gpriv->can_clk)) {
+			err = PTR_ERR(gpriv->can_clk);
+			dev_err(&pdev->dev,
+				"cannot get canfd clock, error %d\n", err);
+			goto fail_dev;
+		}
+		gpriv->fcan = RCANFD_CANFDCLK;
+
+	} else {
+		gpriv->fcan = RCANFD_EXTCLK;
+	}
+	fcan_freq = clk_get_rate(gpriv->can_clk);
+
+	if (gpriv->fcan == RCANFD_CANFDCLK)
+		/* CANFD clock is further divided by (1/2) within the IP */
+		fcan_freq /= 2;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	addr = devm_ioremap_resource(&pdev->dev, mem);
+	if (IS_ERR(addr)) {
+		err = PTR_ERR(addr);
+		goto fail_dev;
+	}
+	gpriv->base = addr;
+
+	/* Request IRQ that's common for both channels */
+	err = devm_request_irq(&pdev->dev, ch_irq,
+			       rcar_canfd_channel_interrupt, 0,
+			       "canfd.chn", gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+			ch_irq, err);
+		goto fail_dev;
+	}
+	err = devm_request_irq(&pdev->dev, g_irq,
+			       rcar_canfd_global_interrupt, 0,
+			       "canfd.gbl", gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+			g_irq, err);
+		goto fail_dev;
+	}
+
+	/* Enable peripheral clock for register access */
+	err = clk_prepare_enable(gpriv->clkp);
+	if (err) {
+		dev_err(&pdev->dev,
+			"failed to enable peripheral clock, error %d\n", err);
+		goto fail_dev;
+	}
+
+	err = rcar_canfd_reset_controller(gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "reset controller failed\n");
+		goto fail_clk;
+	}
+
+	/* Controller in Global reset & Channel reset mode */
+	rcar_canfd_configure_controller(gpriv);
+
+	/* Configure per channel attributes */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		/* Configure Channel's Rx fifo */
+		rcar_canfd_configure_rx(gpriv, ch);
+
+		/* Configure Channel's Tx (Common) fifo */
+		rcar_canfd_configure_tx(gpriv, ch);
+
+		/* Configure receive rules */
+		rcar_canfd_configure_afl_rules(gpriv, ch);
+	}
+
+	/* Configure common interrupts */
+	rcar_canfd_enable_global_interrupts(gpriv);
+
+	/* Start Global operation mode */
+	rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_MODEMASK,
+			      RCANFD_GCTR_GOPM);
+
+	/* Verify mode change */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
+	if (err) {
+		dev_err(&pdev->dev, "global operational mode failed\n");
+		goto fail_mode;
+	}
+
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq);
+		if (err)
+			goto fail_channel;
+	}
+
+	platform_set_drvdata(pdev, gpriv);
+	dev_info(&pdev->dev, "global operational state (clk %d)\n",
+		 gpriv->fcan);
+	return 0;
+
+fail_channel:
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+		rcar_canfd_channel_remove(gpriv, ch);
+fail_mode:
+	rcar_canfd_disable_global_interrupts(gpriv);
+fail_clk:
+	clk_disable_unprepare(gpriv->clkp);
+fail_dev:
+	return err;
+}
+
+static int rcar_canfd_remove(struct platform_device *pdev)
+{
+	struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
+	u32 ch;
+
+	rcar_canfd_reset_controller(gpriv);
+	rcar_canfd_disable_global_interrupts(gpriv);
+
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
+		rcar_canfd_channel_remove(gpriv, ch);
+	}
+
+	/* Enter global sleep mode */
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_SLPR);
+	clk_disable_unprepare(gpriv->clkp);
+	return 0;
+}
+
+static int __maybe_unused rcar_canfd_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int __maybe_unused rcar_canfd_resume(struct device *dev)
+{
+	return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
+			 rcar_canfd_resume);
+
+static const struct of_device_id rcar_canfd_of_table[] = {
+	{ .compatible = "renesas,rcar-gen3-canfd" },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
+
+static struct platform_driver rcar_canfd_driver = {
+	.driver = {
+		.name = RCANFD_DRV_NAME,
+		.of_match_table = of_match_ptr(rcar_canfd_of_table),
+		.pm = &rcar_canfd_pm_ops,
+	},
+	.probe = rcar_canfd_probe,
+	.remove = rcar_canfd_remove,
+};
+
+module_platform_driver(rcar_canfd_driver);
+
+MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
+MODULE_ALIAS("platform:" RCANFD_DRV_NAME);
-- 
1.9.1

[PATCH v5 2/2] can: rcar_can: Move Renesas CAN driver to rcar dir

[Ramesh Shanmugasundaram]

This patch clubs the Renesas controller drivers in one rcar dir.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
---
 drivers/net/can/Kconfig               | 10 ----------
 drivers/net/can/Makefile              |  1 -
 drivers/net/can/rcar/Kconfig          | 10 ++++++++++
 drivers/net/can/rcar/Makefile         |  3 ++-
 drivers/net/can/{ => rcar}/rcar_can.c |  0
 5 files changed, 12 insertions(+), 12 deletions(-)
 rename drivers/net/can/{ => rcar}/rcar_can.c (100%)

diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 13003a9..22570ea 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -104,16 +104,6 @@ config CAN_JANZ_ICAN3
 	  This driver can also be built as a module. If so, the module will be
 	  called janz-ican3.ko.
 
-config CAN_RCAR
-	tristate "Renesas R-Car CAN controller"
-	depends on ARCH_RENESAS || ARM
-	---help---
-	  Say Y here if you want to use CAN controller found on Renesas R-Car
-	  SoCs.
-
-	  To compile this driver as a module, choose M here: the module will
-	  be called rcar_can.
-
 config CAN_SUN4I
 	tristate "Allwinner A10 CAN controller"
 	depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index 226d5b5..26ba4b7 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_CAN_IFI_CANFD)	+= ifi_canfd/
 obj-$(CONFIG_CAN_JANZ_ICAN3)	+= janz-ican3.o
 obj-$(CONFIG_CAN_MSCAN)		+= mscan/
 obj-$(CONFIG_CAN_M_CAN)		+= m_can/
-obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
 obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
 obj-$(CONFIG_CAN_SUN4I)		+= sun4i_can.o
 obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
diff --git a/drivers/net/can/rcar/Kconfig b/drivers/net/can/rcar/Kconfig
index 6ea64d1..7b03a3a 100644
--- a/drivers/net/can/rcar/Kconfig
+++ b/drivers/net/can/rcar/Kconfig
@@ -1,3 +1,13 @@
+config CAN_RCAR
+	tristate "Renesas R-Car CAN controller"
+	depends on ARCH_RENESAS || ARM
+	---help---
+	  Say Y here if you want to use CAN controller found on Renesas R-Car
+	  SoCs.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called rcar_can.
+
 config CAN_RCAR_CANFD
 	tristate "Renesas R-Car CAN FD controller"
 	depends on ARCH_RENESAS || ARM
diff --git a/drivers/net/can/rcar/Makefile b/drivers/net/can/rcar/Makefile
index cbaf498e..08de36a 100644
--- a/drivers/net/can/rcar/Makefile
+++ b/drivers/net/can/rcar/Makefile
@@ -1,5 +1,6 @@
 #
-#  Makefile for the Renesas R-Car CAN FD controller driver
+#  Makefile for the Renesas R-Car CAN & CAN FD controller drivers
 #
 
+obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
 obj-$(CONFIG_CAN_RCAR_CANFD)	+= rcar_canfd.o
diff --git a/drivers/net/can/rcar_can.c b/drivers/net/can/rcar/rcar_can.c
similarity index 100%
rename from drivers/net/can/rcar_can.c
rename to drivers/net/can/rcar/rcar_can.c
-- 
1.9.1

RE: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Oliver,

Thanks :-)
Actually it will be v5 patch set & I have sent it now. Marc comments were on old v2 patch.

Thanks,
Ramesh

> -----Original Message-----
> From: Oliver Hartkopp [mailto:socketcan@hartkopp.net]
> Sent: 28 April 2016 07:28
> To: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>;
> wg@grandegger.com; robh+dt@kernel.org; pawel.moll@arm.com;
> mark.rutland@arm.com; ijc+devicetree@hellion.org.uk; galak@codeaurora.org;
> corbet@lwn.net; mkl@pengutronix.de
> Cc: linux-renesas-soc@vger.kernel.org; devicetree@vger.kernel.org; linux-
> can@vger.kernel.org; netdev@vger.kernel.org; linux-doc@vger.kernel.org;
> geert+renesas@glider.be; Chris Paterson <Chris.Paterson2@renesas.com>
> Subject: Re: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD driver
> 
> Hello Ramesh,
> 
> please send out a new v3 patchset to trigger the process again :-)
> 
> Best regards,
> Oliver
> 
> On 04/13/2016 08:25 AM, Ramesh Shanmugasundaram wrote:
> > HI Marc,
> >
> > Gentle reminder!
> > Are you happy with the open comment's disposition? I can send a next
> version of patch if we have a closure on current set of comments.
> >
> > Thanks,
> > Ramesh
> >
> >> -----Original Message-----
> >> From: Ramesh Shanmugasundaram
> >> Sent: 01 April 2016 13:49
> >> To: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>;
> >> wg@grandegger.com; robh+dt@kernel.org; pawel.moll@arm.com;
> >> mark.rutland@arm.com; ijc+devicetree@hellion.org.uk;
> >> galak@codeaurora.org; corbet@lwn.net
> >> Cc: linux-renesas-soc@vger.kernel.org; devicetree@vger.kernel.org;
> >> linux- can@vger.kernel.org; netdev@vger.kernel.org;
> >> linux-doc@vger.kernel.org;
> >> geert+renesas@glider.be; Chris Paterson <Chris.Paterson2@renesas.com>
> >> Subject: RE: [PATCH v2] can: rcar_canfd: Add Renesas R-Car CAN FD
> >> driver
> >>
> >> Hi Marc,
> >>
> >> Thanks for your time & review comments.
> >>
> >>> -----Original Message-----
> >> (...)
> >>>> +#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
> >>>> +
> >>>> +#define RCANFD_NUM_CHANNELS		2
> >>>> +#define RCANFD_CHANNELS_MASK		0x3	/* Two channels max */
> >>>
> >>> (BIT(RCANFD_NUM_CHANNELS) - 1
> >>
> >> OK
> >>
> >>>
> >>>> +
> >>>> +/* Rx FIFO is a global resource of the controller. There are 8
> >>>> +such
> >>> FIFOs
> >>>> + * available. Each channel gets a dedicated Rx FIFO (i.e.) the
> >>>> + channel
> >> (...)
> >>>> +#define RCANFD_CMFIFO_CFDLC(x)		(((x) & 0xf) << 28)
> >>>> +#define RCANFD_CMFIFO_CFPTR(x)		(((x) & 0xfff) << 16)
> >>>> +#define RCANFD_CMFIFO_CFTS(x)		(((x) & 0xff) << 0)
> >>>> +
> >>>> +/* Global Test Config register */
> >>>> +#define RCANFD_GTSTCFG_C0CBCE		BIT(0)
> >>>> +#define RCANFD_GTSTCFG_C1CBCE		BIT(1)
> >>>> +
> >>>> +#define RCANFD_GTSTCTR_ICBCTME		BIT(0)
> >>>> +
> >>>> +/* AFL Rx rules registers */
> >>>> +#define RCANFD_AFLCFG_SETRNC0(x)	(((x) & 0xff) << 24)
> >>>> +#define RCANFD_AFLCFG_SETRNC1(x)	(((x) & 0xff) << 16)
> >>>
> >>> What about something like:
> >>>
> >>> #define RCANFD_AFLCFG_SETRNC(n, x)	(((x) & 0xff) << (24 - n * 8))
> >>>
> >>> This will save some if()s in the code
> >>
> >> Nice :-). Will update.
> >>
> >>>
> >>>> +#define RCANFD_AFLCFG_GETRNC0(x)	(((x) >> 24) & 0xff)
> >>>> +#define RCANFD_AFLCFG_GETRNC1(x)	(((x) >> 16) & 0xff)
> >>>> +
> >>>> +#define RCANFD_AFL_PAGENUM(entry)	((entry) / 16)
> >> (...)
> >>>> +#define rcar_canfd_read(priv, offset)			\
> >>>> +	readl(priv->base + (offset))
> >>>> +#define rcar_canfd_write(priv, offset, val)		\
> >>>> +	writel(val, priv->base + (offset))
> >>>> +#define rcar_canfd_set_bit(priv, reg, val)		\
> >>>> +	rcar_canfd_update(val, val, priv->base + (reg))
> >>>> +#define rcar_canfd_clear_bit(priv, reg, val)		\
> >>>> +	rcar_canfd_update(val, 0, priv->base + (reg))
> >>>> +#define rcar_canfd_update_bit(priv, reg, mask, val)	\
> >>>> +	rcar_canfd_update(mask, val, priv->base + (reg))
> >>>
> >>> please use static inline functions instead of defines.
> >>
> >> OK.
> >>
> >>>
> >>>> +
> >>>> +static void rcar_canfd_get_data(struct canfd_frame *cf,
> >>>> +				struct rcar_canfd_channel *priv, u32 off)
> >>>
> >>> Please use "struct rcar_canfd_channel *priv" as first argument,
> >>> struct canfd_frame *cf as second. Remove off, as the offset is
> >>> already defined by the channel.
> >>
> >> I'll re-order priv, cf as you mentioned. I'll leave "off" arg as it
> >> is because it is based on FIFO number of channel + mode (CAN only or
> >> CANFD only). Otherwise, I will have to add another check inside this
> >> function for mode.
> >>
> >>>> +{
> >>>> +	u32 i, lwords;
> >>>> +
> >>>> +	lwords = cf->len / sizeof(u32);
> >>>> +	if (cf->len % sizeof(u32))
> >>>> +		lwords++;
> >>>
> >>> Use DIV_ROUND_UP() instead of open coding it.
> >>
> >> Agreed. Thanks.
> >>
> >>>
> >>>> +	for (i = 0; i < lwords; i++)
> >>>> +		*((u32 *)cf->data + i) =
> >>>> +			rcar_canfd_read(priv, off + (i * sizeof(u32))); }
> >>>> +
> >>>> +static void rcar_canfd_put_data(struct canfd_frame *cf,
> >>>> +				struct rcar_canfd_channel *priv, u32 off)
> >>>
> >>> same here
> >>
> >> Yes (same as _get_data)
> >>
> >>>
> >>>> +{
> >>>> +	u32 i, j, lwords, leftover;
> >>>> +	u32 data = 0;
> >>>> +
> >>>> +	lwords = cf->len / sizeof(u32);
> >>>> +	leftover = cf->len % sizeof(u32);
> >>>> +	for (i = 0; i < lwords; i++)
> >>>> +		rcar_canfd_write(priv, off + (i * sizeof(u32)),
> >>>> +				 *((u32 *)cf->data + i));
> >>>
> >>> Here you don't convert the endianess...
> >>
> >> Yes
> >>
> >>>> +
> >>>> +	if (leftover) {
> >>>> +		u8 *p = (u8 *)((u32 *)cf->data + i);
> >>>> +
> >>>> +		for (j = 0; j < leftover; j++)
> >>>> +			data |= p[j] << (j * 8);
> >>>
> >>> ...here you do an implicit endianess conversion. "data" is little
> >>> endian, while p[j] is big endian.
> >>
> >> Not sure I got the question correctly.
> >> Controller expectation of data bytes in 32bit register is bits[7:0] =
> >> byte0, bits[15:8] = byte1 and so on - little endian.
> >> For e.g. if cf->data points to byte stream H'112233445566
> >> (cf->data[0] = 0x11), first rcar_canfd_write will write 0x44332211
> >> value to register. Yes the host cpu is assumed little endian. In
> >> leftover case, data will be
> >> 0x00006655 - again little endian.
> >> I think I should remove this leftover logic and just mask the unused
> >> bits to zero as cf->data is pre-allocated for max length anyway.
> >>
> >> p[j] is a byte?? Am I missing something?
> >>
> >>>
> >>>> +		rcar_canfd_write(priv, off + (i * sizeof(u32)), data);
> >>>> +	}
> >>>
> >>> Have you tested to send CAN frames with len != n*4 against a
> >>> different controller?
> >>
> >> Yes, with Vector VN1630A.
> >>
> >>>> +}
> >>>> +
> >>>> +static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
> >>>> +{
> >>>> +	u32 i;
> >>>> +
> >>>> +	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
> >>>> +		can_free_echo_skb(ndev, i);
> >>>> +}
> >>>> +
> >> (...)
> >>>> +static void rcar_canfd_tx_done(struct net_device *ndev) {
> >>>> +	struct rcar_canfd_channel *priv = netdev_priv(ndev);
> >>>> +	struct net_device_stats *stats = &ndev->stats;
> >>>> +	u32 sts;
> >>>> +	unsigned long flags;
> >>>> +	u32 ch = priv->channel;
> >>>> +
> >>>> +	do {
> >>>
> >>> You should iterare over all pending CAN frames:
> >>>
> >>>> 	for (/* nix */; (priv->tx_head - priv->tx_tail) > 0; priv-
> >>>> tx_tail++) {
> >>>
> >>
> >> Yes, current code does iterate over pending tx'ed frames. If we use
> >> this for loop semantics, we may have to protect the whole loop with
> >> no real benefit.
> >>
> >>>
> >>>> +		u8 unsent, sent;
> >>>> +
> >>>> +		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
> >>>
> >>> and check here, if that packet has really been tramsitted. Exit the
> >>> loop otherweise.
> >>
> >> We are here because of tx_done and hence no need to check tx done
> >> again for the first iteration. Hence the do-while loop. Checks
> >> further down takes care of the need for more iterations/pending tx'ed
> frames.
> >>
> >>>
> >>>> +		stats->tx_packets++;
> >>>> +		stats->tx_bytes += priv->tx_len[sent];
> >>>> +		priv->tx_len[sent] = 0;
> >>>> +		can_get_echo_skb(ndev, sent);
> >>>> +
> >>>> +		spin_lock_irqsave(&priv->tx_lock, flags);
> >>>
> >>> What does the tx_lock protect? The tx path is per channel, isn't it?
> >>
> >> You are right - tx path is per channel. In tx path, head & tail are
> >> also used to determine when to stop/wakeup netif queue. They are
> >> incremented & compared in different contexts to make this decision.
> >> Per channel tx_lock protects this critical section.
> >>
> >>>
> >>>> +		priv->tx_tail++;
> >>>> +		sts = rcar_canfd_read(priv,
> >>>> +				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
> >>>> +		unsent = RCANFD_CMFIFO_CFMC(sts);
> >>>> +
> >>>> +		/* Wake producer only when there is room */
> >>>> +		if (unsent != RCANFD_FIFO_DEPTH)
> >>>> +			netif_wake_queue(ndev);
> >>>
> >>> Move the netif_wake_queue() out of the loop.
> >>
> >> With the tx logic mentioned above, I think keeping it in the loop
> >> seems better. For e.g. say cpu1 pumps 8 frames from an app loop and
> >> cpu0 handles tx_done interrupt handling: cpu1 would have stopped the
> >> queue because FIFO is full -> cpu0 gets tx_done interrupt and by the
> time it checks "unsent"
> >> there could be one or more frames transmitted by device (i.e.) there
> >> would be more space in fifo. It is better to wakeup the netif queue
> >> then and there so that app running on cpu1 can pump more. If we move
> >> it out of the loop we wake up the queue only in the end. Have I missed
> anything?
> >>
> >>>
> >>>> +
> >>>> +		if (priv->tx_head - priv->tx_tail <= unsent) {
> >>>> +			spin_unlock_irqrestore(&priv->tx_lock, flags);
> >>>> +			break;
> >>>> +		}
> >>>> +		spin_unlock_irqrestore(&priv->tx_lock, flags);
> >>>> +
> >>>> +	} while (1);
> >>>> +
> >>>> +	/* Clear interrupt */
> >>>> +	rcar_canfd_write(priv, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
> >>>> +			 sts & ~RCANFD_CMFIFO_CFTXIF);
> >>>> +	can_led_event(ndev, CAN_LED_EVENT_TX); }
> >>>> +
> >>>> +	if (cf->can_id & CAN_RTR_FLAG)
> >>>> +		id |= RCANFD_CMFIFO_CFRTR;
> >>>> +
> >>>> +	rcar_canfd_write(priv, RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX),
> >>>> +			 id);
> >>>> +	ptr = RCANFD_CMFIFO_CFDLC(can_len2dlc(cf->len));
> >>>
> >>> ptr usually means pointer, better call it dlc.
> >>
> >> I used the register name "ptr". OK, will change it do dlc.
> >>
> >>>
> >>>> +	rcar_canfd_write(priv, RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX),
> >>>> +			 ptr);
> >>>> +
> >> (...)
> >>>> +	can_put_echo_skb(skb, ndev, priv->tx_head %
> RCANFD_FIFO_DEPTH);
> >>>> +
> >>>> +	spin_lock_irqsave(&priv->tx_lock, flags);
> >>>> +	priv->tx_head++;
> >>>> +
> >>>> +	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
> >>>> +	 * pointer for the Common FIFO
> >>>> +	 */
> >>>> +	rcar_canfd_write(priv, RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX),
> >>>> +0xff);
> >>>> +
> >>>> +	/* Stop the queue if we've filled all FIFO entries */
> >>>> +	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
> >>>> +		netif_stop_queue(ndev);
> >>>
> >>> Please move the check of stop_queue, before starting the send.
> >>
> >> OK.
> >>
> >>>
> >>>> +
> >>>> +	spin_unlock_irqrestore(&priv->tx_lock, flags);
> >>>> +	return NETDEV_TX_OK;
> >>>> +}
> >>>> +
> >> (...)
> >>>> +{
> >>>> +	struct rcar_canfd_channel *priv =
> >>>> +		container_of(napi, struct rcar_canfd_channel, napi);
> >>>> +	int num_pkts;
> >>>> +	u32 sts;
> >>>> +	u32 ch = priv->channel;
> >>>> +	u32 ridx = ch + RCANFD_RFFIFO_IDX;
> >>>> +
> >>>> +	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
> >>>> +		sts = rcar_canfd_read(priv, RCANFD_RFSTS(ridx));
> >>>> +		/* Clear interrupt bit */
> >>>> +		if (sts & RCANFD_RFFIFO_RFIF)
> >>>> +			rcar_canfd_write(priv, RCANFD_RFSTS(ridx),
> >>>> +					 sts & ~RCANFD_RFFIFO_RFIF);
> >>>> +
> >>>> +		/* Check FIFO empty condition */
> >>>> +		if (sts & RCANFD_RFFIFO_RFEMP)
> >>>> +			break;
> >>>> +
> >>>> +		rcar_canfd_rx_pkt(priv);
> >>>
> >>> This sequence looks strange. You first conditionally ack the
> >>> interrupt then you check for empty fifo, then read the CAN frame. I
> >>> would assume that you first check if there's a CAN frame, read it
> >>> and then clear the interrupt.
> >>
> >> Yes, I shall re-arrange the sequence as you mentioned.
> >>
> >>>
> >>>> +	}
> >>>> +
> >>>> +	/* All packets processed */
> >>>> +	if (num_pkts < quota) {
> >>>> +		napi_complete(napi);
> >>>> +		/* Enable Rx FIFO interrupts */
> >>>> +		rcar_canfd_set_bit(priv, RCANFD_RFCC(ridx),
> >>> RCANFD_RFFIFO_RFIE);
> >> (...)
> >>>> +	for_each_set_bit(ch, &gpriv->channels_mask,
> RCANFD_NUM_CHANNELS) {
> >>>> +		err = rcar_canfd_channel_probe(gpriv, ch);
> >>>> +		if (err)
> >>>> +			goto fail_channel;
> >>>> +	}
> >>>
> >>> Should the CAN IP core be clocked the whole time? What about shuting
> >>> down the clock and enabling it on ifup?
> >>
> >> The fCAN clock is enabled only on ifup of one of the channels.
> >> However, the peripheral clock is enabled during probe to bring the
> >> controller to Global Operational mode. This clock cannot be turned
> >> off with the register values & mode retained.
> >>
> >>>> +
> >>>> +	platform_set_drvdata(pdev, gpriv);
> >>>> +	dev_info(&pdev->dev, "global operational state (clk %d)\n",
> >>>> +		 gpriv->clock_select);
> >> (...)
> >>>> +	rcar_canfd_reset_controller(gpriv);
> >>>> +	rcar_canfd_disable_global_interrupts(gpriv);
> >>>> +
> >>>> +	for_each_set_bit(ch, &gpriv->channels_mask,
> RCANFD_NUM_CHANNELS) {
> >>>> +		priv = gpriv->ch[ch];
> >>>> +		if (priv) {
> >>>
> >>> This should always be true.
> >>
> >> I agree. I thought I cleaned this up but it's in my local commits :-(
> >>
> >>>
> >>>> +			rcar_canfd_disable_channel_interrupts(priv);
> >>>> +			unregister_candev(priv->ndev);
> >>>> +			netif_napi_del(&priv->napi);
> >>>> +			free_candev(priv->ndev);
> >>>
> >>> Please make use of rcar_canfd_channel_remove(), as you already have
> >>> the function.
> >>
> >> Yes.
> >>
> >> Thanks,
> >> Ramesh

Re: [PATCH v5 1/2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Rob Herring]

On Thu, Apr 28, 2016 at 01:23:07PM +0100, Ramesh Shanmugasundaram wrote:
> This patch adds support for the CAN FD controller found in Renesas R-Car
> SoCs. The controller operates in CAN FD only mode by default.
> 
> CAN FD mode supports both Classical CAN & CAN FD frame formats. The
> controller supports ISO 11898-1:2015 CAN FD format only.
> 
> This controller supports two channels and the driver can enable either
> or both of the channels.
> 
> Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs (one
> per channel) for transmission. Rx filter rules are configured to the
> minimum (one per channel) and it accepts Standard, Extended, Data &
> Remote Frame combinations.
> 
> Note: There are few documentation errors in R-Car Gen3 Hardware User
> Manual v0.5E with respect to CAN FD controller. They are listed below:
> 
> 1. CAN FD interrupt numbers 29 & 30 are listed as per channel
> interrupts. However, they are common to both channels (i.e.) they are
> global and channel interrupts respectively.
> 
> 2. CANFD clock is derived from PLL1. This is not documented.
> 
> 3. CANFD clock is further divided by (1/2) within the CAN FD controller.
> This is not documented.
> 
> 4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
> is specified 4 Tq in the manual.
> 
> 5. The maximum number of message RAM area the controller can use is 3584
> bytes. It is specified 10752 bytes in the manual.
> 
> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
> ---
>  .../devicetree/bindings/net/can/rcar_canfd.txt     |   89 ++

What happened to my ack?

>  drivers/net/can/Kconfig                            |    1 +
>  drivers/net/can/Makefile                           |    1 +
>  drivers/net/can/rcar/Kconfig                       |   11 +
>  drivers/net/can/rcar/Makefile                      |    5 +
>  drivers/net/can/rcar/rcar_canfd.c                  | 1624 ++++++++++++++++++++
>  6 files changed, 1731 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
>  create mode 100644 drivers/net/can/rcar/Kconfig
>  create mode 100644 drivers/net/can/rcar/Makefile
>  create mode 100644 drivers/net/can/rcar/rcar_canfd.c

RE: [PATCH v5 1/2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Rob,

> On Thu, Apr 28, 2016 at 01:23:07PM +0100, Ramesh Shanmugasundaram wrote:
> > This patch adds support for the CAN FD controller found in Renesas
> > R-Car SoCs. The controller operates in CAN FD only mode by default.
> >
> > CAN FD mode supports both Classical CAN & CAN FD frame formats. The
> > controller supports ISO 11898-1:2015 CAN FD format only.
> >
> > This controller supports two channels and the driver can enable either
> > or both of the channels.
> >
> > Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs
> > (one per channel) for transmission. Rx filter rules are configured to
> > the minimum (one per channel) and it accepts Standard, Extended, Data
> > & Remote Frame combinations.
> >
> > Note: There are few documentation errors in R-Car Gen3 Hardware User
> > Manual v0.5E with respect to CAN FD controller. They are listed below:
> >
> > 1. CAN FD interrupt numbers 29 & 30 are listed as per channel
> > interrupts. However, they are common to both channels (i.e.) they are
> > global and channel interrupts respectively.
> >
> > 2. CANFD clock is derived from PLL1. This is not documented.
> >
> > 3. CANFD clock is further divided by (1/2) within the CAN FD controller.
> > This is not documented.
> >
> > 4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
> > is specified 4 Tq in the manual.
> >
> > 5. The maximum number of message RAM area the controller can use is
> > 3584 bytes. It is specified 10752 bytes in the manual.
> >
> > Signed-off-by: Ramesh Shanmugasundaram
> > <ramesh.shanmugasundaram@bp.renesas.com>
> > ---
> >  .../devicetree/bindings/net/can/rcar_canfd.txt     |   89 ++
> 
> What happened to my ack?

Sorry, I missed it when I updated the patch. I mentioned it in cover letter though. I will request the CAN maintainer to add it if this is accepted or otherwise I will add it to the next patch series.

---
Changes since v3:
	* Split v3 patch into two (Marc K)
	  (1) Introduce rcar_canfd.c driver in drivers/net/can/rcar dir
	  (2) Move rcar_can.c driver to new drivers/net/can/rcar dir
	* Added Acked-by Rob H for the bindings
---

Thanks,
Ramesh

RE: [PATCH v5 0/2] Add CAN FD driver support to r8a7795 SoC

[Chris Paterson]

Hello Marc.

This patch series has been waiting for a response for a while now and we are keen to see it included upstream.

Are there any blocking points to it being accepted?


Kind regards, Chris


> -----Original Message-----
> From: Ramesh Shanmugasundaram
> [mailto:ramesh.shanmugasundaram@bp.renesas.com]
> Sent: 28 April 2016 13:23
> To: mkl@pengutronix.de; wg@grandegger.com; socketcan@hartkopp.net;
> robh+dt@kernel.org; pawel.moll@arm.com; mark.rutland@arm.com;
> ijc+devicetree@hellion.org.uk; galak@codeaurora.org
> Cc: linux-renesas-soc@vger.kernel.org; devicetree@vger.kernel.org; linux-
> can@vger.kernel.org; netdev@vger.kernel.org; Chris Paterson
> <Chris.Paterson2@renesas.com>; Ramesh Shanmugasundaram
> <ramesh.shanmugasundaram@bp.renesas.com>
> Subject: [PATCH v5 0/2] Add CAN FD driver support to r8a7795 SoC
> 
> Hi All,
> 
>    This patch is based on commit "885cc17abad6" of can-next/testing branch
> 
> Changes since v4:
> 	* Rebased to latest can-next/testing branch
> 	* Addressed Marc K review comments on v2 patch
> 	* Use clk_get_rate() to find ext clock availability. Refer thread
> 	(https://lkml.org/lkml/2016/4/8/203)
> 
> Changes since v3:
> 	* Split v3 patch into two (Marc K)
> 	  (1) Introduce rcar_canfd.c driver in drivers/net/can/rcar dir
> 	  (2) Move rcar_can.c driver to new drivers/net/can/rcar dir
> 	* Added Acked-by Rob H for the bindings
> 	* Added comments on CAN FD only mode in driver & Kconfig (Oliver
> H)
> 
> Changes since v2:
> 	* Rebased to latest tag (linux-can-next-for-4.6-20160310)
> 	* Cleaned up leftover debugfs code (Thanks Oliver H)
> 	* Revised devicetree documentation text (as suggested by Rob H)
> 	  (https://www.mail-archive.com/linux-renesas-
> soc@vger.kernel.org/msg01597.html)
> 	* Used new can subsystem api to set static configuration & removed
> check in rcar_canfd_start (as suggested by Oliver H)
> 	  (Refer: http://comments.gmane.org/gmane.linux.can/9126 &
> 	   https://www.mail-archive.com/linux-renesas-
> soc@vger.kernel.org/msg01867.html)
> 	* Clubbed Renesas controller drivers to driver/net/can/rcar dir (as
> suggested by Oliver H)
> 	* Updated commit message
> 
> Changes since v1:
> 	* Removed testmodes & debugfs code (suggested by Oliver H)
> 	* Fixed tx path race issue by introducing lock (suggested by Marc K)
> 	* Removed __maybe_unused attribute of rcar_canfd_of_table
> 
> Ramesh Shanmugasundaram (2):
>   can: rcar_canfd: Add Renesas R-Car CAN FD driver
>   can: rcar_can: Move Renesas CAN driver to rcar dir
> 
>  .../devicetree/bindings/net/can/rcar_canfd.txt     |   89 ++
>  drivers/net/can/Kconfig                            |   11 +-
>  drivers/net/can/Makefile                           |    2 +-
>  drivers/net/can/rcar/Kconfig                       |   21 +
>  drivers/net/can/rcar/Makefile                      |    6 +
>  drivers/net/can/{ => rcar}/rcar_can.c              |    0
>  drivers/net/can/rcar/rcar_canfd.c                  | 1624 ++++++++++++++++++++
>  7 files changed, 1742 insertions(+), 11 deletions(-)  create mode 100644
> Documentation/devicetree/bindings/net/can/rcar_canfd.txt
>  create mode 100644 drivers/net/can/rcar/Kconfig  create mode 100644
> drivers/net/can/rcar/Makefile  rename drivers/net/can/{ => rcar}/rcar_can.c
> (100%)  create mode 100644 drivers/net/can/rcar/rcar_canfd.c
> 
> --
> 1.9.1

[RESEND PATCH v5 0/2] Add CAN FD driver support to r8a7795 SoC

[Ramesh Shanmugasundaram]

--------------------------
Resend of patch set [1] posted on Apr 28th 2016

[1] https://www.mail-archive.com/linux-renesas-soc%40vger.kernel.org/msg03352.html
--------------------------

Hi All,

   This patch is based on commit "885cc17abad6" of can-next/testing branch

Changes since v4:
	* Rebased to latest can-next/testing branch
	* Addressed Marc K review comments on v2 patch
	* Use clk_get_rate() to find ext clock availability. Refer thread
	(https://lkml.org/lkml/2016/4/8/203)

Changes since v3:
	* Split v3 patch into two (Marc K)
	  (1) Introduce rcar_canfd.c driver in drivers/net/can/rcar dir
	  (2) Move rcar_can.c driver to new drivers/net/can/rcar dir
	* Added Acked-by Rob H for the bindings
	* Added comments on CAN FD only mode in driver & Kconfig (Oliver H)

Changes since v2:
	* Rebased to latest tag (linux-can-next-for-4.6-20160310)
	* Cleaned up leftover debugfs code (Thanks Oliver H)
	* Revised devicetree documentation text (as suggested by Rob H)
	  (https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg01597.html)
	* Used new can subsystem api to set static configuration & removed check in rcar_canfd_start (as suggested by Oliver H)
	  (Refer: http://comments.gmane.org/gmane.linux.can/9126 &
	   https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg01867.html)
	* Clubbed Renesas controller drivers to driver/net/can/rcar dir (as suggested by Oliver H)
	* Updated commit message

Changes since v1:
	* Removed testmodes & debugfs code (suggested by Oliver H)
	* Fixed tx path race issue by introducing lock (suggested by Marc K)
	* Removed __maybe_unused attribute of rcar_canfd_of_table

Ramesh Shanmugasundaram (2):
  can: rcar_canfd: Add Renesas R-Car CAN FD driver
  can: rcar_can: Move Renesas CAN driver to rcar dir

 .../devicetree/bindings/net/can/rcar_canfd.txt     |   89 ++
 drivers/net/can/Kconfig                            |   11 +-
 drivers/net/can/Makefile                           |    2 +-
 drivers/net/can/rcar/Kconfig                       |   21 +
 drivers/net/can/rcar/Makefile                      |    6 +
 drivers/net/can/{ => rcar}/rcar_can.c              |    0
 drivers/net/can/rcar/rcar_canfd.c                  | 1624 ++++++++++++++++++++
 7 files changed, 1742 insertions(+), 11 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
 create mode 100644 drivers/net/can/rcar/Kconfig
 create mode 100644 drivers/net/can/rcar/Makefile
 rename drivers/net/can/{ => rcar}/rcar_can.c (100%)
 create mode 100644 drivers/net/can/rcar/rcar_canfd.c

-- 
1.9.1

[RESEND PATCH v5 1/2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

This patch adds support for the CAN FD controller found in Renesas R-Car
SoCs. The controller operates in CAN FD only mode by default.

CAN FD mode supports both Classical CAN & CAN FD frame formats. The
controller supports ISO 11898-1:2015 CAN FD format only.

This controller supports two channels and the driver can enable either
or both of the channels.

Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs (one
per channel) for transmission. Rx filter rules are configured to the
minimum (one per channel) and it accepts Standard, Extended, Data &
Remote Frame combinations.

Note: There are few documentation errors in R-Car Gen3 Hardware User
Manual v0.5E with respect to CAN FD controller. They are listed below:

1. CAN FD interrupt numbers 29 & 30 are listed as per channel
interrupts. However, they are common to both channels (i.e.) they are
global and channel interrupts respectively.

2. CANFD clock is derived from PLL1. This is not documented.

3. CANFD clock is further divided by (1/2) within the CAN FD controller.
This is not documented.

4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
is specified 4 Tq in the manual.

5. The maximum number of message RAM area the controller can use is 3584
bytes. It is specified 10752 bytes in the manual.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/net/can/rcar_canfd.txt     |   89 ++
 drivers/net/can/Kconfig                            |    1 +
 drivers/net/can/Makefile                           |    1 +
 drivers/net/can/rcar/Kconfig                       |   11 +
 drivers/net/can/rcar/Makefile                      |    5 +
 drivers/net/can/rcar/rcar_canfd.c                  | 1624 ++++++++++++++++++++
 6 files changed, 1731 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
 create mode 100644 drivers/net/can/rcar/Kconfig
 create mode 100644 drivers/net/can/rcar/Makefile
 create mode 100644 drivers/net/can/rcar/rcar_canfd.c

diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
new file mode 100644
index 0000000..d45182b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
@@ -0,0 +1,89 @@
+Renesas R-Car CAN FD controller Device Tree Bindings
+----------------------------------------------------
+
+Required properties:
+- compatible: Must contain one or more of the following:
+  - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
+  - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
+
+  When compatible with the generic version, nodes must list the
+  SoC-specific version corresponding to the platform first, followed by the
+  family-specific and/or generic versions.
+
+- reg: physical base address and size of the R-Car CAN FD register map.
+- interrupts: interrupt specifier for the Global & Channel interrupts
+- clocks: phandles and clock specifiers for 3 clock inputs.
+- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
+- pinctrl-0: pin control group to be used for this controller.
+- pinctrl-names: must be "default".
+
+Required child nodes:
+The controller supports two channels and each is represented as a child node.
+The name of the child nodes are "channel0" and "channel1" respectively. Each
+child node supports the "status" property only, which is used to
+enable/disable the respective channel.
+
+Required properties for "renesas,r8a7795-canfd" compatible:
+In R8A7795 SoC, canfd clock is a div6 clock and can be used by both CAN
+and CAN FD controller at the same time. It needs to be scaled to maximum
+frequency if any of these controllers use it. This is done using the
+below properties.
+
+- assigned-clocks: phandle of canfd clock.
+- assigned-clock-rates: maximum frequency of this clock.
+
+Example
+-------
+
+SoC common .dtsi file:
+
+		canfd: can@e66c0000 {
+			compatible = "renesas,r8a7795-canfd",
+				     "renesas,rcar-gen3-canfd";
+			reg = <0 0xe66c0000 0 0x8000>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 914>,
+			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
+			       <&can_clk>;
+			clock-names = "fck", "canfd", "can_clk";
+			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
+			assigned-clock-rates = <40000000>;
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			channel0 {
+				status = "disabled";
+			};
+
+			channel1 {
+				status = "disabled";
+			};
+		};
+
+Board specific .dts file:
+
+E.g. below enables Channel 1 alone in the board.
+
+&canfd {
+        pinctrl-0 = <&canfd1_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+	channel1 {
+		status = "okay";
+	};
+};
+
+E.g. below enables Channel 0 alone in the board using External clock
+as fCAN clock.
+
+&canfd {
+        pinctrl-0 = <&canfd0_pins &can_clk_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+	channel0 {
+		status = "okay";
+	};
+};
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 0d40aef..13003a9 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -152,6 +152,7 @@ source "drivers/net/can/cc770/Kconfig"
 source "drivers/net/can/ifi_canfd/Kconfig"
 source "drivers/net/can/m_can/Kconfig"
 source "drivers/net/can/mscan/Kconfig"
+source "drivers/net/can/rcar/Kconfig"
 source "drivers/net/can/sja1000/Kconfig"
 source "drivers/net/can/softing/Kconfig"
 source "drivers/net/can/spi/Kconfig"
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index e3db0c8..226d5b5 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -10,6 +10,7 @@ can-dev-y			:= dev.o
 
 can-dev-$(CONFIG_CAN_LEDS)	+= led.o
 
+obj-y				+= rcar/
 obj-y				+= spi/
 obj-y				+= usb/
 obj-y				+= softing/
diff --git a/drivers/net/can/rcar/Kconfig b/drivers/net/can/rcar/Kconfig
new file mode 100644
index 0000000..6ea64d1
--- /dev/null
+++ b/drivers/net/can/rcar/Kconfig
@@ -0,0 +1,11 @@
+config CAN_RCAR_CANFD
+	tristate "Renesas R-Car CAN FD controller"
+	depends on ARCH_RENESAS || ARM
+	---help---
+	  Say Y here if you want to use CAN FD controller found on
+	  Renesas R-Car SoCs. The driver puts the controller in CAN FD only
+	  mode, which can interoperate with CAN2.0 nodes but does not support
+	  dedicated CAN 2.0 mode.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called rcar_canfd.
diff --git a/drivers/net/can/rcar/Makefile b/drivers/net/can/rcar/Makefile
new file mode 100644
index 0000000..cbaf498e
--- /dev/null
+++ b/drivers/net/can/rcar/Makefile
@@ -0,0 +1,5 @@
+#
+#  Makefile for the Renesas R-Car CAN FD controller driver
+#
+
+obj-$(CONFIG_CAN_RCAR_CANFD)	+= rcar_canfd.o
diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
new file mode 100644
index 0000000..e198732
--- /dev/null
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -0,0 +1,1624 @@
+/* Renesas R-Car CAN FD device driver
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/* The R-Car CAN FD controller can operate in either one of the below two modes
+ *  - CAN FD only mode
+ *  - Classical CAN (CAN 2.0) only mode
+ *
+ * This driver puts the controller in CAN FD only mode by default. In this
+ * mode, the controller acts as a CAN FD node that can also interoperate with
+ * CAN 2.0 nodes.
+ *
+ * As of now, this driver does not support the Classical CAN (CAN 2.0) mode,
+ * which is handled by a different register map compared to CAN FD only mode.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/netdevice.h>
+#include <linux/platform_device.h>
+#include <linux/can/led.h>
+#include <linux/can/dev.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+
+#define RCANFD_DRV_NAME			"rcar_canfd"
+
+#define RCANFD_FIFO_DEPTH		8	/* Tx FIFO depth */
+#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
+
+#define RCANFD_NUM_CHANNELS		2	/* Two channels max */
+#define RCANFD_CHANNELS_MASK		BIT((RCANFD_NUM_CHANNELS) - 1)
+
+/* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
+ * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
+ * number is added to RFFIFO index.
+ */
+#define RCANFD_RFFIFO_IDX		0
+
+/* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
+ * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
+ */
+#define RCANFD_CFFIFO_IDX		0
+
+/* Global register bits */
+#define RCANFD_GINTF_CANFD		BIT(0)
+
+#define RCANFD_GCFG_TPRI		BIT(0)
+#define RCANFD_GCFG_DCE			BIT(1)
+#define RCANFD_GCFG_DCS			BIT(4)
+#define RCANFD_GCFG_CMPOC		BIT(5)
+#define RCANFD_GCFG_EEFE		BIT(6)
+
+#define RCANFD_GCTR_SLPR		BIT(2)
+#define RCANFD_GCTR_MODEMASK		(0x3)
+#define RCANFD_GCTR_GOPM		(0x0)
+#define RCANFD_GCTR_GRESET		(0x1)
+#define RCANFD_GCTR_GHLT		(0x2)
+
+#define RCANFD_GCTR_DEIE		BIT(8)
+#define RCANFD_GCTR_MEIE		BIT(9)
+#define RCANFD_GCTR_THLEIE		BIT(10)
+#define RCANFD_GCTR_CFMPOFIE		BIT(11)
+#define RCANFD_GCTR_TSRST		BIT(16)
+
+#define RCANFD_GSTS_RAMINIT		BIT(3)
+#define RCANFD_GSTS_SLP			BIT(2)
+#define RCANFD_GSTS_HLT			BIT(1)
+#define RCANFD_GSTS_RESET		BIT(0)
+
+#define RCANFD_GSTS_GNOPM		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+/* Channel register bits */
+#define RCANFD_CCTR_CSLPR		BIT(2)
+#define RCANFD_CCTR_MODEMASK		(0x3)
+#define RCANFD_CCTR_COPM		(0x0)
+#define RCANFD_CCTR_CRESET		(0x1)
+#define RCANFD_CCTR_CHLT		(0x2)
+#define RCANFD_CCTR_CTMASK		(0x3 << 25)
+#define RCANFD_CCTR_CTMS_ILB		(0x3 << 25)
+#define RCANFD_CCTR_CTME		BIT(24)
+#define RCANFD_CCTR_ERRD		BIT(23)
+#define RCANFD_CCTR_BOMMASK		(0x3 << 21)
+#define RCANFD_CCTR_BOM_ENTRY		(0x1 << 21)
+#define RCANFD_CCTR_TDCVFIE		BIT(19)
+#define RCANFD_CCTR_SOCOIE		BIT(18)
+#define RCANFD_CCTR_EOCOIE		BIT(17)
+#define RCANFD_CCTR_TAIE		BIT(16)
+#define RCANFD_CCTR_ALIE		BIT(15)
+#define RCANFD_CCTR_BLIE		BIT(14)
+#define RCANFD_CCTR_OLIE		BIT(13)
+#define RCANFD_CCTR_BORIE		BIT(12)
+#define RCANFD_CCTR_BOEIE		BIT(11)
+#define RCANFD_CCTR_EPIE		BIT(10)
+#define RCANFD_CCTR_EWIE		BIT(9)
+#define RCANFD_CCTR_BEIE		BIT(8)
+
+#define RCANFD_CSTS_COM			BIT(7)
+#define RCANFD_CSTS_REC			BIT(6)
+#define RCANFD_CSTS_TRM			BIT(5)
+#define RCANFD_CSTS_BO			BIT(4)
+#define RCANFD_CSTS_EP			BIT(3)
+#define RCANFD_CSTS_SLP			BIT(2)
+#define RCANFD_CSTS_HALT		BIT(1)
+#define RCANFD_CSTS_RESET		BIT(0)
+
+#define RCANFD_CSTS_TECCNT(x)		(((x) >> 24) & 0xff)
+#define RCANFD_CSTS_RECCNT(x)		(((x) >> 16) & 0xff)
+
+/* Bit Configuration register */
+#define RCANFD_BRP(x)			(((x) & 0x3ff) << 0)
+#define RCANFD_SJW(x)			(((x) & 0x3) << 24)
+#define RCANFD_TSEG1(x)			(((x) & 0xf) << 16)
+#define RCANFD_TSEG2(x)			(((x) & 0x7) << 20)
+
+#define RCANFD_NR_BRP(x)		(((x) & 0x3ff) << 0)
+#define RCANFD_NR_SJW(x)		(((x) & 0x1f) << 11)
+#define RCANFD_NR_TSEG1(x)		(((x) & 0x7f) << 16)
+#define RCANFD_NR_TSEG2(x)		(((x) & 0x1f) << 24)
+
+#define RCANFD_DR_BRP(x)		(((x) & 0xff) << 0)
+#define RCANFD_DR_SJW(x)		(((x) & 0x7) << 24)
+#define RCANFD_DR_TSEG1(x)		(((x) & 0xf) << 16)
+#define RCANFD_DR_TSEG2(x)		(((x) & 0x7) << 20)
+
+/* Global Error flag bits */
+#define RCANFD_GERFL_EEF1		BIT(17)
+#define RCANFD_GERFL_EEF0		BIT(16)
+#define RCANFD_GERFL_CMPOF		BIT(3)
+#define RCANFD_GERFL_THLES		BIT(2)
+#define RCANFD_GERFL_MES		BIT(1)
+#define RCANFD_GERFL_DEF		BIT(0)
+
+#define RCANFD_GERFL_ERR(x)		((x) & (RCANFD_GERFL_EEF1 |\
+						RCANFD_GERFL_EEF0 |\
+						RCANFD_GERFL_MES |\
+						RCANFD_GERFL_CMPOF))
+
+/* Channel Error flag bits */
+#define RCANFD_CERFL_ADEF		BIT(14)
+#define RCANFD_CERFL_B0EF		BIT(13)
+#define RCANFD_CERFL_B1EF		BIT(12)
+#define RCANFD_CERFL_CEF		BIT(11)
+#define RCANFD_CERFL_AEF		BIT(10)
+#define RCANFD_CERFL_FEF		BIT(9)
+#define RCANFD_CERFL_SEF		BIT(8)
+#define RCANFD_CERFL_ALEF		BIT(7)
+#define RCANFD_CERFL_BLEF		BIT(6)
+#define RCANFD_CERFL_OLEF		BIT(5)
+#define RCANFD_CERFL_BOREF		BIT(4)
+#define RCANFD_CERFL_BOEEF		BIT(3)
+#define RCANFD_CERFL_EPEF		BIT(2)
+#define RCANFD_CERFL_EWEF		BIT(1)
+#define RCANFD_CERFL_BEF		BIT(0)
+
+#define RCANFD_CERFL_ERR(x)		((x) & (0x7fff)) /* above bits 14:0 */
+
+/* CAN FD specific registers */
+#define RCANFD_DCFG_TDCE		BIT(9)
+#define RCANFD_DCFG_TDCOC		BIT(8)
+#define RCANFD_DCFG_TDCO(x)		(((x) & 0x7f) >> 16)
+
+#define RCANFD_DCSTS_TDCR(x)		(((x) >> 0) & 0x7f)
+#define RCANFD_DCSTS_SOCCNT(x)		(((x) >> 24) & 0xff)
+#define RCANFD_DCSTS_EOCCNT(x)		(((x) >> 16) & 0xff)
+
+#define RCANFD_DCSTS_TDCVF		BIT(7)
+#define RCANFD_DCSTS_EOCO		BIT(8)
+#define RCANFD_DCSTS_SOCO		BIT(9)
+
+/* Rx FIFO bits */
+#define RCANFD_RFFIFO_RFIF		BIT(3)
+#define RCANFD_RFFIFO_RFMLT		BIT(2)
+#define RCANFD_RFFIFO_RFFLL		BIT(1)
+#define RCANFD_RFFIFO_RFEMP		BIT(0)
+
+#define RCANFD_RFFIFO_RFESI		BIT(0)
+#define RCANFD_RFFIFO_RFBRS		BIT(1)
+#define RCANFD_RFFIFO_RFFDF		BIT(2)
+
+#define RCANFD_RFFIFO_RFIDE		BIT(31)
+#define RCANFD_RFFIFO_RFRTR		BIT(30)
+
+#define RCANFD_RFFIFO_RFDLC(x)		(((x) >> 28) & 0xf)
+#define RCANFD_RFFIFO_RFPTR(x)		(((x) >> 16) & 0xfff)
+#define RCANFD_RFFIFO_RFTS(x)		(((x) >> 0) & 0xff)
+
+#define RCANFD_RFFIFO_RFIM		BIT(12)
+#define RCANFD_RFFIFO_RFDC(x)		(((x) & 0x7) << 8)
+#define RCANFD_RFFIFO_RFPLS(x)		(((x) & 0x7) << 4)
+#define RCANFD_RFFIFO_RFIE		BIT(1)
+#define RCANFD_RFFIFO_RFE		BIT(0)
+
+/* Common FIFO bits */
+#define RCANFD_CMFIFO_TML(x)		(((x) & 0xf) << 20)
+#define RCANFD_CMFIFO_M(x)		(((x) & 0x3) << 16)
+#define RCANFD_CMFIFO_CFIM		BIT(12)
+#define RCANFD_CMFIFO_DC(x)		(((x) & 0x7) << 8)
+#define RCANFD_CMFIFO_PLS(x)		(((x) & 0x7) << 4)
+#define RCANFD_CMFIFO_CFTXIE		BIT(2)
+#define RCANFD_CMFIFO_CFE		BIT(0)
+
+#define RCANFD_CMFIFO_CFTXIF		BIT(4)
+#define RCANFD_CMFIFO_CFMLT		BIT(2)
+#define RCANFD_CMFIFO_CFFLL		BIT(1)
+#define RCANFD_CMFIFO_CFEMP		BIT(0)
+#define RCANFD_CMFIFO_CFMC(x)		(((x) >> 8) & 0xff)
+
+#define RCANFD_CMFIFO_CFESI		BIT(0)
+#define RCANFD_CMFIFO_CFBRS		BIT(1)
+#define RCANFD_CMFIFO_CFFDF		BIT(2)
+
+#define RCANFD_CMFIFO_CFIDE		BIT(31)
+#define RCANFD_CMFIFO_CFRTR		BIT(30)
+#define RCANFD_CMFIFO_CFID(x)		((x) & 0x1fffffff)
+
+#define RCANFD_CMFIFO_CFDLC(x)		(((x) & 0xf) << 28)
+#define RCANFD_CMFIFO_CFPTR(x)		(((x) & 0xfff) << 16)
+#define RCANFD_CMFIFO_CFTS(x)		(((x) & 0xff) << 0)
+
+/* Global Test Config register */
+#define RCANFD_GTSTCFG_C0CBCE		BIT(0)
+#define RCANFD_GTSTCFG_C1CBCE		BIT(1)
+
+#define RCANFD_GTSTCTR_ICBCTME		BIT(0)
+
+/* AFL Rx rules registers */
+#define RCANFD_AFLCFG_SETRNC(n, x)	(((x) & 0xff) << (24 - n * 8))
+#define RCANFD_AFLCFG_GETRNC(n, x)	(((x) >> (24 - n * 8)) & 0xff)
+
+#define RCANFD_AFL_PAGENUM(entry)	((entry) / 16)
+
+#define RCANFD_AFLCTR_AFLDAE		BIT(8)
+#define RCANFD_AFLCTR_AFLPN(x)		((x) & 0x1f)
+#define RCANFD_CHANNEL_NUMRULES		1	/* only one rule per channel */
+#define RCANFD_AFLID_GAFLLB		BIT(29)
+#define RCANFD_AFLPTR1_RFFIFO(x)	(1 << (x))
+
+/* Common register map offsets */
+
+/* Nominal rate registers */
+#define RCANFD_CCFG(m)			(0x0000 + (0x10 * (m)))
+#define RCANFD_CCTR(m)			(0x0004 + (0x10 * (m)))
+#define RCANFD_CSTS(m)			(0x0008 + (0x10 * (m)))
+#define RCANFD_CERFL(m)			(0x000C + (0x10 * (m)))
+
+/* Global registers */
+#define RCANFD_GCFG			(0x0084)
+#define RCANFD_GCTR			(0x0088)
+#define RCANFD_GSTS			(0x008c)
+#define RCANFD_GERFL			(0x0090)
+#define RCANFD_GTSC			(0x0094)
+#define RCANFD_GAFLECTR			(0x0098)
+#define RCANFD_GAFLCFG0			(0x009c)
+#define RCANFD_GAFLCFG1			(0x00a0)
+#define RCANFD_RMNB			(0x00a4)
+
+#define RCANFD_RMND(y)			(0x00a8 + (0x04 * (y)))
+
+/* Rx FIFO Control registers */
+#define RCANFD_RFCC(x)			(0x00b8 + (0x04 * (x)))
+#define RCANFD_RFSTS(x)			(0x00d8 + (0x04 * (x)))
+#define RCANFD_RFPCTR(x)		(0x00f8 + (0x04 * (x)))
+
+/* Common FIFO Control registers */
+#define RCANFD_CFCC(ch, idx)		(0x0118 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+#define RCANFD_CFSTS(ch, idx)		(0x0178 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+#define RCANFD_CFPCTR(ch, idx)		(0x01d8 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+
+#define RCANFD_FESTS			(0x0238)
+#define RCANFD_FFSTS			(0x023c)
+#define RCANFD_FMSTS			(0x0240)
+#define RCANFD_RFISTS			(0x0244)
+#define RCANFD_CFRISTS			(0x0248)
+#define RCANFD_CFTISTS			(0x024c)
+
+#define RCANFD_TMC(p)			(0x0250 + (0x01 * (p)))
+#define RCANFD_TMSTS(p)			(0x02d0 + (0x01 * (p)))
+
+#define RCANFD_TMTRSTS(y)		(0x0350 + (0x04 * (y)))
+#define RCANFD_TMTARSTS(y)		(0x0360 + (0x04 * (y)))
+#define RCANFD_TMTCSTS(y)		(0x0370 + (0x04 * (y)))
+#define RCANFD_TMTASTS(y)		(0x0380 + (0x04 * (y)))
+#define RCANFD_TMIEC(y)			(0x0390 + (0x04 * (y)))
+
+#define RCANFD_TXQCC(m)			(0x03a0 + (0x04 * (m)))
+#define RCANFD_TXQSTS(m)		(0x03c0 + (0x04 * (m)))
+#define RCANFD_TXQPCTR(m)		(0x03e0 + (0x04 * (m)))
+
+#define RCANFD_THLCC(m)			(0x0400 + (0x04 * (m)))
+#define RCANFD_THLSTS(m)		(0x0420 + (0x04 * (m)))
+#define RCANFD_THLPCTR(m)		(0x0440 + (0x04 * (m)))
+
+#define RCANFD_GTINTSTS0		(0x0460)
+#define RCANFD_GTINTSTS1		(0x0464)
+#define RCANFD_GTSTCFG			(0x0468)
+#define RCANFD_GTSTCTR			(0x046c)
+#define RCANFD_GLOCKK			(0x047c)
+#define RCANFD_GRMCFG			(0x04fc)
+
+/* Receive rule registers */
+#define RCANFD_GAFLID(offset, j)	((offset) + (0x10 * (j)))
+#define RCANFD_GAFLM(offset, j)		((offset) + 0x04 + (0x10 * (j)))
+#define RCANFD_GAFLP0(offset, j)	((offset) + 0x08 + (0x10 * (j)))
+#define RCANFD_GAFLP1(offset, j)	((offset) + 0x0c + (0x10 * (j)))
+
+/* CAN FD mode specific regsiter map */
+
+/* Data bitrate registers */
+#define RCANFD_F_CDFG(m)		(0x0500 + (0x20 * (m)))
+#define RCANFD_F_CFDCFG(m)		(0x0504 + (0x20 * (m)))
+#define RCANFD_F_CFDCTR(m)		(0x0508 + (0x20 * (m)))
+#define RCANFD_F_CFDSTS(m)		(0x050c + (0x20 * (m)))
+#define RCANFD_F_CFDCRC(m)		(0x0510 + (0x20 * (m)))
+
+#define RCANFD_F_GAFL_OFFSET		(0x1000)
+
+#define RCANFD_F_RMID(q)		(0x2000 + (0x10 * (q)))
+#define RCANFD_F_RMPTR(q)		(0x2004 + (0x10 * (q)))
+#define RCANFD_F_RMFDSTS(q)		(0x2008 + (0x10 * (q)))
+#define RCANFD_F_RMDF(q, b)		(0x200c + (0x04 * (b)) + (0x20 * (q)))
+
+/* Rx FIFO data registers */
+#define RCANFD_F_RFOFFSET		(0x3000)
+#define RCANFD_F_RFID(x)		(RCANFD_F_RFOFFSET + (0x80 * (x)))
+#define RCANFD_F_RFPTR(x)		(RCANFD_F_RFOFFSET + 0x04 + \
+					 (0x80 * (x)))
+#define RCANFD_F_RFFDSTS(x)		(RCANFD_F_RFOFFSET + 0x08 + \
+					 (0x80 * (x)))
+#define RCANFD_F_RFDF(x, df)		(RCANFD_F_RFOFFSET + 0x0c + \
+					 (0x80 * (x)) + (0x04 * (df)))
+
+/* Common FIFO data registers */
+#define RCANFD_F_CFOFFSET		(0x3400)
+#define RCANFD_F_CFID(ch, idx)		(RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
+					 (0x80 * (idx)))
+#define RCANFD_F_CFPTR(ch, idx)		(RCANFD_F_CFOFFSET + 0x04 + \
+					 (0x180 * (ch)) + (0x80 * (idx)))
+#define RCANFD_F_CFFDCSTS(ch, idx)	(RCANFD_F_CFOFFSET + 0x08 + \
+					 (0x180 * (ch)) + (0x80 * (idx)))
+#define RCANFD_F_CFDF(ch, idx, df)	(RCANFD_F_CFOFFSET + 0x0c + \
+					 (0x180 * (ch)) + (0x80 * (idx)) + \
+					 (0x04 * (df)))
+
+#define RCANFD_F_TMID(p)		(0x4000 + (0x20 * (p)))
+#define RCANFD_F_TMPTR(p)		(0x4004 + (0x20 * (p)))
+#define RCANFD_F_TMFDCTR(p)		(0x4008 + (0x20 * (p)))
+#define RCANFD_F_TMDF(p, b)		(0x400c + (0x20 * (p)) + (0x04 * (b)))
+
+#define RCANFD_F_THLACC(m)		(0x6000 + (0x04 * (m)))
+#define RCANFD_F_RPGACC(r)		(0x6400 + (0x04 * (r)))
+
+/* fCAN clock select register settings */
+enum rcar_canfd_fcanclk {
+	RCANFD_CANFDCLK = 0,		/* CANFD clock */
+	RCANFD_EXTCLK,			/* Externally input clock */
+};
+
+struct rcar_canfd_global;
+
+/* Channel priv data */
+struct rcar_canfd_channel {
+	struct can_priv can;			/* Must be the first member */
+	struct net_device *ndev;
+	struct rcar_canfd_global *gpriv;	/* Controller reference */
+	void __iomem *base;			/* Register base address */
+	struct napi_struct napi;
+	u8  tx_len[RCANFD_FIFO_DEPTH];		/* For net stats */
+	u32 tx_head;				/* Incremented on xmit */
+	u32 tx_tail;				/* Incremented on xmit done */
+	u32 channel;				/* Channel number */
+	spinlock_t tx_lock;			/* To protect tx path */
+};
+
+/* Global priv data */
+struct rcar_canfd_global {
+	struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
+	void __iomem *base;		/* Register base address */
+	struct platform_device *pdev;	/* Respective platform device */
+	struct clk *clkp;		/* Peripheral clock */
+	struct clk *can_clk;		/* fCAN clock */
+	enum rcar_canfd_fcanclk fcan;	/* CANFD or Ext clock */
+	unsigned long channels_mask;	/* Enabled channels mask */
+};
+
+/* CAN FD mode nominal rate constants */
+static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
+	.name = RCANFD_DRV_NAME,
+	.tseg1_min = 2,
+	.tseg1_max = 128,
+	.tseg2_min = 2,
+	.tseg2_max = 32,
+	.sjw_max = 32,
+	.brp_min = 1,
+	.brp_max = 1024,
+	.brp_inc = 1,
+};
+
+/* CAN FD mode data rate constants */
+static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
+	.name = RCANFD_DRV_NAME,
+	.tseg1_min = 2,
+	.tseg1_max = 16,
+	.tseg2_min = 2,
+	.tseg2_max = 8,
+	.sjw_max = 8,
+	.brp_min = 1,
+	.brp_max = 256,
+	.brp_inc = 1,
+};
+
+/* Helper functions */
+static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
+{
+	u32 data = readl(reg);
+
+	data &= ~mask;
+	data |= (val & mask);
+	writel(data, reg);
+}
+
+static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
+{
+	return readl(base + (offset));
+}
+
+static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
+{
+	writel(val, base + (offset));
+}
+
+static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
+{
+	rcar_canfd_update(val, val, base + (reg));
+}
+
+static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
+{
+	rcar_canfd_update(val, 0, base + (reg));
+}
+
+static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
+				  u32 mask, u32 val)
+{
+	rcar_canfd_update(mask, val, base + (reg));
+}
+
+static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
+				struct canfd_frame *cf, u32 off)
+{
+	u32 i, lwords;
+
+	lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
+	for (i = 0; i < lwords; i++)
+		*((u32 *)cf->data + i) =
+			rcar_canfd_read(priv->base, off + (i * sizeof(u32)));
+}
+
+static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
+				struct canfd_frame *cf, u32 off)
+{
+	u32 i, lwords;
+
+	lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
+	for (i = 0; i < lwords; i++)
+		rcar_canfd_write(priv->base, off + (i * sizeof(u32)),
+				 *((u32 *)cf->data + i));
+}
+
+static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
+{
+	u32 i;
+
+	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
+		can_free_echo_skb(ndev, i);
+}
+
+static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
+{
+	u32 sts, ch;
+	int err;
+
+	/* Check RAMINIT flag as CAN RAM initialization takes place
+	 * after the MCU reset
+	 */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 !(sts & RCANFD_GSTS_RAMINIT), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
+		return err;
+	}
+
+	/* Transition to Global Reset mode */
+	rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_SLPR);
+	rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
+			      RCANFD_GCTR_MODEMASK, RCANFD_GCTR_GRESET);
+
+	/* Ensure Global reset mode */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 (sts & RCANFD_GSTS_RESET), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
+		return err;
+	}
+
+	/* Reset Global error flags */
+	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
+
+	/* Set the controller into FD mode */
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG, RCANFD_GINTF_CANFD);
+
+	/* Transition all Channels to reset mode */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_clear_bit(gpriv->base,
+				     RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
+
+		rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
+				      RCANFD_CCTR_MODEMASK,
+				      RCANFD_CCTR_CRESET);
+
+		/* Ensure Channel reset mode */
+		err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
+					 (sts & RCANFD_CSTS_RESET), 2, 500000);
+		if (err) {
+			dev_dbg(&gpriv->pdev->dev,
+				"channel %u reset failed\n", ch);
+			return err;
+		}
+	}
+	return 0;
+}
+
+static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
+{
+	u32 cfg, ch;
+
+	/* Global Configuration settings */
+	cfg = RCANFD_GCFG_EEFE;		/* ECC error flag enabled */
+
+	/* Set External Clock if selected */
+	if (gpriv->fcan != RCANFD_CANFDCLK)
+		cfg |= RCANFD_GCFG_DCS;
+
+	/* Truncate payload to configured message size RFPLS */
+	cfg |= RCANFD_GCFG_CMPOC;
+
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
+
+	/* Channel configuration settings */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
+				   RCANFD_CCTR_ERRD);
+		rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
+				      RCANFD_CCTR_BOMMASK,
+				      RCANFD_CCTR_BOM_ENTRY);
+	}
+}
+
+static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
+					   u32 ch)
+{
+	u32 cfg;
+	int start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	if (ch == 0) {
+		start = 0; /* Channel 0 always starts from 0th rule */
+	} else {
+		/* Get number of Channel 0 rules and adjust */
+		cfg = rcar_canfd_read(gpriv->base, RCANFD_GAFLCFG0);
+		start = RCANFD_AFLCFG_GETRNC(0, cfg);
+	}
+
+	/* Enable write access to entry */
+	page = RCANFD_AFL_PAGENUM(start);
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
+			   (RCANFD_AFLCTR_AFLPN(page) | RCANFD_AFLCTR_AFLDAE));
+
+	/* Write number of rules for channel */
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG0,
+			   RCANFD_AFLCFG_SETRNC(ch, num_rules));
+
+	/* Accept all IDs */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_GAFLID(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* IDE or RTR is not considered for matching */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_GAFLM(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* Any data length accepted */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_GAFLP0(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* Place the msg in corresponding Rx FIFO entry */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_GAFLP1(RCANFD_F_GAFL_OFFSET, start),
+			 RCANFD_AFLPTR1_RFFIFO(ridx));
+
+	/* Disable write access to page */
+	rcar_canfd_clear_bit(gpriv->base,
+			     RCANFD_GAFLECTR, RCANFD_AFLCTR_AFLDAE);
+}
+
+static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	/* Rx FIFO is used for reception */
+	u32 cfg;
+	u16 rfdc, rfpls;
+
+	/* Select Rx FIFO based on channel */
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	rfdc = 2;		/* b010 - 8 messages Rx FIFO depth */
+	rfpls = 7;		/* b111 - Max 64 bytes payload */
+
+	cfg = (RCANFD_RFFIFO_RFIM | RCANFD_RFFIFO_RFDC(rfdc) |
+		RCANFD_RFFIFO_RFPLS(rfpls) | RCANFD_RFFIFO_RFIE);
+	rcar_canfd_write(gpriv->base, RCANFD_RFCC(ridx), cfg);
+}
+
+static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	/* Tx/Rx(Common) FIFO configured in Tx mode is
+	 * used for transmission
+	 *
+	 * Each channel has 3 Common FIFO dedicated to them.
+	 * Use the 1st (index 0) out of 3
+	 */
+	u32 cfg;
+	u16 cftml, cfm, cfdc, cfpls;
+
+	cftml = 0;		/* 0th buffer */
+	cfm = 1;		/* b01 - Transmit mode */
+	cfdc = 2;		/* b010 - 8 messages Tx FIFO depth */
+	cfpls = 7;		/* b111 - Max 64 bytes payload */
+
+	cfg = (RCANFD_CMFIFO_TML(cftml) | RCANFD_CMFIFO_M(cfm) |
+		RCANFD_CMFIFO_CFIM | RCANFD_CMFIFO_DC(cfdc) |
+		RCANFD_CMFIFO_PLS(cfpls) | RCANFD_CMFIFO_CFTXIE);
+	rcar_canfd_write(gpriv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
+
+	/* Clear FD mode specific control/status register */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
+}
+
+static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
+{
+	u32 ctr;
+
+	/* Clear any stray error interrupt flags */
+	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
+
+	/* Global interrupts setup */
+	ctr = RCANFD_GCTR_MEIE;
+	ctr |= RCANFD_GCTR_CFMPOFIE;
+
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
+}
+
+static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
+						 *gpriv)
+{
+	/* Disable all interrupts */
+	rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
+
+	/* Clear any stray error interrupt flags */
+	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
+}
+
+static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
+						 *priv)
+{
+	u32 ctr, ch = priv->channel;
+
+	/* Clear any stray error flags */
+	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
+
+	/* Channel interrupts setup */
+	ctr = (RCANFD_CCTR_TAIE |
+	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
+	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
+	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
+	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
+	rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
+}
+
+static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
+						  *priv)
+{
+	u32 ctr, ch = priv->channel;
+
+	ctr = (RCANFD_CCTR_TAIE |
+	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
+	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
+	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
+	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
+	rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
+
+	/* Clear any stray error flags */
+	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
+}
+
+static void rcar_canfd_global_error(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 ch = priv->channel;
+	u32 gerfl, sts;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
+	if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
+		netdev_dbg(ndev, "Ch0: ECC Error flag\n");
+		stats->tx_dropped++;
+	}
+	if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
+		netdev_dbg(ndev, "Ch1: ECC Error flag\n");
+		stats->tx_dropped++;
+	}
+	if (gerfl & RCANFD_GERFL_MES) {
+		sts = rcar_canfd_read(priv->base,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		if (sts & RCANFD_CMFIFO_CFMLT) {
+			netdev_dbg(ndev, "Tx Message Lost flag\n");
+			stats->tx_dropped++;
+			rcar_canfd_write(priv->base,
+					 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
+					 sts & ~RCANFD_CMFIFO_CFMLT);
+		}
+
+		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
+		if (sts & RCANFD_RFFIFO_RFMLT) {
+			netdev_dbg(ndev, "Rx Message Lost flag\n");
+			stats->rx_dropped++;
+			rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
+					 sts & ~RCANFD_RFFIFO_RFMLT);
+		}
+	}
+	if (gerfl & RCANFD_GERFL_CMPOF) {
+		/* Message Lost flag will be set for respective channel
+		 * when this condition happens with counters and flags
+		 * already updated.
+		 */
+		netdev_dbg(ndev, "global payload overflow interrupt\n");
+	}
+
+	/* Clear all global error interrupts. Only affected channels bits
+	 * get cleared
+	 */
+	rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
+}
+
+static void rcar_canfd_error(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	struct can_frame *cf;
+	struct sk_buff *skb;
+	u32 cerfl, csts;
+	u32 txerr = 0, rxerr = 0;
+	u32 ch = priv->channel;
+
+	/* Propagate the error condition to the CAN stack */
+	skb = alloc_can_err_skb(ndev, &cf);
+	if (!skb) {
+		stats->rx_dropped++;
+		return;
+	}
+
+	/* Channel error interrupt */
+	cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
+	csts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
+	txerr = RCANFD_CSTS_TECCNT(csts);
+	rxerr = RCANFD_CSTS_RECCNT(csts);
+
+	netdev_dbg(ndev, "ch erfl %x sts %x txerr %u rxerr %u\n",
+		   cerfl, csts, txerr, rxerr);
+
+	if (cerfl & RCANFD_CERFL_BEF) {
+		netdev_dbg(ndev, "Bus error\n");
+		cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
+		cf->data[2] = CAN_ERR_PROT_UNSPEC;
+		priv->can.can_stats.bus_error++;
+	}
+	if (cerfl & RCANFD_CERFL_ADEF) {
+		netdev_dbg(ndev, "ACK Delimiter Error\n");
+		stats->tx_errors++;
+		cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
+	}
+	if (cerfl & RCANFD_CERFL_B0EF) {
+		netdev_dbg(ndev, "Bit Error (dominant)\n");
+		stats->tx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_BIT0;
+	}
+	if (cerfl & RCANFD_CERFL_B1EF) {
+		netdev_dbg(ndev, "Bit Error (recessive)\n");
+		stats->tx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_BIT1;
+	}
+	if (cerfl & RCANFD_CERFL_CEF) {
+		netdev_dbg(ndev, "CRC Error\n");
+		stats->rx_errors++;
+		cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
+	}
+	if (cerfl & RCANFD_CERFL_AEF) {
+		netdev_dbg(ndev, "ACK Error\n");
+		stats->tx_errors++;
+		cf->can_id |= CAN_ERR_ACK;
+		cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
+	}
+	if (cerfl & RCANFD_CERFL_FEF) {
+		netdev_dbg(ndev, "Form Error\n");
+		stats->rx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_FORM;
+	}
+	if (cerfl & RCANFD_CERFL_SEF) {
+		netdev_dbg(ndev, "Stuff Error\n");
+		stats->rx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_STUFF;
+	}
+	if (cerfl & RCANFD_CERFL_ALEF) {
+		netdev_dbg(ndev, "Arbitration lost Error\n");
+		priv->can.can_stats.arbitration_lost++;
+		cf->can_id |= CAN_ERR_LOSTARB;
+		cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
+	}
+	if (cerfl & RCANFD_CERFL_BLEF) {
+		netdev_dbg(ndev, "Bus Lock Error\n");
+		stats->rx_errors++;
+		cf->can_id |= CAN_ERR_BUSERROR;
+	}
+	if (cerfl & RCANFD_CERFL_EWEF) {
+		netdev_dbg(ndev, "Error warning interrupt\n");
+		priv->can.state = CAN_STATE_ERROR_WARNING;
+		priv->can.can_stats.error_warning++;
+		cf->can_id |= CAN_ERR_CRTL;
+		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
+			CAN_ERR_CRTL_RX_WARNING;
+		cf->data[6] = txerr;
+		cf->data[7] = rxerr;
+	}
+	if (cerfl & RCANFD_CERFL_EPEF) {
+		netdev_dbg(ndev, "Error passive interrupt\n");
+		priv->can.state = CAN_STATE_ERROR_PASSIVE;
+		priv->can.can_stats.error_passive++;
+		cf->can_id |= CAN_ERR_CRTL;
+		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
+			CAN_ERR_CRTL_RX_PASSIVE;
+		cf->data[6] = txerr;
+		cf->data[7] = rxerr;
+	}
+	if (cerfl & RCANFD_CERFL_BOEEF) {
+		netdev_dbg(ndev, "Bus-off entry interrupt\n");
+		rcar_canfd_tx_failure_cleanup(ndev);
+		priv->can.state = CAN_STATE_BUS_OFF;
+		priv->can.can_stats.bus_off++;
+		can_bus_off(ndev);
+		cf->can_id |= CAN_ERR_BUSOFF;
+	}
+	if (cerfl & RCANFD_CERFL_OLEF) {
+		netdev_dbg(ndev,
+			   "Overload Frame Transmission error interrupt\n");
+		stats->tx_errors++;
+		cf->can_id |= CAN_ERR_PROT;
+		cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
+	}
+
+	/* Clear all channel error interrupts */
+	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
+	stats->rx_packets++;
+	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
+}
+
+static void rcar_canfd_tx_done(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 sts;
+	unsigned long flags;
+	u32 ch = priv->channel;
+
+	do {
+		u8 unsent, sent;
+
+		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
+		stats->tx_packets++;
+		stats->tx_bytes += priv->tx_len[sent];
+		priv->tx_len[sent] = 0;
+		can_get_echo_skb(ndev, sent);
+
+		spin_lock_irqsave(&priv->tx_lock, flags);
+		priv->tx_tail++;
+		sts = rcar_canfd_read(priv->base,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		unsent = RCANFD_CMFIFO_CFMC(sts);
+
+		/* Wake producer only when there is room */
+		if (unsent != RCANFD_FIFO_DEPTH)
+			netif_wake_queue(ndev);
+
+		if (priv->tx_head - priv->tx_tail <= unsent) {
+			spin_unlock_irqrestore(&priv->tx_lock, flags);
+			break;
+		}
+		spin_unlock_irqrestore(&priv->tx_lock, flags);
+
+	} while (1);
+
+	/* Clear interrupt */
+	rcar_canfd_write(priv->base, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
+			 sts & ~RCANFD_CMFIFO_CFTXIF);
+	can_led_event(ndev, CAN_LED_EVENT_TX);
+}
+
+static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
+{
+	struct rcar_canfd_global *gpriv = dev_id;
+	struct net_device *ndev;
+	struct rcar_canfd_channel *priv;
+	u32 sts, gerfl;
+	u32 ch, ridx;
+
+	/* Global error interrupts still indicate a condition specific
+	 * to a channel. RxFIFO interrupt is a global interrupt.
+	 */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		ndev = priv->ndev;
+		ridx = ch + RCANFD_RFFIFO_IDX;
+
+		/* Global error interrupts */
+		gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
+		if (RCANFD_GERFL_ERR(gerfl))
+			rcar_canfd_global_error(ndev);
+
+		/* Handle Rx interrupts */
+		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
+		if (sts & RCANFD_RFFIFO_RFIF) {
+			if (napi_schedule_prep(&priv->napi)) {
+				/* Disable Rx FIFO interrupts */
+				rcar_canfd_clear_bit(priv->base,
+						     RCANFD_RFCC(ridx),
+						     RCANFD_RFFIFO_RFIE);
+				__napi_schedule(&priv->napi);
+			}
+		}
+	}
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
+{
+	struct rcar_canfd_global *gpriv = dev_id;
+	struct net_device *ndev;
+	struct rcar_canfd_channel *priv;
+	u32 sts, cerfl, ch;
+
+	/* Common FIFO is a per channel resource */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		ndev = priv->ndev;
+
+		/* Channel error interrupts */
+		cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
+		if (RCANFD_CERFL_ERR(cerfl))
+			rcar_canfd_error(ndev);
+
+		/* Handle Tx interrupts */
+		sts = rcar_canfd_read(priv->base,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		if (sts & RCANFD_CMFIFO_CFTXIF)
+			rcar_canfd_tx_done(ndev);
+	}
+	return IRQ_HANDLED;
+}
+
+static void rcar_canfd_set_bittiming(struct net_device *dev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(dev);
+	const struct can_bittiming *bt = &priv->can.bittiming;
+	const struct can_bittiming *dbt = &priv->can.data_bittiming;
+	u16 brp, sjw, tseg1, tseg2;
+	u32 cfg;
+	u32 ch = priv->channel;
+
+	/* Nominal bit timing settings */
+	brp = bt->brp - 1;
+	sjw = bt->sjw - 1;
+	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
+	tseg2 = bt->phase_seg2 - 1;
+
+	cfg = (RCANFD_NR_TSEG1(tseg1) | RCANFD_NR_BRP(brp) |
+	       RCANFD_NR_SJW(sjw) | RCANFD_NR_TSEG2(tseg2));
+
+	rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
+	netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
+		   brp, sjw, tseg1, tseg2);
+
+	/* Data bit timing settings */
+	brp = dbt->brp - 1;
+	sjw = dbt->sjw - 1;
+	tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
+	tseg2 = dbt->phase_seg2 - 1;
+
+	cfg = (RCANFD_DR_TSEG1(tseg1) | RCANFD_DR_BRP(brp) |
+	       RCANFD_DR_SJW(sjw) | RCANFD_DR_TSEG2(tseg2));
+
+	rcar_canfd_write(priv->base, RCANFD_F_CDFG(ch), cfg);
+	netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
+		   brp, sjw, tseg1, tseg2);
+}
+
+static int rcar_canfd_start(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	int err = -EOPNOTSUPP;
+	u32 sts, ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	rcar_canfd_set_bittiming(ndev);
+
+	rcar_canfd_enable_channel_interrupts(priv);
+
+	/* Set channel to Operational mode */
+	rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_COPM);
+
+	/* Verify channel mode change */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_COM), 2, 500000);
+	if (err) {
+		netdev_err(ndev, "channel %u communication state failed\n", ch);
+		goto fail_mode_change;
+	}
+
+	/* Enable Common & Rx FIFO */
+	rcar_canfd_set_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
+			   RCANFD_CMFIFO_CFE);
+	rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFE);
+
+	priv->can.state = CAN_STATE_ERROR_ACTIVE;
+	return 0;
+
+fail_mode_change:
+	rcar_canfd_disable_channel_interrupts(priv);
+	return err;
+}
+
+static int rcar_canfd_open(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct rcar_canfd_global *gpriv = priv->gpriv;
+	int err;
+
+	/* Peripheral clock is already enabled in probe */
+	err = clk_prepare_enable(gpriv->can_clk);
+	if (err) {
+		netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
+		goto out_clock;
+	}
+
+	err = open_candev(ndev);
+	if (err) {
+		netdev_err(ndev, "open_candev() failed, error %d\n", err);
+		goto out_can_clock;
+	}
+
+	napi_enable(&priv->napi);
+	err = rcar_canfd_start(ndev);
+	if (err)
+		goto out_close;
+	netif_start_queue(ndev);
+	can_led_event(ndev, CAN_LED_EVENT_OPEN);
+	return 0;
+out_close:
+	napi_disable(&priv->napi);
+	close_candev(ndev);
+out_can_clock:
+	clk_disable_unprepare(gpriv->can_clk);
+out_clock:
+	return err;
+}
+
+static void rcar_canfd_stop(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	int err;
+	u32 sts, ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	/* Transition to channel reset mode  */
+	rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_MODEMASK, RCANFD_CCTR_CRESET);
+
+	/* Check Channel reset mode */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_RESET), 2, 500000);
+	if (err)
+		netdev_err(ndev, "channel %u reset failed\n", ch);
+
+	rcar_canfd_disable_channel_interrupts(priv);
+
+	/* Disable Common & Rx FIFO */
+	rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
+			     RCANFD_CMFIFO_CFE);
+	rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFFIFO_RFE);
+
+	/* Set the state as STOPPED */
+	priv->can.state = CAN_STATE_STOPPED;
+}
+
+static int rcar_canfd_close(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct rcar_canfd_global *gpriv = priv->gpriv;
+
+	netif_stop_queue(ndev);
+	rcar_canfd_stop(ndev);
+	napi_disable(&priv->napi);
+	clk_disable_unprepare(gpriv->can_clk);
+	close_candev(ndev);
+	can_led_event(ndev, CAN_LED_EVENT_STOP);
+	return 0;
+}
+
+static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
+					 struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
+	u32 sts = 0, id, dlc;
+	unsigned long flags;
+	u32 ch = priv->channel;
+
+	if (can_dropped_invalid_skb(ndev, skb))
+		return NETDEV_TX_OK;
+
+	if (cf->can_id & CAN_EFF_FLAG) {
+		id = cf->can_id & CAN_EFF_MASK;
+		id |= RCANFD_CMFIFO_CFIDE;
+	} else {
+		id = cf->can_id & CAN_SFF_MASK;
+	}
+
+	if (cf->can_id & CAN_RTR_FLAG)
+		id |= RCANFD_CMFIFO_CFRTR;
+
+	rcar_canfd_write(priv->base,
+			 RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX), id);
+	dlc = RCANFD_CMFIFO_CFDLC(can_len2dlc(cf->len));
+	rcar_canfd_write(priv->base,
+			 RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
+
+	if (can_is_canfd_skb(skb)) {
+		/* CAN FD frame format */
+		sts |= RCANFD_CMFIFO_CFFDF;
+		if (cf->flags & CANFD_BRS)
+			sts |= RCANFD_CMFIFO_CFBRS;
+
+		if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
+			sts |= RCANFD_CMFIFO_CFESI;
+	}
+
+	rcar_canfd_write(priv->base, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX),
+			 sts);
+
+	rcar_canfd_put_data(priv, cf,
+			    RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
+
+	priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
+	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
+
+	spin_lock_irqsave(&priv->tx_lock, flags);
+	priv->tx_head++;
+
+	/* Stop the queue if we've filled all FIFO entries */
+	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
+		netif_stop_queue(ndev);
+
+	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
+	 * pointer for the Common FIFO
+	 */
+	rcar_canfd_write(priv->base,
+			 RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
+
+	spin_unlock_irqrestore(&priv->tx_lock, flags);
+	return NETDEV_TX_OK;
+}
+
+static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
+{
+	struct net_device_stats *stats = &priv->ndev->stats;
+	struct canfd_frame *cf;
+	struct sk_buff *skb;
+	u32 sts = 0, id, ptr;
+	u32 ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	id = rcar_canfd_read(priv->base, RCANFD_F_RFID(ridx));
+	ptr = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(ridx));
+
+	sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(ridx));
+	if (sts & RCANFD_RFFIFO_RFFDF)
+		skb = alloc_canfd_skb(priv->ndev, &cf);
+	else
+		skb = alloc_can_skb(priv->ndev,
+				    (struct can_frame **)&cf);
+
+	if (!skb) {
+		stats->rx_dropped++;
+		return;
+	}
+
+	if (sts & RCANFD_RFFIFO_RFFDF)
+		cf->len = can_dlc2len(RCANFD_RFFIFO_RFDLC(ptr));
+	else
+		cf->len = get_can_dlc(RCANFD_RFFIFO_RFDLC(ptr));
+
+	if (sts & RCANFD_RFFIFO_RFESI) {
+		cf->flags |= CANFD_ESI;
+		netdev_dbg(priv->ndev, "ESI Error\n");
+	}
+
+	if (id & RCANFD_RFFIFO_RFIDE)
+		cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+	else
+		cf->can_id = id & CAN_SFF_MASK;
+
+	if (!(sts & RCANFD_RFFIFO_RFFDF) && (id & RCANFD_RFFIFO_RFRTR)) {
+		cf->can_id |= CAN_RTR_FLAG;
+	} else {
+		if (sts & RCANFD_RFFIFO_RFBRS)
+			cf->flags |= CANFD_BRS;
+
+		rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(ridx, 0));
+	}
+
+	/* Write 0xff to RFPC to increment the CPU-side
+	 * pointer of the Rx FIFO
+	 */
+	rcar_canfd_write(priv->base, RCANFD_RFPCTR(ridx), 0xff);
+
+	can_led_event(priv->ndev, CAN_LED_EVENT_RX);
+
+	stats->rx_bytes += cf->len;
+	stats->rx_packets++;
+	netif_receive_skb(skb);
+}
+
+static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
+{
+	struct rcar_canfd_channel *priv =
+		container_of(napi, struct rcar_canfd_channel, napi);
+	int num_pkts;
+	u32 sts;
+	u32 ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
+		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
+		/* Check FIFO empty condition */
+		if (sts & RCANFD_RFFIFO_RFEMP)
+			break;
+
+		rcar_canfd_rx_pkt(priv);
+
+		/* Clear interrupt bit */
+		if (sts & RCANFD_RFFIFO_RFIF)
+			rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
+					 sts & ~RCANFD_RFFIFO_RFIF);
+	}
+
+	/* All packets processed */
+	if (num_pkts < quota) {
+		napi_complete(napi);
+		/* Enable Rx FIFO interrupts */
+		rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx),
+				   RCANFD_RFFIFO_RFIE);
+	}
+	return num_pkts;
+}
+
+static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
+{
+	int err;
+
+	switch (mode) {
+	case CAN_MODE_START:
+		err = rcar_canfd_start(ndev);
+		if (err)
+			return err;
+		netif_wake_queue(ndev);
+		return 0;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int rcar_canfd_get_berr_counter(const struct net_device *dev,
+				       struct can_berr_counter *bec)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(dev);
+	u32 val, ch = priv->channel;
+
+	/* Peripheral clock is already enabled in probe */
+	val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
+	bec->txerr = RCANFD_CSTS_TECCNT(val);
+	bec->rxerr = RCANFD_CSTS_RECCNT(val);
+	return 0;
+}
+
+static const struct net_device_ops rcar_canfd_netdev_ops = {
+	.ndo_open = rcar_canfd_open,
+	.ndo_stop = rcar_canfd_close,
+	.ndo_start_xmit = rcar_canfd_start_xmit,
+	.ndo_change_mtu = can_change_mtu,
+};
+
+static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
+				    u32 fcan_freq)
+{
+	struct platform_device *pdev = gpriv->pdev;
+	struct rcar_canfd_channel *priv;
+	struct net_device *ndev;
+	int err = -ENODEV;
+
+	ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
+	if (!ndev) {
+		dev_err(&pdev->dev, "alloc_candev() failed\n");
+		err = -ENOMEM;
+		goto fail;
+	}
+	priv = netdev_priv(ndev);
+
+	ndev->netdev_ops = &rcar_canfd_netdev_ops;
+	ndev->flags |= IFF_ECHO;
+	priv->ndev = ndev;
+	priv->base = gpriv->base;
+	priv->channel = ch;
+	priv->can.clock.freq = fcan_freq;
+	dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
+
+	priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
+	priv->can.data_bittiming_const =
+		&rcar_canfd_data_bittiming_const;
+
+	/* Controller starts in CAN FD only mode */
+	can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
+	priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
+
+	priv->can.do_set_mode = rcar_canfd_do_set_mode;
+	priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
+	priv->gpriv = gpriv;
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+
+	netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
+		       RCANFD_NAPI_WEIGHT);
+	err = register_candev(ndev);
+	if (err) {
+		dev_err(&pdev->dev,
+			"register_candev() failed, error %d\n", err);
+		goto fail_candev;
+	}
+	spin_lock_init(&priv->tx_lock);
+	devm_can_led_init(ndev);
+	gpriv->ch[priv->channel] = priv;
+	dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
+	return 0;
+
+fail_candev:
+	netif_napi_del(&priv->napi);
+	free_candev(ndev);
+fail:
+	return err;
+}
+
+static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	struct rcar_canfd_channel *priv = gpriv->ch[ch];
+
+	if (priv) {
+		unregister_candev(priv->ndev);
+		netif_napi_del(&priv->napi);
+		free_candev(priv->ndev);
+	}
+}
+
+static int rcar_canfd_probe(struct platform_device *pdev)
+{
+	struct resource *mem;
+	void __iomem *addr;
+	u32 sts, ch, fcan_freq;
+	struct rcar_canfd_global *gpriv;
+	struct device_node *of_child;
+	unsigned long channels_mask = 0;
+	int err, ch_irq, g_irq;
+
+	of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
+	if (of_child && of_device_is_available(of_child))
+		channels_mask |= BIT(0);	/* Channel 0 */
+
+	of_child = of_get_child_by_name(pdev->dev.of_node, "channel1");
+	if (of_child && of_device_is_available(of_child))
+		channels_mask |= BIT(1);	/* Channel 1 */
+
+	ch_irq = platform_get_irq(pdev, 0);
+	if (ch_irq < 0) {
+		dev_err(&pdev->dev, "no Channel IRQ resource\n");
+		err = ch_irq;
+		goto fail_dev;
+	}
+
+	g_irq = platform_get_irq(pdev, 1);
+	if (g_irq < 0) {
+		dev_err(&pdev->dev, "no Global IRQ resource\n");
+		err = g_irq;
+		goto fail_dev;
+	}
+
+	/* Global controller context */
+	gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
+	if (!gpriv) {
+		err = -ENOMEM;
+		goto fail_dev;
+	}
+	gpriv->pdev = pdev;
+	gpriv->channels_mask = channels_mask;
+
+	/* Peripheral clock */
+	gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
+	if (IS_ERR(gpriv->clkp)) {
+		err = PTR_ERR(gpriv->clkp);
+		dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
+			err);
+		goto fail_dev;
+	}
+
+	/* fCAN clock: Pick External clock. If not available fallback to
+	 * CANFD clock
+	 */
+	gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
+	if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
+		gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
+		if (IS_ERR(gpriv->can_clk)) {
+			err = PTR_ERR(gpriv->can_clk);
+			dev_err(&pdev->dev,
+				"cannot get canfd clock, error %d\n", err);
+			goto fail_dev;
+		}
+		gpriv->fcan = RCANFD_CANFDCLK;
+
+	} else {
+		gpriv->fcan = RCANFD_EXTCLK;
+	}
+	fcan_freq = clk_get_rate(gpriv->can_clk);
+
+	if (gpriv->fcan == RCANFD_CANFDCLK)
+		/* CANFD clock is further divided by (1/2) within the IP */
+		fcan_freq /= 2;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	addr = devm_ioremap_resource(&pdev->dev, mem);
+	if (IS_ERR(addr)) {
+		err = PTR_ERR(addr);
+		goto fail_dev;
+	}
+	gpriv->base = addr;
+
+	/* Request IRQ that's common for both channels */
+	err = devm_request_irq(&pdev->dev, ch_irq,
+			       rcar_canfd_channel_interrupt, 0,
+			       "canfd.chn", gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+			ch_irq, err);
+		goto fail_dev;
+	}
+	err = devm_request_irq(&pdev->dev, g_irq,
+			       rcar_canfd_global_interrupt, 0,
+			       "canfd.gbl", gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+			g_irq, err);
+		goto fail_dev;
+	}
+
+	/* Enable peripheral clock for register access */
+	err = clk_prepare_enable(gpriv->clkp);
+	if (err) {
+		dev_err(&pdev->dev,
+			"failed to enable peripheral clock, error %d\n", err);
+		goto fail_dev;
+	}
+
+	err = rcar_canfd_reset_controller(gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "reset controller failed\n");
+		goto fail_clk;
+	}
+
+	/* Controller in Global reset & Channel reset mode */
+	rcar_canfd_configure_controller(gpriv);
+
+	/* Configure per channel attributes */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		/* Configure Channel's Rx fifo */
+		rcar_canfd_configure_rx(gpriv, ch);
+
+		/* Configure Channel's Tx (Common) fifo */
+		rcar_canfd_configure_tx(gpriv, ch);
+
+		/* Configure receive rules */
+		rcar_canfd_configure_afl_rules(gpriv, ch);
+	}
+
+	/* Configure common interrupts */
+	rcar_canfd_enable_global_interrupts(gpriv);
+
+	/* Start Global operation mode */
+	rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_MODEMASK,
+			      RCANFD_GCTR_GOPM);
+
+	/* Verify mode change */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
+	if (err) {
+		dev_err(&pdev->dev, "global operational mode failed\n");
+		goto fail_mode;
+	}
+
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq);
+		if (err)
+			goto fail_channel;
+	}
+
+	platform_set_drvdata(pdev, gpriv);
+	dev_info(&pdev->dev, "global operational state (clk %d)\n",
+		 gpriv->fcan);
+	return 0;
+
+fail_channel:
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+		rcar_canfd_channel_remove(gpriv, ch);
+fail_mode:
+	rcar_canfd_disable_global_interrupts(gpriv);
+fail_clk:
+	clk_disable_unprepare(gpriv->clkp);
+fail_dev:
+	return err;
+}
+
+static int rcar_canfd_remove(struct platform_device *pdev)
+{
+	struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
+	u32 ch;
+
+	rcar_canfd_reset_controller(gpriv);
+	rcar_canfd_disable_global_interrupts(gpriv);
+
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
+		rcar_canfd_channel_remove(gpriv, ch);
+	}
+
+	/* Enter global sleep mode */
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_SLPR);
+	clk_disable_unprepare(gpriv->clkp);
+	return 0;
+}
+
+static int __maybe_unused rcar_canfd_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int __maybe_unused rcar_canfd_resume(struct device *dev)
+{
+	return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
+			 rcar_canfd_resume);
+
+static const struct of_device_id rcar_canfd_of_table[] = {
+	{ .compatible = "renesas,rcar-gen3-canfd" },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
+
+static struct platform_driver rcar_canfd_driver = {
+	.driver = {
+		.name = RCANFD_DRV_NAME,
+		.of_match_table = of_match_ptr(rcar_canfd_of_table),
+		.pm = &rcar_canfd_pm_ops,
+	},
+	.probe = rcar_canfd_probe,
+	.remove = rcar_canfd_remove,
+};
+
+module_platform_driver(rcar_canfd_driver);
+
+MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
+MODULE_ALIAS("platform:" RCANFD_DRV_NAME);
-- 
1.9.1

[RESEND PATCH v5 2/2] can: rcar_can: Move Renesas CAN driver to rcar dir

[Ramesh Shanmugasundaram]

This patch clubs the Renesas controller drivers in one rcar dir.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
---
 drivers/net/can/Kconfig               | 10 ----------
 drivers/net/can/Makefile              |  1 -
 drivers/net/can/rcar/Kconfig          | 10 ++++++++++
 drivers/net/can/rcar/Makefile         |  3 ++-
 drivers/net/can/{ => rcar}/rcar_can.c |  0
 5 files changed, 12 insertions(+), 12 deletions(-)
 rename drivers/net/can/{ => rcar}/rcar_can.c (100%)

diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 13003a9..22570ea 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -104,16 +104,6 @@ config CAN_JANZ_ICAN3
 	  This driver can also be built as a module. If so, the module will be
 	  called janz-ican3.ko.
 
-config CAN_RCAR
-	tristate "Renesas R-Car CAN controller"
-	depends on ARCH_RENESAS || ARM
-	---help---
-	  Say Y here if you want to use CAN controller found on Renesas R-Car
-	  SoCs.
-
-	  To compile this driver as a module, choose M here: the module will
-	  be called rcar_can.
-
 config CAN_SUN4I
 	tristate "Allwinner A10 CAN controller"
 	depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index 226d5b5..26ba4b7 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_CAN_IFI_CANFD)	+= ifi_canfd/
 obj-$(CONFIG_CAN_JANZ_ICAN3)	+= janz-ican3.o
 obj-$(CONFIG_CAN_MSCAN)		+= mscan/
 obj-$(CONFIG_CAN_M_CAN)		+= m_can/
-obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
 obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
 obj-$(CONFIG_CAN_SUN4I)		+= sun4i_can.o
 obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
diff --git a/drivers/net/can/rcar/Kconfig b/drivers/net/can/rcar/Kconfig
index 6ea64d1..7b03a3a 100644
--- a/drivers/net/can/rcar/Kconfig
+++ b/drivers/net/can/rcar/Kconfig
@@ -1,3 +1,13 @@
+config CAN_RCAR
+	tristate "Renesas R-Car CAN controller"
+	depends on ARCH_RENESAS || ARM
+	---help---
+	  Say Y here if you want to use CAN controller found on Renesas R-Car
+	  SoCs.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called rcar_can.
+
 config CAN_RCAR_CANFD
 	tristate "Renesas R-Car CAN FD controller"
 	depends on ARCH_RENESAS || ARM
diff --git a/drivers/net/can/rcar/Makefile b/drivers/net/can/rcar/Makefile
index cbaf498e..08de36a 100644
--- a/drivers/net/can/rcar/Makefile
+++ b/drivers/net/can/rcar/Makefile
@@ -1,5 +1,6 @@
 #
-#  Makefile for the Renesas R-Car CAN FD controller driver
+#  Makefile for the Renesas R-Car CAN & CAN FD controller drivers
 #
 
+obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
 obj-$(CONFIG_CAN_RCAR_CANFD)	+= rcar_canfd.o
diff --git a/drivers/net/can/rcar_can.c b/drivers/net/can/rcar/rcar_can.c
similarity index 100%
rename from drivers/net/can/rcar_can.c
rename to drivers/net/can/rcar/rcar_can.c
-- 
1.9.1

Re: [RESEND PATCH v5 1/2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ulrich Hecht]

Thank you for your patch.

On Thu, Jun 2, 2016 at 11:45 AM, Ramesh Shanmugasundaram
<ramesh.shanmugasundaram@bp.renesas.com> wrote:
[...]
> diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
> new file mode 100644
> index 0000000..e198732
> --- /dev/null
> +++ b/drivers/net/can/rcar/rcar_canfd.c
> @@ -0,0 +1,1624 @@
> +/* Renesas R-Car CAN FD device driver
> + *
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +
> +/* The R-Car CAN FD controller can operate in either one of the below two modes
> + *  - CAN FD only mode
> + *  - Classical CAN (CAN 2.0) only mode
> + *
> + * This driver puts the controller in CAN FD only mode by default. In this
> + * mode, the controller acts as a CAN FD node that can also interoperate with
> + * CAN 2.0 nodes.
> + *
> + * As of now, this driver does not support the Classical CAN (CAN 2.0) mode,
> + * which is handled by a different register map compared to CAN FD only mode.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/interrupt.h>
> +#include <linux/errno.h>
> +#include <linux/netdevice.h>
> +#include <linux/platform_device.h>
> +#include <linux/can/led.h>
> +#include <linux/can/dev.h>
> +#include <linux/clk.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/bitmap.h>
> +#include <linux/bitops.h>
> +#include <linux/iopoll.h>
> +
> +#define RCANFD_DRV_NAME                        "rcar_canfd"
> +
> +#define RCANFD_FIFO_DEPTH              8       /* Tx FIFO depth */
> +#define RCANFD_NAPI_WEIGHT             8       /* Rx poll quota */
> +
> +#define RCANFD_NUM_CHANNELS            2       /* Two channels max */
> +#define RCANFD_CHANNELS_MASK           BIT((RCANFD_NUM_CHANNELS) - 1)
> +
> +/* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
> + * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
> + * number is added to RFFIFO index.
> + */
> +#define RCANFD_RFFIFO_IDX              0
> +
> +/* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
> + * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
> + */
> +#define RCANFD_CFFIFO_IDX              0
> +
> +/* Global register bits */
> +#define RCANFD_GINTF_CANFD             BIT(0)
> +
> +#define RCANFD_GCFG_TPRI               BIT(0)
> +#define RCANFD_GCFG_DCE                        BIT(1)
> +#define RCANFD_GCFG_DCS                        BIT(4)
> +#define RCANFD_GCFG_CMPOC              BIT(5)

What reference are the register layouts based on? This bit, for
instance, is marked reserved in R-Car-Gen3-rev0.51e.pdf, and many are
named differently.

CU
Uli

RE: [RESEND PATCH v5 1/2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Uli,

Thanks for the review

> Thank you for your patch.
> 
> On Thu, Jun 2, 2016 at 11:45 AM, Ramesh Shanmugasundaram
> <ramesh.shanmugasundaram@bp.renesas.com> wrote:
> [...]
> > diff --git a/drivers/net/can/rcar/rcar_canfd.c
> > b/drivers/net/can/rcar/rcar_canfd.c
> > new file mode 100644
> > index 0000000..e198732
> > --- /dev/null
> > +++ b/drivers/net/can/rcar/rcar_canfd.c
> > @@ -0,0 +1,1624 @@
> > +/* Renesas R-Car CAN FD device driver
> > + *
> > + * Copyright (C) 2015 Renesas Electronics Corp.
> > + *
> > + * This program is free software; you can redistribute  it and/or
> > +modify it
> > + * under  the terms of  the GNU General  Public License as published
> > +by the
> > + * Free Software Foundation;  either version 2 of the  License, or
> > +(at your
> > + * option) any later version.
> > + */
> > +
> > +/* The R-Car CAN FD controller can operate in either one of the below
> > +two modes
> > + *  - CAN FD only mode
> > + *  - Classical CAN (CAN 2.0) only mode
> > + *
> > + * This driver puts the controller in CAN FD only mode by default. In
> > +this
> > + * mode, the controller acts as a CAN FD node that can also
> > +interoperate with
> > + * CAN 2.0 nodes.
> > + *
> > + * As of now, this driver does not support the Classical CAN (CAN
> > +2.0) mode,
> > + * which is handled by a different register map compared to CAN FD only
> mode.
> > + */
> > +
> > +#include <linux/module.h>
> > +#include <linux/moduleparam.h>
> > +#include <linux/kernel.h>
> > +#include <linux/types.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/errno.h>
> > +#include <linux/netdevice.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/can/led.h>
> > +#include <linux/can/dev.h>
> > +#include <linux/clk.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/bitmap.h>
> > +#include <linux/bitops.h>
> > +#include <linux/iopoll.h>
> > +
> > +#define RCANFD_DRV_NAME                        "rcar_canfd"
> > +
> > +#define RCANFD_FIFO_DEPTH              8       /* Tx FIFO depth */
> > +#define RCANFD_NAPI_WEIGHT             8       /* Rx poll quota */
> > +
> > +#define RCANFD_NUM_CHANNELS            2       /* Two channels max */
> > +#define RCANFD_CHANNELS_MASK           BIT((RCANFD_NUM_CHANNELS) - 1)
> > +
> > +/* Rx FIFO is a global resource of the controller. There are 8 such
> > +FIFOs
> > + * available. Each channel gets a dedicated Rx FIFO (i.e.) the
> > +channel
> > + * number is added to RFFIFO index.
> > + */
> > +#define RCANFD_RFFIFO_IDX              0
> > +
> > +/* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3
> > +Common
> > + * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3
> for Tx.
> > + */
> > +#define RCANFD_CFFIFO_IDX              0
> > +
> > +/* Global register bits */
> > +#define RCANFD_GINTF_CANFD             BIT(0)
> > +
> > +#define RCANFD_GCFG_TPRI               BIT(0)
> > +#define RCANFD_GCFG_DCE                        BIT(1)
> > +#define RCANFD_GCFG_DCS                        BIT(4)
> > +#define RCANFD_GCFG_CMPOC              BIT(5)
> 
> What reference are the register layouts based on? This bit, for instance,
> is marked reserved in R-Car-Gen3-rev0.51e.pdf, and many are named
> differently.

It is based on rev0.51e Gen3 h/w manual. This controller has two register maps within itself for classical CAN only mode or CAN FD only mode. Section 52A.7.3.1 defines GCFG classical CAN only mode where bit 5 is reserved and Section 52A.9.3.1 defines GCFG CAN FD mode where bit 5 is defined as CMPOC.

It is explained in the initial comments section of this driver 

-------------
+/* The R-Car CAN FD controller can operate in either one of the below two modes
+ *  - CAN FD only mode
+ *  - Classical CAN (CAN 2.0) only mode
+ *
+ * This driver puts the controller in CAN FD only mode by default. In this
+ * mode, the controller acts as a CAN FD node that can also interoperate with
+ * CAN 2.0 nodes.
+ *
+ * As of now, this driver does not support the Classical CAN (CAN 2.0) mode,
+ * which is handled by a different register map compared to CAN FD only mode
--------------

Thanks,
Ramesh

Re: [RESEND PATCH v5 1/2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ulrich Hecht]

On Fri, Jun 3, 2016 at 8:42 AM, Ramesh Shanmugasundaram
<ramesh.shanmugasundaram@bp.renesas.com> wrote:
> Hi Uli,
>
> Thanks for the review
>
>> Thank you for your patch.
>>
>> On Thu, Jun 2, 2016 at 11:45 AM, Ramesh Shanmugasundaram
>> <ramesh.shanmugasundaram@bp.renesas.com> wrote:
>> [...]
>> > diff --git a/drivers/net/can/rcar/rcar_canfd.c
>> > b/drivers/net/can/rcar/rcar_canfd.c
>> > new file mode 100644
>> > index 0000000..e198732
>> > --- /dev/null
>> > +++ b/drivers/net/can/rcar/rcar_canfd.c
>> > @@ -0,0 +1,1624 @@
>> > +/* Renesas R-Car CAN FD device driver
>> > + *
>> > + * Copyright (C) 2015 Renesas Electronics Corp.
>> > + *
>> > + * This program is free software; you can redistribute  it and/or
>> > +modify it
>> > + * under  the terms of  the GNU General  Public License as published
>> > +by the
>> > + * Free Software Foundation;  either version 2 of the  License, or
>> > +(at your
>> > + * option) any later version.
>> > + */
>> > +
>> > +/* The R-Car CAN FD controller can operate in either one of the below
>> > +two modes
>> > + *  - CAN FD only mode
>> > + *  - Classical CAN (CAN 2.0) only mode
>> > + *
>> > + * This driver puts the controller in CAN FD only mode by default. In
>> > +this
>> > + * mode, the controller acts as a CAN FD node that can also
>> > +interoperate with
>> > + * CAN 2.0 nodes.
>> > + *
>> > + * As of now, this driver does not support the Classical CAN (CAN
>> > +2.0) mode,
>> > + * which is handled by a different register map compared to CAN FD only
>> mode.
>> > + */
>> > +
>> > +#include <linux/module.h>
>> > +#include <linux/moduleparam.h>
>> > +#include <linux/kernel.h>
>> > +#include <linux/types.h>
>> > +#include <linux/interrupt.h>
>> > +#include <linux/errno.h>
>> > +#include <linux/netdevice.h>
>> > +#include <linux/platform_device.h>
>> > +#include <linux/can/led.h>
>> > +#include <linux/can/dev.h>
>> > +#include <linux/clk.h>
>> > +#include <linux/of.h>
>> > +#include <linux/of_device.h>
>> > +#include <linux/bitmap.h>
>> > +#include <linux/bitops.h>
>> > +#include <linux/iopoll.h>
>> > +
>> > +#define RCANFD_DRV_NAME                        "rcar_canfd"
>> > +
>> > +#define RCANFD_FIFO_DEPTH              8       /* Tx FIFO depth */
>> > +#define RCANFD_NAPI_WEIGHT             8       /* Rx poll quota */
>> > +
>> > +#define RCANFD_NUM_CHANNELS            2       /* Two channels max */
>> > +#define RCANFD_CHANNELS_MASK           BIT((RCANFD_NUM_CHANNELS) - 1)
>> > +
>> > +/* Rx FIFO is a global resource of the controller. There are 8 such
>> > +FIFOs
>> > + * available. Each channel gets a dedicated Rx FIFO (i.e.) the
>> > +channel
>> > + * number is added to RFFIFO index.
>> > + */
>> > +#define RCANFD_RFFIFO_IDX              0
>> > +
>> > +/* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3
>> > +Common
>> > + * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3
>> for Tx.
>> > + */
>> > +#define RCANFD_CFFIFO_IDX              0
>> > +
>> > +/* Global register bits */
>> > +#define RCANFD_GINTF_CANFD             BIT(0)
>> > +
>> > +#define RCANFD_GCFG_TPRI               BIT(0)
>> > +#define RCANFD_GCFG_DCE                        BIT(1)
>> > +#define RCANFD_GCFG_DCS                        BIT(4)
>> > +#define RCANFD_GCFG_CMPOC              BIT(5)
>>
>> What reference are the register layouts based on? This bit, for instance,
>> is marked reserved in R-Car-Gen3-rev0.51e.pdf, and many are named
>> differently.
>
> It is based on rev0.51e Gen3 h/w manual. This controller has two register maps within itself for classical CAN only mode or CAN FD only mode. Section 52A.7.3.1 defines GCFG classical CAN only mode where bit 5 is reserved and Section 52A.9.3.1 defines GCFG CAN FD mode where bit 5 is defined as CMPOC.

Thanks; I missed that every register is described twice.

Nevertheless, names often vary more or less subtly between your patch
and the specs, making it very hard to review. Some have letters added,
some have letters removed, and some are just plain confusing. For
instance, RCANFD_DCFG_* apparently does not describe, as one might
think, RSCFDnCFDCmDCFG, but RSCFDnCFDCmFDCFG. These names are, of
course, completely ridiculous, but inventing a new set makes things
even worse, IMO.

At least for the bits, I'd stick with the names given in the
datasheet. They usually make a modicum of sense, and it makes it way
easier to search for them. It would also help if the bits were sorted
consistently.

CU
Uli

Re: [RESEND PATCH v5 1/2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Oliver Hartkopp]

On 06/03/2016 07:03 PM, Ulrich Hecht wrote:

> Thanks; I missed that every register is described twice.
>
> Nevertheless, names often vary more or less subtly between your patch
> and the specs, making it very hard to review. Some have letters added,
> some have letters removed, and some are just plain confusing. For
> instance, RCANFD_DCFG_* apparently does not describe, as one might
> think, RSCFDnCFDCmDCFG, but RSCFDnCFDCmFDCFG. These names are, of
> course, completely ridiculous, but inventing a new set makes things
> even worse, IMO.

???

You suggest to use 'completely ridiculous' definitions in favor to 
definitions that have a proper name space RCANFD_ ?

When there is a more readable way that maintains proper readable code 
there's no reason to adopt crappy definitions just because some chip 
designer has no clue how to design proper register names.

When there's some mapping from RSCFDnCFDCmFDCFG to RCANFD_DCFG_* this 
could be mentioned in the comments.

But I'm totally against these blurry upper/lower case letter stuff for 
register definitions.

Regards,
Oliver


>
> At least for the bits, I'd stick with the names given in the
> datasheet. They usually make a modicum of sense, and it makes it way
> easier to search for them. It would also help if the bits were sorted
> consistently.
>
> CU
> Uli
>

Re: [RESEND PATCH v5 1/2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[David Miller]

From: Oliver Hartkopp <socketcan@hartkopp.net>
Date: Fri, 3 Jun 2016 19:15:29 +0200

> On 06/03/2016 07:03 PM, Ulrich Hecht wrote:
> 
>> Thanks; I missed that every register is described twice.
>>
>> Nevertheless, names often vary more or less subtly between your patch
>> and the specs, making it very hard to review. Some have letters added,
>> some have letters removed, and some are just plain confusing. For
>> instance, RCANFD_DCFG_* apparently does not describe, as one might
>> think, RSCFDnCFDCmDCFG, but RSCFDnCFDCmFDCFG. These names are, of
>> course, completely ridiculous, but inventing a new set makes things
>> even worse, IMO.
> 
> ???
> 
> You suggest to use 'completely ridiculous' definitions in favor to
> definitions that have a proper name space RCANFD_ ?
> 
> When there is a more readable way that maintains proper readable code
> there's no reason to adopt crappy definitions just because some chip
> designer has no clue how to design proper register names.
> 
> When there's some mapping from RSCFDnCFDCmFDCFG to RCANFD_DCFG_* this
> could be mentioned in the comments.
> 
> But I'm totally against these blurry upper/lower case letter stuff for
> register definitions.

I agree with Oliver, these StuDlyCaPS names used in the spec should
not be used in the driver, they are completely unreadable.

RE: [RESEND PATCH v5 1/2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

> > On 06/03/2016 07:03 PM, Ulrich Hecht wrote:
> >
> >> Thanks; I missed that every register is described twice.
> >>
> >> Nevertheless, names often vary more or less subtly between your patch
> >> and the specs, making it very hard to review. Some have letters
> >> added, some have letters removed, and some are just plain confusing.
> >> For instance, RCANFD_DCFG_* apparently does not describe, as one
> >> might think, RSCFDnCFDCmDCFG, but RSCFDnCFDCmFDCFG. These names are,
> >> of course, completely ridiculous, but inventing a new set makes
> >> things even worse, IMO.
> >
> > ???
> >
> > You suggest to use 'completely ridiculous' definitions in favor to
> > definitions that have a proper name space RCANFD_ ?
> >
> > When there is a more readable way that maintains proper readable code
> > there's no reason to adopt crappy definitions just because some chip
> > designer has no clue how to design proper register names.
> >
> > When there's some mapping from RSCFDnCFDCmFDCFG to RCANFD_DCFG_* this
> > could be mentioned in the comments.
> >
> > But I'm totally against these blurry upper/lower case letter stuff for
> > register definitions.
> 
> I agree with Oliver, these StuDlyCaPS names used in the spec should not be
> used in the driver, they are completely unreadable.

Thanks Oliver, Dave for your inputs.

Hi Uli,

I have added comments to the readable register set mapping them to the clumsy name in h/w manual to aid your review. I have kept the bit name definitions within register exactly as in h/w manual. E.g.

+/* RSCFDnCFDGSTS */
+#define RCANFD_GSTS_GRAMINIT		BIT(3)
+#define RCANFD_GSTS_GSLPSTS		BIT(2)
+#define RCANFD_GSTS_GHLTSTS		BIT(1)
+#define RCANFD_GSTS_GRSTSTS		BIT(0)

I have also sorted the bit definition ordering from MSB to LSB. I will send out the updated patch set next. I hope this addresses your concern.

Please note that I am planning to add classical CAN only mode support next (after the current patch set is accepted). The code is designed to support both modes and hence I have classified the register definitions as "common register set" & "CAN FD specific register set". In future, I will just add the "Classical CAN specific register set" alone without much code re-org.

Thanks,
Ramesh

[PATCH v6 0/2] Add CAN FD driver support to r8a7795 SoC

[Ramesh Shanmugasundaram]

Hi All,

   This patch is based on can-next latest tag "linux-can-next-for-4.7-20160509"

Changes since v5:
	* Addressed Ulrich's concerns on register, bits naming convention
	* Rebased to latest tag (linux-can-next-for-4.7-20160509)

Changes since v4:
	* Rebased to latest can-next/testing branch
	* Addressed Marc K review comments on v2 patch
	* Use clk_get_rate() to find ext clock availability. Refer thread
	(https://lkml.org/lkml/2016/4/8/203)

Changes since v3:
	* Split v3 patch into two (Marc K)
	  (1) Introduce rcar_canfd.c driver in drivers/net/can/rcar dir
	  (2) Move rcar_can.c driver to new drivers/net/can/rcar dir
	* Added Acked-by Rob H for the bindings
	* Added comments on CAN FD only mode in driver & Kconfig (Oliver H)

Changes since v2:
	* Rebased to latest tag (linux-can-next-for-4.6-20160310)
	* Cleaned up leftover debugfs code (Thanks Oliver H)
	* Revised devicetree documentation text (as suggested by Rob H)
	  (https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg01597.html)
	* Used new can subsystem api to set static configuration & removed check in rcar_canfd_start (as suggested by Oliver H)
	  (Refer: http://comments.gmane.org/gmane.linux.can/9126 &
	   https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg01867.html)
	* Clubbed Renesas controller drivers to driver/net/can/rcar dir (as suggested by Oliver H)
	* Updated commit message

Changes since v1:
	* Removed testmodes & debugfs code (suggested by Oliver H)
	* Fixed tx path race issue by introducing lock (suggested by Marc K)
	* Removed __maybe_unused attribute of rcar_canfd_of_table


Ramesh Shanmugasundaram (2):
  can: rcar_canfd: Add Renesas R-Car CAN FD driver
  can: rcar_can: Move Renesas CAN driver to rcar dir

 .../devicetree/bindings/net/can/rcar_canfd.txt     |   89 +
 drivers/net/can/Kconfig                            |   11 +-
 drivers/net/can/Makefile                           |    2 +-
 drivers/net/can/rcar/Kconfig                       |   21 +
 drivers/net/can/rcar/Makefile                      |    6 +
 drivers/net/can/{ => rcar}/rcar_can.c              |    0
 drivers/net/can/rcar/rcar_canfd.c                  | 1695 ++++++++++++++++++++
 7 files changed, 1813 insertions(+), 11 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
 create mode 100644 drivers/net/can/rcar/Kconfig
 create mode 100644 drivers/net/can/rcar/Makefile
 rename drivers/net/can/{ => rcar}/rcar_can.c (100%)
 create mode 100644 drivers/net/can/rcar/rcar_canfd.c

-- 
1.9.1

[PATCH v6 1/2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

This patch adds support for the CAN FD controller found in Renesas R-Car
SoCs. The controller operates in CAN FD only mode by default.

CAN FD mode supports both Classical CAN & CAN FD frame formats. The
controller supports ISO 11898-1:2015 CAN FD format only.

This controller supports two channels and the driver can enable either
or both of the channels.

Driver uses Rx FIFOs (one per channel) for reception & Common FIFOs (one
per channel) for transmission. Rx filter rules are configured to the
minimum (one per channel) and it accepts Standard, Extended, Data &
Remote Frame combinations.

Note: There are few documentation errors in R-Car Gen3 Hardware User
Manual v0.5E with respect to CAN FD controller. They are listed below:

1. CAN FD interrupt numbers 29 & 30 are listed as per channel
interrupts. However, they are common to both channels (i.e.) they are
global and channel interrupts respectively.

2. CANFD clock is derived from PLL1. This is not documented.

3. CANFD clock is further divided by (1/2) within the CAN FD controller.
This is not documented.

4. The minimum value of NTSEG1 in RSCFDnCFDCmNCFG register is 2 Tq. It
is specified 4 Tq in the manual.

5. The maximum number of message RAM area the controller can use is 3584
bytes. It is specified 10752 bytes in the manual.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/net/can/rcar_canfd.txt     |   89 +
 drivers/net/can/Kconfig                            |    1 +
 drivers/net/can/Makefile                           |    1 +
 drivers/net/can/rcar/Kconfig                       |   11 +
 drivers/net/can/rcar/Makefile                      |    5 +
 drivers/net/can/rcar/rcar_canfd.c                  | 1695 ++++++++++++++++++++
 6 files changed, 1802 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt
 create mode 100644 drivers/net/can/rcar/Kconfig
 create mode 100644 drivers/net/can/rcar/Makefile
 create mode 100644 drivers/net/can/rcar/rcar_canfd.c

diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
new file mode 100644
index 0000000..d45182b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
@@ -0,0 +1,89 @@
+Renesas R-Car CAN FD controller Device Tree Bindings
+----------------------------------------------------
+
+Required properties:
+- compatible: Must contain one or more of the following:
+  - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
+  - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
+
+  When compatible with the generic version, nodes must list the
+  SoC-specific version corresponding to the platform first, followed by the
+  family-specific and/or generic versions.
+
+- reg: physical base address and size of the R-Car CAN FD register map.
+- interrupts: interrupt specifier for the Global & Channel interrupts
+- clocks: phandles and clock specifiers for 3 clock inputs.
+- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
+- pinctrl-0: pin control group to be used for this controller.
+- pinctrl-names: must be "default".
+
+Required child nodes:
+The controller supports two channels and each is represented as a child node.
+The name of the child nodes are "channel0" and "channel1" respectively. Each
+child node supports the "status" property only, which is used to
+enable/disable the respective channel.
+
+Required properties for "renesas,r8a7795-canfd" compatible:
+In R8A7795 SoC, canfd clock is a div6 clock and can be used by both CAN
+and CAN FD controller at the same time. It needs to be scaled to maximum
+frequency if any of these controllers use it. This is done using the
+below properties.
+
+- assigned-clocks: phandle of canfd clock.
+- assigned-clock-rates: maximum frequency of this clock.
+
+Example
+-------
+
+SoC common .dtsi file:
+
+		canfd: can@e66c0000 {
+			compatible = "renesas,r8a7795-canfd",
+				     "renesas,rcar-gen3-canfd";
+			reg = <0 0xe66c0000 0 0x8000>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 914>,
+			       <&cpg CPG_CORE R8A7795_CLK_CANFD>,
+			       <&can_clk>;
+			clock-names = "fck", "canfd", "can_clk";
+			assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
+			assigned-clock-rates = <40000000>;
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			channel0 {
+				status = "disabled";
+			};
+
+			channel1 {
+				status = "disabled";
+			};
+		};
+
+Board specific .dts file:
+
+E.g. below enables Channel 1 alone in the board.
+
+&canfd {
+        pinctrl-0 = <&canfd1_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+	channel1 {
+		status = "okay";
+	};
+};
+
+E.g. below enables Channel 0 alone in the board using External clock
+as fCAN clock.
+
+&canfd {
+        pinctrl-0 = <&canfd0_pins &can_clk_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+	channel0 {
+		status = "okay";
+	};
+};
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 0d40aef..13003a9 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -152,6 +152,7 @@ source "drivers/net/can/cc770/Kconfig"
 source "drivers/net/can/ifi_canfd/Kconfig"
 source "drivers/net/can/m_can/Kconfig"
 source "drivers/net/can/mscan/Kconfig"
+source "drivers/net/can/rcar/Kconfig"
 source "drivers/net/can/sja1000/Kconfig"
 source "drivers/net/can/softing/Kconfig"
 source "drivers/net/can/spi/Kconfig"
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index e3db0c8..226d5b5 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -10,6 +10,7 @@ can-dev-y			:= dev.o
 
 can-dev-$(CONFIG_CAN_LEDS)	+= led.o
 
+obj-y				+= rcar/
 obj-y				+= spi/
 obj-y				+= usb/
 obj-y				+= softing/
diff --git a/drivers/net/can/rcar/Kconfig b/drivers/net/can/rcar/Kconfig
new file mode 100644
index 0000000..6ea64d1
--- /dev/null
+++ b/drivers/net/can/rcar/Kconfig
@@ -0,0 +1,11 @@
+config CAN_RCAR_CANFD
+	tristate "Renesas R-Car CAN FD controller"
+	depends on ARCH_RENESAS || ARM
+	---help---
+	  Say Y here if you want to use CAN FD controller found on
+	  Renesas R-Car SoCs. The driver puts the controller in CAN FD only
+	  mode, which can interoperate with CAN2.0 nodes but does not support
+	  dedicated CAN 2.0 mode.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called rcar_canfd.
diff --git a/drivers/net/can/rcar/Makefile b/drivers/net/can/rcar/Makefile
new file mode 100644
index 0000000..cbaf498e
--- /dev/null
+++ b/drivers/net/can/rcar/Makefile
@@ -0,0 +1,5 @@
+#
+#  Makefile for the Renesas R-Car CAN FD controller driver
+#
+
+obj-$(CONFIG_CAN_RCAR_CANFD)	+= rcar_canfd.o
diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
new file mode 100644
index 0000000..9f1f513
--- /dev/null
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -0,0 +1,1695 @@
+/* Renesas R-Car CAN FD device driver
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/* The R-Car CAN FD controller can operate in either one of the below two modes
+ *  - CAN FD only mode
+ *  - Classical CAN (CAN 2.0) only mode
+ *
+ * This driver puts the controller in CAN FD only mode by default. In this
+ * mode, the controller acts as a CAN FD node that can also interoperate with
+ * CAN 2.0 nodes.
+ *
+ * As of now, this driver does not support the Classical CAN (CAN 2.0) mode,
+ * which is handled by a different register map compared to CAN FD only mode.
+ *
+ * Note: The h/w manual register naming convention is clumsy and not acceptable
+ * to use as it is in the driver. However, those names are added as comments
+ * wherever it is modified to a readable name.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/netdevice.h>
+#include <linux/platform_device.h>
+#include <linux/can/led.h>
+#include <linux/can/dev.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+
+#define RCANFD_DRV_NAME			"rcar_canfd"
+
+/* Global register bits */
+
+/* RSCFDnCFDGRMCFG */
+#define RCANFD_GRMCFG_RCMC		BIT(0)
+
+/* RSCFDnCFDGCFG */
+#define RCANFD_GCFG_CMPOC		BIT(5)
+#define RCANFD_GCFG_DCS			BIT(4)
+#define RCANFD_GCFG_DCE			BIT(1)
+#define RCANFD_GCFG_TPRI		BIT(0)
+
+/* RSCFDnCFDGCTR */
+#define RCANFD_GCTR_TSRST		BIT(16)
+#define RCANFD_GCTR_CFMPOFIE		BIT(11)
+#define RCANFD_GCTR_THLEIE		BIT(10)
+#define RCANFD_GCTR_MEIE		BIT(9)
+#define RCANFD_GCTR_DEIE		BIT(8)
+#define RCANFD_GCTR_GSLPR		BIT(2)
+#define RCANFD_GCTR_GMDC_MASK		(0x3)
+#define RCANFD_GCTR_GMDC_GOPM		(0x0)
+#define RCANFD_GCTR_GMDC_GRESET		(0x1)
+#define RCANFD_GCTR_GMDC_GTEST		(0x2)
+
+/* RSCFDnCFDGSTS */
+#define RCANFD_GSTS_GRAMINIT		BIT(3)
+#define RCANFD_GSTS_GSLPSTS		BIT(2)
+#define RCANFD_GSTS_GHLTSTS		BIT(1)
+#define RCANFD_GSTS_GRSTSTS		BIT(0)
+/* Non-operational status */
+#define RCANFD_GSTS_GNOPM		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+/* RSCFDnCFDGERFL */
+#define RCANFD_GERFL_EEF1		BIT(17)
+#define RCANFD_GERFL_EEF0		BIT(16)
+#define RCANFD_GERFL_CMPOF		BIT(3)
+#define RCANFD_GERFL_THLES		BIT(2)
+#define RCANFD_GERFL_MES		BIT(1)
+#define RCANFD_GERFL_DEF		BIT(0)
+
+#define RCANFD_GERFL_ERR(x)		((x) & (RCANFD_GERFL_EEF1 |\
+						RCANFD_GERFL_EEF0 |\
+						RCANFD_GERFL_MES |\
+						RCANFD_GERFL_CMPOF))
+
+/* AFL Rx rules registers */
+
+/* RSCFDnCFDGAFLCFG0 */
+#define RCANFD_GAFLCFG_SETRNC(n, x)	(((x) & 0xff) << (24 - n * 8))
+#define RCANFD_GAFLCFG_GETRNC(n, x)	(((x) >> (24 - n * 8)) & 0xff)
+
+/* RSCFDnCFDGAFLECTR */
+#define RCANFD_GAFLECTR_AFLDAE		BIT(8)
+#define RCANFD_GAFLECTR_AFLPN(x)	((x) & 0x1f)
+
+/* RSCFDnCFDGAFLIDj */
+#define RCANFD_GAFLID_GAFLLB		BIT(29)
+
+/* RSCFDnCFDGAFLP1_j */
+#define RCANFD_GAFLP1_GAFLFDP(x)	(1 << (x))
+
+/* Channel register bits */
+
+/* RSCFDnCFDCmNCFG */
+#define RCANFD_NCFG_NTSEG2(x)		(((x) & 0x1f) << 24)
+#define RCANFD_NCFG_NTSEG1(x)		(((x) & 0x7f) << 16)
+#define RCANFD_NCFG_NSJW(x)		(((x) & 0x1f) << 11)
+#define RCANFD_NCFG_NBRP(x)		(((x) & 0x3ff) << 0)
+
+/* RSCFDnCFDCmCTR */
+#define RCANFD_CCTR_CTME		BIT(24)
+#define RCANFD_CCTR_ERRD		BIT(23)
+#define RCANFD_CCTR_BOM_MASK		(0x3 << 21)
+#define RCANFD_CCTR_BOM_ISO		(0x0 << 21)
+#define RCANFD_CCTR_BOM_BENTRY		(0x1 << 21)
+#define RCANFD_CCTR_BOM_BEND		(0x2 << 21)
+#define RCANFD_CCTR_TDCVFIE		BIT(19)
+#define RCANFD_CCTR_SOCOIE		BIT(18)
+#define RCANFD_CCTR_EOCOIE		BIT(17)
+#define RCANFD_CCTR_TAIE		BIT(16)
+#define RCANFD_CCTR_ALIE		BIT(15)
+#define RCANFD_CCTR_BLIE		BIT(14)
+#define RCANFD_CCTR_OLIE		BIT(13)
+#define RCANFD_CCTR_BORIE		BIT(12)
+#define RCANFD_CCTR_BOEIE		BIT(11)
+#define RCANFD_CCTR_EPIE		BIT(10)
+#define RCANFD_CCTR_EWIE		BIT(9)
+#define RCANFD_CCTR_BEIE		BIT(8)
+#define RCANFD_CCTR_CSLPR		BIT(2)
+#define RCANFD_CCTR_CHMDC_MASK		(0x3)
+#define RCANFD_CCTR_CHDMC_COPM		(0x0)
+#define RCANFD_CCTR_CHDMC_CRESET	(0x1)
+#define RCANFD_CCTR_CHDMC_CHLT		(0x2)
+
+/* RSCFDnCFDCmSTS */
+#define RCANFD_CSTS_COMSTS		BIT(7)
+#define RCANFD_CSTS_RECSTS		BIT(6)
+#define RCANFD_CSTS_TRMSTS		BIT(5)
+#define RCANFD_CSTS_BOSTS		BIT(4)
+#define RCANFD_CSTS_EPSTS		BIT(3)
+#define RCANFD_CSTS_SLPSTS		BIT(2)
+#define RCANFD_CSTS_HLTSTS		BIT(1)
+#define RCANFD_CSTS_CRSTSTS		BIT(0)
+
+#define RCANFD_CSTS_TECCNT(x)		(((x) >> 24) & 0xff)
+#define RCANFD_CSTS_RECCNT(x)		(((x) >> 16) & 0xff)
+
+/* RSCFDnCFDCmERFL */
+#define RCANFD_CERFL_ADERR		BIT(14)
+#define RCANFD_CERFL_B0ERR		BIT(13)
+#define RCANFD_CERFL_B1ERR		BIT(12)
+#define RCANFD_CERFL_CERR		BIT(11)
+#define RCANFD_CERFL_AERR		BIT(10)
+#define RCANFD_CERFL_FERR		BIT(9)
+#define RCANFD_CERFL_SERR		BIT(8)
+#define RCANFD_CERFL_ALF		BIT(7)
+#define RCANFD_CERFL_BLF		BIT(6)
+#define RCANFD_CERFL_OVLF		BIT(5)
+#define RCANFD_CERFL_BORF		BIT(4)
+#define RCANFD_CERFL_BOEF		BIT(3)
+#define RCANFD_CERFL_EPF		BIT(2)
+#define RCANFD_CERFL_EWF		BIT(1)
+#define RCANFD_CERFL_BEF		BIT(0)
+
+#define RCANFD_CERFL_ERR(x)		((x) & (0x7fff)) /* above bits 14:0 */
+
+/* RSCFDnCFDCmDCFG */
+#define RCANFD_DCFG_DSJW(x)		(((x) & 0x7) << 24)
+#define RCANFD_DCFG_DTSEG2(x)		(((x) & 0x7) << 20)
+#define RCANFD_DCFG_DTSEG1(x)		(((x) & 0xf) << 16)
+#define RCANFD_DCFG_DBRP(x)		(((x) & 0xff) << 0)
+
+/* RSCFDnCFDCmFDCFG */
+#define RCANFD_FDCFG_TDCE		BIT(9)
+#define RCANFD_FDCFG_TDCOC		BIT(8)
+#define RCANFD_FDCFG_TDCO(x)		(((x) & 0x7f) >> 16)
+
+/* RSCFDnCFDRFCCx */
+#define RCANFD_RFCC_RFIM		BIT(12)
+#define RCANFD_RFCC_RFDC(x)		(((x) & 0x7) << 8)
+#define RCANFD_RFCC_RFPLS(x)		(((x) & 0x7) << 4)
+#define RCANFD_RFCC_RFIE		BIT(1)
+#define RCANFD_RFCC_RFE			BIT(0)
+
+/* RSCFDnCFDRFSTSx */
+#define RCANFD_RFSTS_RFIF		BIT(3)
+#define RCANFD_RFSTS_RFMLT		BIT(2)
+#define RCANFD_RFSTS_RFFLL		BIT(1)
+#define RCANFD_RFSTS_RFEMP		BIT(0)
+
+/* RSCFDnCFDRFIDx */
+#define RCANFD_RFID_RFIDE		BIT(31)
+#define RCANFD_RFID_RFRTR		BIT(30)
+
+/* RSCFDnCFDRFPTRx */
+#define RCANFD_RFPTR_RFDLC(x)		(((x) >> 28) & 0xf)
+#define RCANFD_RFPTR_RFPTR(x)		(((x) >> 16) & 0xfff)
+#define RCANFD_RFPTR_RFTS(x)		(((x) >> 0) & 0xff)
+
+/* RSCFDnCFDRFFDSTSx */
+#define RCANFD_RFFDSTS_RFFDF		BIT(2)
+#define RCANFD_RFFDSTS_RFBRS		BIT(1)
+#define RCANFD_RFFDSTS_RFESI		BIT(0)
+
+/* Common FIFO bits */
+
+/* RSCFDnCFDCFCCk */
+#define RCANFD_CFCC_CFTML(x)		(((x) & 0xf) << 20)
+#define RCANFD_CFCC_CFM(x)		(((x) & 0x3) << 16)
+#define RCANFD_CFCC_CFIM		BIT(12)
+#define RCANFD_CFCC_CFDC(x)		(((x) & 0x7) << 8)
+#define RCANFD_CFCC_CFPLS(x)		(((x) & 0x7) << 4)
+#define RCANFD_CFCC_CFTXIE		BIT(2)
+#define RCANFD_CFCC_CFE			BIT(0)
+
+/* RSCFDnCFDCFSTSk */
+#define RCANFD_CFSTS_CFMC(x)		(((x) >> 8) & 0xff)
+#define RCANFD_CFSTS_CFTXIF		BIT(4)
+#define RCANFD_CFSTS_CFMLT		BIT(2)
+#define RCANFD_CFSTS_CFFLL		BIT(1)
+#define RCANFD_CFSTS_CFEMP		BIT(0)
+
+/* RSCFDnCFDCFIDk */
+#define RCANFD_CFID_CFIDE		BIT(31)
+#define RCANFD_CFID_CFRTR		BIT(30)
+#define RCANFD_CFID_CFID_MASK(x)	((x) & 0x1fffffff)
+
+/* RSCFDnCFDCFPTRk */
+#define RCANFD_CFPTR_CFDLC(x)		(((x) & 0xf) << 28)
+#define RCANFD_CFPTR_CFPTR(x)		(((x) & 0xfff) << 16)
+#define RCANFD_CFPTR_CFTS(x)		(((x) & 0xff) << 0)
+
+/* RSCFDnCFDCFFDCSTSk */
+#define RCANFD_CFFDCSTS_CFFDF		BIT(2)
+#define RCANFD_CFFDCSTS_CFBRS		BIT(1)
+#define RCANFD_CFFDCSTS_CFESI		BIT(0)
+
+/* This controller supports classical CAN only mode or CAN FD only mode. These
+ * modes are supported in two separate set of register maps & names. However,
+ * some of the register offsets are common for both modes. Those offsets are
+ * listed below as Common registers.
+ *
+ * The CAN FD only specific registers are listed separately and their names
+ * starts with RCANFD_F_xxx names. When classical CAN only specific registers
+ * are added, those specific registers can be prefixed as RCANFD_C_xxx.
+ */
+
+/* Common registers */
+
+/* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
+#define RCANFD_CCFG(m)			(0x0000 + (0x10 * (m)))
+/* RSCFDnCFDCmCTR / RSCFDnCmCTR */
+#define RCANFD_CCTR(m)			(0x0004 + (0x10 * (m)))
+/* RSCFDnCFDCmSTS / RSCFDnCmSTS */
+#define RCANFD_CSTS(m)			(0x0008 + (0x10 * (m)))
+/* RSCFDnCFDCmERFL / RSCFDnCmERFL */
+#define RCANFD_CERFL(m)			(0x000C + (0x10 * (m)))
+
+/* RSCFDnCFDGCFG / RSCFDnGCFG */
+#define RCANFD_GCFG			(0x0084)
+/* RSCFDnCFDGCTR / RSCFDnGCTR */
+#define RCANFD_GCTR			(0x0088)
+/* RSCFDnCFDGCTS / RSCFDnGCTS */
+#define RCANFD_GSTS			(0x008c)
+/* RSCFDnCFDGERFL / RSCFDnGERFL */
+#define RCANFD_GERFL			(0x0090)
+/* RSCFDnCFDGTSC / RSCFDnGTSC */
+#define RCANFD_GTSC			(0x0094)
+/* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
+#define RCANFD_GAFLECTR			(0x0098)
+/* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
+#define RCANFD_GAFLCFG0			(0x009c)
+/* RSCFDnCFDGAFLCFG1 / RSCFDnGAFLCFG1 */
+#define RCANFD_GAFLCFG1			(0x00a0)
+/* RSCFDnCFDRMNB / RSCFDnRMNB */
+#define RCANFD_RMNB			(0x00a4)
+/* RSCFDnCFDRMND / RSCFDnRMND */
+#define RCANFD_RMND(y)			(0x00a8 + (0x04 * (y)))
+
+/* RSCFDnCFDRFCCx / RSCFDnRFCCx */
+#define RCANFD_RFCC(x)			(0x00b8 + (0x04 * (x)))
+/* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
+#define RCANFD_RFSTS(x)			(0x00d8 + (0x04 * (x)))
+/* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
+#define RCANFD_RFPCTR(x)		(0x00f8 + (0x04 * (x)))
+
+/* Common FIFO Control registers */
+
+/* RSCFDnCFDCFCCx / RSCFDnCFCCx */
+#define RCANFD_CFCC(ch, idx)		(0x0118 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+/* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
+#define RCANFD_CFSTS(ch, idx)		(0x0178 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+/* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
+#define RCANFD_CFPCTR(ch, idx)		(0x01d8 + (0x0c * (ch)) + \
+					 (0x04 * (idx)))
+
+/* RSCFDnCFDFESTS / RSCFDnFESTS */
+#define RCANFD_FESTS			(0x0238)
+/* RSCFDnCFDFFSTS / RSCFDnFFSTS */
+#define RCANFD_FFSTS			(0x023c)
+/* RSCFDnCFDFMSTS / RSCFDnFMSTS */
+#define RCANFD_FMSTS			(0x0240)
+/* RSCFDnCFDRFISTS / RSCFDnRFISTS */
+#define RCANFD_RFISTS			(0x0244)
+/* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */
+#define RCANFD_CFRISTS			(0x0248)
+/* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */
+#define RCANFD_CFTISTS			(0x024c)
+
+/* RSCFDnCFDTMCp / RSCFDnTMCp */
+#define RCANFD_TMC(p)			(0x0250 + (0x01 * (p)))
+/* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */
+#define RCANFD_TMSTS(p)			(0x02d0 + (0x01 * (p)))
+
+/* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */
+#define RCANFD_TMTRSTS(y)		(0x0350 + (0x04 * (y)))
+/* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */
+#define RCANFD_TMTARSTS(y)		(0x0360 + (0x04 * (y)))
+/* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */
+#define RCANFD_TMTCSTS(y)		(0x0370 + (0x04 * (y)))
+/* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */
+#define RCANFD_TMTASTS(y)		(0x0380 + (0x04 * (y)))
+/* RSCFDnCFDTMIECy / RSCFDnTMIECy */
+#define RCANFD_TMIEC(y)			(0x0390 + (0x04 * (y)))
+
+/* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */
+#define RCANFD_TXQCC(m)			(0x03a0 + (0x04 * (m)))
+/* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */
+#define RCANFD_TXQSTS(m)		(0x03c0 + (0x04 * (m)))
+/* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */
+#define RCANFD_TXQPCTR(m)		(0x03e0 + (0x04 * (m)))
+
+/* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */
+#define RCANFD_THLCC(m)			(0x0400 + (0x04 * (m)))
+/* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */
+#define RCANFD_THLSTS(m)		(0x0420 + (0x04 * (m)))
+/* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */
+#define RCANFD_THLPCTR(m)		(0x0440 + (0x04 * (m)))
+
+/* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */
+#define RCANFD_GTINTSTS0		(0x0460)
+/* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */
+#define RCANFD_GTINTSTS1		(0x0464)
+/* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */
+#define RCANFD_GTSTCFG			(0x0468)
+/* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */
+#define RCANFD_GTSTCTR			(0x046c)
+/* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
+#define RCANFD_GLOCKK			(0x047c)
+/* RSCFDnCFDGRMCFG / RSCFDnGRMCFG */
+#define RCANFD_GRMCFG			(0x04fc)
+
+/* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
+#define RCANFD_GAFLID(offset, j)	((offset) + (0x10 * (j)))
+/* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
+#define RCANFD_GAFLM(offset, j)		((offset) + 0x04 + (0x10 * (j)))
+/* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
+#define RCANFD_GAFLP0(offset, j)	((offset) + 0x08 + (0x10 * (j)))
+/* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
+#define RCANFD_GAFLP1(offset, j)	((offset) + 0x0c + (0x10 * (j)))
+
+/* CAN FD mode specific regsiter map */
+
+/* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
+#define RCANFD_F_DCFG(m)		(0x0500 + (0x20 * (m)))
+#define RCANFD_F_CFDCFG(m)		(0x0504 + (0x20 * (m)))
+#define RCANFD_F_CFDCTR(m)		(0x0508 + (0x20 * (m)))
+#define RCANFD_F_CFDSTS(m)		(0x050c + (0x20 * (m)))
+#define RCANFD_F_CFDCRC(m)		(0x0510 + (0x20 * (m)))
+
+/* RSCFDnCFDGAFLXXXj offset */
+#define RCANFD_F_GAFL_OFFSET		(0x1000)
+
+/* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
+#define RCANFD_F_RMID(q)		(0x2000 + (0x10 * (q)))
+#define RCANFD_F_RMPTR(q)		(0x2004 + (0x10 * (q)))
+#define RCANFD_F_RMFDSTS(q)		(0x2008 + (0x10 * (q)))
+#define RCANFD_F_RMDF(q, b)		(0x200c + (0x04 * (b)) + (0x20 * (q)))
+
+/* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
+#define RCANFD_F_RFOFFSET		(0x3000)
+#define RCANFD_F_RFID(x)		(RCANFD_F_RFOFFSET + (0x80 * (x)))
+#define RCANFD_F_RFPTR(x)		(RCANFD_F_RFOFFSET + 0x04 + \
+					 (0x80 * (x)))
+#define RCANFD_F_RFFDSTS(x)		(RCANFD_F_RFOFFSET + 0x08 + \
+					 (0x80 * (x)))
+#define RCANFD_F_RFDF(x, df)		(RCANFD_F_RFOFFSET + 0x0c + \
+					 (0x80 * (x)) + (0x04 * (df)))
+
+/* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
+#define RCANFD_F_CFOFFSET		(0x3400)
+#define RCANFD_F_CFID(ch, idx)		(RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
+					 (0x80 * (idx)))
+#define RCANFD_F_CFPTR(ch, idx)		(RCANFD_F_CFOFFSET + 0x04 + \
+					 (0x180 * (ch)) + (0x80 * (idx)))
+#define RCANFD_F_CFFDCSTS(ch, idx)	(RCANFD_F_CFOFFSET + 0x08 + \
+					 (0x180 * (ch)) + (0x80 * (idx)))
+#define RCANFD_F_CFDF(ch, idx, df)	(RCANFD_F_CFOFFSET + 0x0c + \
+					 (0x180 * (ch)) + (0x80 * (idx)) + \
+					 (0x04 * (df)))
+
+/* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
+#define RCANFD_F_TMID(p)		(0x4000 + (0x20 * (p)))
+#define RCANFD_F_TMPTR(p)		(0x4004 + (0x20 * (p)))
+#define RCANFD_F_TMFDCTR(p)		(0x4008 + (0x20 * (p)))
+#define RCANFD_F_TMDF(p, b)		(0x400c + (0x20 * (p)) + (0x04 * (b)))
+
+/* RSCFDnCFDTHLACCm */
+#define RCANFD_F_THLACC(m)		(0x6000 + (0x04 * (m)))
+/* RSCFDnCFDRPGACCr */
+#define RCANFD_F_RPGACC(r)		(0x6400 + (0x04 * (r)))
+
+/* Constants */
+#define RCANFD_FIFO_DEPTH		8	/* Tx FIFO depth */
+#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
+
+#define RCANFD_NUM_CHANNELS		2	/* Two channels max */
+#define RCANFD_CHANNELS_MASK		BIT((RCANFD_NUM_CHANNELS) - 1)
+
+#define RCANFD_GAFL_PAGENUM(entry)	((entry) / 16)
+#define RCANFD_CHANNEL_NUMRULES		1	/* only one rule per channel */
+
+/* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
+ * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
+ * number is added to RFFIFO index.
+ */
+#define RCANFD_RFFIFO_IDX		0
+
+/* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
+ * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
+ */
+#define RCANFD_CFFIFO_IDX		0
+
+/* fCAN clock select register settings */
+enum rcar_canfd_fcanclk {
+	RCANFD_CANFDCLK = 0,		/* CANFD clock */
+	RCANFD_EXTCLK,			/* Externally input clock */
+};
+
+struct rcar_canfd_global;
+
+/* Channel priv data */
+struct rcar_canfd_channel {
+	struct can_priv can;			/* Must be the first member */
+	struct net_device *ndev;
+	struct rcar_canfd_global *gpriv;	/* Controller reference */
+	void __iomem *base;			/* Register base address */
+	struct napi_struct napi;
+	u8  tx_len[RCANFD_FIFO_DEPTH];		/* For net stats */
+	u32 tx_head;				/* Incremented on xmit */
+	u32 tx_tail;				/* Incremented on xmit done */
+	u32 channel;				/* Channel number */
+	spinlock_t tx_lock;			/* To protect tx path */
+};
+
+/* Global priv data */
+struct rcar_canfd_global {
+	struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
+	void __iomem *base;		/* Register base address */
+	struct platform_device *pdev;	/* Respective platform device */
+	struct clk *clkp;		/* Peripheral clock */
+	struct clk *can_clk;		/* fCAN clock */
+	enum rcar_canfd_fcanclk fcan;	/* CANFD or Ext clock */
+	unsigned long channels_mask;	/* Enabled channels mask */
+};
+
+/* CAN FD mode nominal rate constants */
+static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
+	.name = RCANFD_DRV_NAME,
+	.tseg1_min = 2,
+	.tseg1_max = 128,
+	.tseg2_min = 2,
+	.tseg2_max = 32,
+	.sjw_max = 32,
+	.brp_min = 1,
+	.brp_max = 1024,
+	.brp_inc = 1,
+};
+
+/* CAN FD mode data rate constants */
+static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
+	.name = RCANFD_DRV_NAME,
+	.tseg1_min = 2,
+	.tseg1_max = 16,
+	.tseg2_min = 2,
+	.tseg2_max = 8,
+	.sjw_max = 8,
+	.brp_min = 1,
+	.brp_max = 256,
+	.brp_inc = 1,
+};
+
+/* Helper functions */
+static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
+{
+	u32 data = readl(reg);
+
+	data &= ~mask;
+	data |= (val & mask);
+	writel(data, reg);
+}
+
+static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
+{
+	return readl(base + (offset));
+}
+
+static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
+{
+	writel(val, base + (offset));
+}
+
+static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
+{
+	rcar_canfd_update(val, val, base + (reg));
+}
+
+static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
+{
+	rcar_canfd_update(val, 0, base + (reg));
+}
+
+static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
+				  u32 mask, u32 val)
+{
+	rcar_canfd_update(mask, val, base + (reg));
+}
+
+static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
+				struct canfd_frame *cf, u32 off)
+{
+	u32 i, lwords;
+
+	lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
+	for (i = 0; i < lwords; i++)
+		*((u32 *)cf->data + i) =
+			rcar_canfd_read(priv->base, off + (i * sizeof(u32)));
+}
+
+static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
+				struct canfd_frame *cf, u32 off)
+{
+	u32 i, lwords;
+
+	lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
+	for (i = 0; i < lwords; i++)
+		rcar_canfd_write(priv->base, off + (i * sizeof(u32)),
+				 *((u32 *)cf->data + i));
+}
+
+static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
+{
+	u32 i;
+
+	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
+		can_free_echo_skb(ndev, i);
+}
+
+static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
+{
+	u32 sts, ch;
+	int err;
+
+	/* Check RAMINIT flag as CAN RAM initialization takes place
+	 * after the MCU reset
+	 */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
+		return err;
+	}
+
+	/* Transition to Global Reset mode */
+	rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
+	rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
+			      RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET);
+
+	/* Ensure Global reset mode */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
+	if (err) {
+		dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
+		return err;
+	}
+
+	/* Reset Global error flags */
+	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
+
+	/* Set the controller into FD mode */
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG, RCANFD_GRMCFG_RCMC);
+
+	/* Transition all Channels to reset mode */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_clear_bit(gpriv->base,
+				     RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
+
+		rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
+				      RCANFD_CCTR_CHMDC_MASK,
+				      RCANFD_CCTR_CHDMC_CRESET);
+
+		/* Ensure Channel reset mode */
+		err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
+					 (sts & RCANFD_CSTS_CRSTSTS),
+					 2, 500000);
+		if (err) {
+			dev_dbg(&gpriv->pdev->dev,
+				"channel %u reset failed\n", ch);
+			return err;
+		}
+	}
+	return 0;
+}
+
+static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
+{
+	u32 cfg, ch;
+
+	/* Global configuration settings */
+
+	/* Truncate payload to configured message size RFPLS */
+	cfg = RCANFD_GCFG_CMPOC;
+
+	/* Set External Clock if selected */
+	if (gpriv->fcan != RCANFD_CANFDCLK)
+		cfg |= RCANFD_GCFG_DCS;
+
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
+
+	/* Channel configuration settings */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
+				   RCANFD_CCTR_ERRD);
+		rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
+				      RCANFD_CCTR_BOM_MASK,
+				      RCANFD_CCTR_BOM_BENTRY);
+	}
+}
+
+static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
+					   u32 ch)
+{
+	u32 cfg;
+	int start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	if (ch == 0) {
+		start = 0; /* Channel 0 always starts from 0th rule */
+	} else {
+		/* Get number of Channel 0 rules and adjust */
+		cfg = rcar_canfd_read(gpriv->base, RCANFD_GAFLCFG0);
+		start = RCANFD_GAFLCFG_GETRNC(0, cfg);
+	}
+
+	/* Enable write access to entry */
+	page = RCANFD_GAFL_PAGENUM(start);
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
+			   (RCANFD_GAFLECTR_AFLPN(page) |
+			    RCANFD_GAFLECTR_AFLDAE));
+
+	/* Write number of rules for channel */
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG0,
+			   RCANFD_GAFLCFG_SETRNC(ch, num_rules));
+
+	/* Accept all IDs */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_GAFLID(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* IDE or RTR is not considered for matching */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_GAFLM(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* Any data length accepted */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_GAFLP0(RCANFD_F_GAFL_OFFSET, start), 0);
+	/* Place the msg in corresponding Rx FIFO entry */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_GAFLP1(RCANFD_F_GAFL_OFFSET, start),
+			 RCANFD_GAFLP1_GAFLFDP(ridx));
+
+	/* Disable write access to page */
+	rcar_canfd_clear_bit(gpriv->base,
+			     RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE);
+}
+
+static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	/* Rx FIFO is used for reception */
+	u32 cfg;
+	u16 rfdc, rfpls;
+
+	/* Select Rx FIFO based on channel */
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	rfdc = 2;		/* b010 - 8 messages Rx FIFO depth */
+	rfpls = 7;		/* b111 - Max 64 bytes payload */
+
+	cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
+		RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
+	rcar_canfd_write(gpriv->base, RCANFD_RFCC(ridx), cfg);
+}
+
+static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	/* Tx/Rx(Common) FIFO configured in Tx mode is
+	 * used for transmission
+	 *
+	 * Each channel has 3 Common FIFO dedicated to them.
+	 * Use the 1st (index 0) out of 3
+	 */
+	u32 cfg;
+	u16 cftml, cfm, cfdc, cfpls;
+
+	cftml = 0;		/* 0th buffer */
+	cfm = 1;		/* b01 - Transmit mode */
+	cfdc = 2;		/* b010 - 8 messages Tx FIFO depth */
+	cfpls = 7;		/* b111 - Max 64 bytes payload */
+
+	cfg = (RCANFD_CFCC_CFTML(cftml) | RCANFD_CFCC_CFM(cfm) |
+		RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(cfdc) |
+		RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
+	rcar_canfd_write(gpriv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
+
+	/* Clear FD mode specific control/status register */
+	rcar_canfd_write(gpriv->base,
+			 RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
+}
+
+static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
+{
+	u32 ctr;
+
+	/* Clear any stray error interrupt flags */
+	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
+
+	/* Global interrupts setup */
+	ctr = RCANFD_GCTR_MEIE;
+	ctr |= RCANFD_GCTR_CFMPOFIE;
+
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
+}
+
+static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
+						 *gpriv)
+{
+	/* Disable all interrupts */
+	rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
+
+	/* Clear any stray error interrupt flags */
+	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
+}
+
+static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
+						 *priv)
+{
+	u32 ctr, ch = priv->channel;
+
+	/* Clear any stray error flags */
+	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
+
+	/* Channel interrupts setup */
+	ctr = (RCANFD_CCTR_TAIE |
+	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
+	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
+	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
+	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
+	rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
+}
+
+static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
+						  *priv)
+{
+	u32 ctr, ch = priv->channel;
+
+	ctr = (RCANFD_CCTR_TAIE |
+	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
+	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
+	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
+	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
+	rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
+
+	/* Clear any stray error flags */
+	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
+}
+
+static void rcar_canfd_global_error(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 ch = priv->channel;
+	u32 gerfl, sts;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
+	if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
+		netdev_dbg(ndev, "Ch0: ECC Error flag\n");
+		stats->tx_dropped++;
+	}
+	if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
+		netdev_dbg(ndev, "Ch1: ECC Error flag\n");
+		stats->tx_dropped++;
+	}
+	if (gerfl & RCANFD_GERFL_MES) {
+		sts = rcar_canfd_read(priv->base,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		if (sts & RCANFD_CFSTS_CFMLT) {
+			netdev_dbg(ndev, "Tx Message Lost flag\n");
+			stats->tx_dropped++;
+			rcar_canfd_write(priv->base,
+					 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
+					 sts & ~RCANFD_CFSTS_CFMLT);
+		}
+
+		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
+		if (sts & RCANFD_RFSTS_RFMLT) {
+			netdev_dbg(ndev, "Rx Message Lost flag\n");
+			stats->rx_dropped++;
+			rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
+					 sts & ~RCANFD_RFSTS_RFMLT);
+		}
+	}
+	if (gerfl & RCANFD_GERFL_CMPOF) {
+		/* Message Lost flag will be set for respective channel
+		 * when this condition happens with counters and flags
+		 * already updated.
+		 */
+		netdev_dbg(ndev, "global payload overflow interrupt\n");
+	}
+
+	/* Clear all global error interrupts. Only affected channels bits
+	 * get cleared
+	 */
+	rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
+}
+
+static void rcar_canfd_error(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	struct can_frame *cf;
+	struct sk_buff *skb;
+	u32 cerfl, csts;
+	u32 txerr = 0, rxerr = 0;
+	u32 ch = priv->channel;
+
+	/* Propagate the error condition to the CAN stack */
+	skb = alloc_can_err_skb(ndev, &cf);
+	if (!skb) {
+		stats->rx_dropped++;
+		return;
+	}
+
+	/* Channel error interrupt */
+	cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
+	csts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
+	txerr = RCANFD_CSTS_TECCNT(csts);
+	rxerr = RCANFD_CSTS_RECCNT(csts);
+
+	netdev_dbg(ndev, "ch erfl %x sts %x txerr %u rxerr %u\n",
+		   cerfl, csts, txerr, rxerr);
+
+	if (cerfl & RCANFD_CERFL_BEF) {
+		netdev_dbg(ndev, "Bus error\n");
+		cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
+		cf->data[2] = CAN_ERR_PROT_UNSPEC;
+		priv->can.can_stats.bus_error++;
+	}
+	if (cerfl & RCANFD_CERFL_ADERR) {
+		netdev_dbg(ndev, "ACK Delimiter Error\n");
+		stats->tx_errors++;
+		cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
+	}
+	if (cerfl & RCANFD_CERFL_B0ERR) {
+		netdev_dbg(ndev, "Bit Error (dominant)\n");
+		stats->tx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_BIT0;
+	}
+	if (cerfl & RCANFD_CERFL_B1ERR) {
+		netdev_dbg(ndev, "Bit Error (recessive)\n");
+		stats->tx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_BIT1;
+	}
+	if (cerfl & RCANFD_CERFL_CERR) {
+		netdev_dbg(ndev, "CRC Error\n");
+		stats->rx_errors++;
+		cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
+	}
+	if (cerfl & RCANFD_CERFL_AERR) {
+		netdev_dbg(ndev, "ACK Error\n");
+		stats->tx_errors++;
+		cf->can_id |= CAN_ERR_ACK;
+		cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
+	}
+	if (cerfl & RCANFD_CERFL_FERR) {
+		netdev_dbg(ndev, "Form Error\n");
+		stats->rx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_FORM;
+	}
+	if (cerfl & RCANFD_CERFL_SERR) {
+		netdev_dbg(ndev, "Stuff Error\n");
+		stats->rx_errors++;
+		cf->data[2] |= CAN_ERR_PROT_STUFF;
+	}
+	if (cerfl & RCANFD_CERFL_ALF) {
+		netdev_dbg(ndev, "Arbitration lost Error\n");
+		priv->can.can_stats.arbitration_lost++;
+		cf->can_id |= CAN_ERR_LOSTARB;
+		cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
+	}
+	if (cerfl & RCANFD_CERFL_BLF) {
+		netdev_dbg(ndev, "Bus Lock Error\n");
+		stats->rx_errors++;
+		cf->can_id |= CAN_ERR_BUSERROR;
+	}
+	if (cerfl & RCANFD_CERFL_EWF) {
+		netdev_dbg(ndev, "Error warning interrupt\n");
+		priv->can.state = CAN_STATE_ERROR_WARNING;
+		priv->can.can_stats.error_warning++;
+		cf->can_id |= CAN_ERR_CRTL;
+		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
+			CAN_ERR_CRTL_RX_WARNING;
+		cf->data[6] = txerr;
+		cf->data[7] = rxerr;
+	}
+	if (cerfl & RCANFD_CERFL_EPF) {
+		netdev_dbg(ndev, "Error passive interrupt\n");
+		priv->can.state = CAN_STATE_ERROR_PASSIVE;
+		priv->can.can_stats.error_passive++;
+		cf->can_id |= CAN_ERR_CRTL;
+		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
+			CAN_ERR_CRTL_RX_PASSIVE;
+		cf->data[6] = txerr;
+		cf->data[7] = rxerr;
+	}
+	if (cerfl & RCANFD_CERFL_BOEF) {
+		netdev_dbg(ndev, "Bus-off entry interrupt\n");
+		rcar_canfd_tx_failure_cleanup(ndev);
+		priv->can.state = CAN_STATE_BUS_OFF;
+		priv->can.can_stats.bus_off++;
+		can_bus_off(ndev);
+		cf->can_id |= CAN_ERR_BUSOFF;
+	}
+	if (cerfl & RCANFD_CERFL_OVLF) {
+		netdev_dbg(ndev,
+			   "Overload Frame Transmission error interrupt\n");
+		stats->tx_errors++;
+		cf->can_id |= CAN_ERR_PROT;
+		cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
+	}
+
+	/* Clear all channel error interrupts */
+	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
+	stats->rx_packets++;
+	stats->rx_bytes += cf->can_dlc;
+	netif_rx(skb);
+}
+
+static void rcar_canfd_tx_done(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct net_device_stats *stats = &ndev->stats;
+	u32 sts;
+	unsigned long flags;
+	u32 ch = priv->channel;
+
+	do {
+		u8 unsent, sent;
+
+		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
+		stats->tx_packets++;
+		stats->tx_bytes += priv->tx_len[sent];
+		priv->tx_len[sent] = 0;
+		can_get_echo_skb(ndev, sent);
+
+		spin_lock_irqsave(&priv->tx_lock, flags);
+		priv->tx_tail++;
+		sts = rcar_canfd_read(priv->base,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		unsent = RCANFD_CFSTS_CFMC(sts);
+
+		/* Wake producer only when there is room */
+		if (unsent != RCANFD_FIFO_DEPTH)
+			netif_wake_queue(ndev);
+
+		if (priv->tx_head - priv->tx_tail <= unsent) {
+			spin_unlock_irqrestore(&priv->tx_lock, flags);
+			break;
+		}
+		spin_unlock_irqrestore(&priv->tx_lock, flags);
+
+	} while (1);
+
+	/* Clear interrupt */
+	rcar_canfd_write(priv->base, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
+			 sts & ~RCANFD_CFSTS_CFTXIF);
+	can_led_event(ndev, CAN_LED_EVENT_TX);
+}
+
+static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
+{
+	struct rcar_canfd_global *gpriv = dev_id;
+	struct net_device *ndev;
+	struct rcar_canfd_channel *priv;
+	u32 sts, gerfl;
+	u32 ch, ridx;
+
+	/* Global error interrupts still indicate a condition specific
+	 * to a channel. RxFIFO interrupt is a global interrupt.
+	 */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		ndev = priv->ndev;
+		ridx = ch + RCANFD_RFFIFO_IDX;
+
+		/* Global error interrupts */
+		gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
+		if (RCANFD_GERFL_ERR(gerfl))
+			rcar_canfd_global_error(ndev);
+
+		/* Handle Rx interrupts */
+		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
+		if (sts & RCANFD_RFSTS_RFIF) {
+			if (napi_schedule_prep(&priv->napi)) {
+				/* Disable Rx FIFO interrupts */
+				rcar_canfd_clear_bit(priv->base,
+						     RCANFD_RFCC(ridx),
+						     RCANFD_RFCC_RFIE);
+				__napi_schedule(&priv->napi);
+			}
+		}
+	}
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
+{
+	struct rcar_canfd_global *gpriv = dev_id;
+	struct net_device *ndev;
+	struct rcar_canfd_channel *priv;
+	u32 sts, cerfl, ch;
+
+	/* Common FIFO is a per channel resource */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		priv = gpriv->ch[ch];
+		ndev = priv->ndev;
+
+		/* Channel error interrupts */
+		cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
+		if (RCANFD_CERFL_ERR(cerfl))
+			rcar_canfd_error(ndev);
+
+		/* Handle Tx interrupts */
+		sts = rcar_canfd_read(priv->base,
+				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
+		if (sts & RCANFD_CFSTS_CFTXIF)
+			rcar_canfd_tx_done(ndev);
+	}
+	return IRQ_HANDLED;
+}
+
+static void rcar_canfd_set_bittiming(struct net_device *dev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(dev);
+	const struct can_bittiming *bt = &priv->can.bittiming;
+	const struct can_bittiming *dbt = &priv->can.data_bittiming;
+	u16 brp, sjw, tseg1, tseg2;
+	u32 cfg;
+	u32 ch = priv->channel;
+
+	/* Nominal bit timing settings */
+	brp = bt->brp - 1;
+	sjw = bt->sjw - 1;
+	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
+	tseg2 = bt->phase_seg2 - 1;
+
+	cfg = (RCANFD_NCFG_NTSEG1(tseg1) | RCANFD_NCFG_NBRP(brp) |
+	       RCANFD_NCFG_NSJW(sjw) | RCANFD_NCFG_NTSEG2(tseg2));
+
+	rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
+	netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
+		   brp, sjw, tseg1, tseg2);
+
+	/* Data bit timing settings */
+	brp = dbt->brp - 1;
+	sjw = dbt->sjw - 1;
+	tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
+	tseg2 = dbt->phase_seg2 - 1;
+
+	cfg = (RCANFD_DCFG_DTSEG1(tseg1) | RCANFD_DCFG_DBRP(brp) |
+	       RCANFD_DCFG_DSJW(sjw) | RCANFD_DCFG_DTSEG2(tseg2));
+
+	rcar_canfd_write(priv->base, RCANFD_F_DCFG(ch), cfg);
+	netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
+		   brp, sjw, tseg1, tseg2);
+}
+
+static int rcar_canfd_start(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	int err = -EOPNOTSUPP;
+	u32 sts, ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	rcar_canfd_set_bittiming(ndev);
+
+	rcar_canfd_enable_channel_interrupts(priv);
+
+	/* Set channel to Operational mode */
+	rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM);
+
+	/* Verify channel mode change */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_COMSTS), 2, 500000);
+	if (err) {
+		netdev_err(ndev, "channel %u communication state failed\n", ch);
+		goto fail_mode_change;
+	}
+
+	/* Enable Common & Rx FIFO */
+	rcar_canfd_set_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
+			   RCANFD_CFCC_CFE);
+	rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE);
+
+	priv->can.state = CAN_STATE_ERROR_ACTIVE;
+	return 0;
+
+fail_mode_change:
+	rcar_canfd_disable_channel_interrupts(priv);
+	return err;
+}
+
+static int rcar_canfd_open(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct rcar_canfd_global *gpriv = priv->gpriv;
+	int err;
+
+	/* Peripheral clock is already enabled in probe */
+	err = clk_prepare_enable(gpriv->can_clk);
+	if (err) {
+		netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
+		goto out_clock;
+	}
+
+	err = open_candev(ndev);
+	if (err) {
+		netdev_err(ndev, "open_candev() failed, error %d\n", err);
+		goto out_can_clock;
+	}
+
+	napi_enable(&priv->napi);
+	err = rcar_canfd_start(ndev);
+	if (err)
+		goto out_close;
+	netif_start_queue(ndev);
+	can_led_event(ndev, CAN_LED_EVENT_OPEN);
+	return 0;
+out_close:
+	napi_disable(&priv->napi);
+	close_candev(ndev);
+out_can_clock:
+	clk_disable_unprepare(gpriv->can_clk);
+out_clock:
+	return err;
+}
+
+static void rcar_canfd_stop(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	int err;
+	u32 sts, ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	/* Transition to channel reset mode  */
+	rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
+			      RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET);
+
+	/* Check Channel reset mode */
+	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
+				 (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
+	if (err)
+		netdev_err(ndev, "channel %u reset failed\n", ch);
+
+	rcar_canfd_disable_channel_interrupts(priv);
+
+	/* Disable Common & Rx FIFO */
+	rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
+			     RCANFD_CFCC_CFE);
+	rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE);
+
+	/* Set the state as STOPPED */
+	priv->can.state = CAN_STATE_STOPPED;
+}
+
+static int rcar_canfd_close(struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct rcar_canfd_global *gpriv = priv->gpriv;
+
+	netif_stop_queue(ndev);
+	rcar_canfd_stop(ndev);
+	napi_disable(&priv->napi);
+	clk_disable_unprepare(gpriv->can_clk);
+	close_candev(ndev);
+	can_led_event(ndev, CAN_LED_EVENT_STOP);
+	return 0;
+}
+
+static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
+					 struct net_device *ndev)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(ndev);
+	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
+	u32 sts = 0, id, dlc;
+	unsigned long flags;
+	u32 ch = priv->channel;
+
+	if (can_dropped_invalid_skb(ndev, skb))
+		return NETDEV_TX_OK;
+
+	if (cf->can_id & CAN_EFF_FLAG) {
+		id = cf->can_id & CAN_EFF_MASK;
+		id |= RCANFD_CFID_CFIDE;
+	} else {
+		id = cf->can_id & CAN_SFF_MASK;
+	}
+
+	if (cf->can_id & CAN_RTR_FLAG)
+		id |= RCANFD_CFID_CFRTR;
+
+	rcar_canfd_write(priv->base,
+			 RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX), id);
+	dlc = RCANFD_CFPTR_CFDLC(can_len2dlc(cf->len));
+	rcar_canfd_write(priv->base,
+			 RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
+
+	if (can_is_canfd_skb(skb)) {
+		/* CAN FD frame format */
+		sts |= RCANFD_CFFDCSTS_CFFDF;
+		if (cf->flags & CANFD_BRS)
+			sts |= RCANFD_CFFDCSTS_CFBRS;
+
+		if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
+			sts |= RCANFD_CFFDCSTS_CFESI;
+	}
+
+	rcar_canfd_write(priv->base, RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX),
+			 sts);
+
+	rcar_canfd_put_data(priv, cf,
+			    RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
+
+	priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
+	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
+
+	spin_lock_irqsave(&priv->tx_lock, flags);
+	priv->tx_head++;
+
+	/* Stop the queue if we've filled all FIFO entries */
+	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
+		netif_stop_queue(ndev);
+
+	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
+	 * pointer for the Common FIFO
+	 */
+	rcar_canfd_write(priv->base,
+			 RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
+
+	spin_unlock_irqrestore(&priv->tx_lock, flags);
+	return NETDEV_TX_OK;
+}
+
+static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
+{
+	struct net_device_stats *stats = &priv->ndev->stats;
+	struct canfd_frame *cf;
+	struct sk_buff *skb;
+	u32 sts = 0, id, ptr;
+	u32 ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	id = rcar_canfd_read(priv->base, RCANFD_F_RFID(ridx));
+	ptr = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(ridx));
+
+	sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(ridx));
+	if (sts & RCANFD_RFFDSTS_RFFDF)
+		skb = alloc_canfd_skb(priv->ndev, &cf);
+	else
+		skb = alloc_can_skb(priv->ndev,
+				    (struct can_frame **)&cf);
+
+	if (!skb) {
+		stats->rx_dropped++;
+		return;
+	}
+
+	if (sts & RCANFD_RFFDSTS_RFFDF)
+		cf->len = can_dlc2len(RCANFD_RFPTR_RFDLC(ptr));
+	else
+		cf->len = get_can_dlc(RCANFD_RFPTR_RFDLC(ptr));
+
+	if (sts & RCANFD_RFFDSTS_RFESI) {
+		cf->flags |= CANFD_ESI;
+		netdev_dbg(priv->ndev, "ESI Error\n");
+	}
+
+	if (id & RCANFD_RFID_RFIDE)
+		cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+	else
+		cf->can_id = id & CAN_SFF_MASK;
+
+	if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
+		cf->can_id |= CAN_RTR_FLAG;
+	} else {
+		if (sts & RCANFD_RFFDSTS_RFBRS)
+			cf->flags |= CANFD_BRS;
+
+		rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(ridx, 0));
+	}
+
+	/* Write 0xff to RFPC to increment the CPU-side
+	 * pointer of the Rx FIFO
+	 */
+	rcar_canfd_write(priv->base, RCANFD_RFPCTR(ridx), 0xff);
+
+	can_led_event(priv->ndev, CAN_LED_EVENT_RX);
+
+	stats->rx_bytes += cf->len;
+	stats->rx_packets++;
+	netif_receive_skb(skb);
+}
+
+static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
+{
+	struct rcar_canfd_channel *priv =
+		container_of(napi, struct rcar_canfd_channel, napi);
+	int num_pkts;
+	u32 sts;
+	u32 ch = priv->channel;
+	u32 ridx = ch + RCANFD_RFFIFO_IDX;
+
+	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
+		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
+		/* Check FIFO empty condition */
+		if (sts & RCANFD_RFSTS_RFEMP)
+			break;
+
+		rcar_canfd_rx_pkt(priv);
+
+		/* Clear interrupt bit */
+		if (sts & RCANFD_RFSTS_RFIF)
+			rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
+					 sts & ~RCANFD_RFSTS_RFIF);
+	}
+
+	/* All packets processed */
+	if (num_pkts < quota) {
+		napi_complete(napi);
+		/* Enable Rx FIFO interrupts */
+		rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx),
+				   RCANFD_RFCC_RFIE);
+	}
+	return num_pkts;
+}
+
+static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
+{
+	int err;
+
+	switch (mode) {
+	case CAN_MODE_START:
+		err = rcar_canfd_start(ndev);
+		if (err)
+			return err;
+		netif_wake_queue(ndev);
+		return 0;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int rcar_canfd_get_berr_counter(const struct net_device *dev,
+				       struct can_berr_counter *bec)
+{
+	struct rcar_canfd_channel *priv = netdev_priv(dev);
+	u32 val, ch = priv->channel;
+
+	/* Peripheral clock is already enabled in probe */
+	val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
+	bec->txerr = RCANFD_CSTS_TECCNT(val);
+	bec->rxerr = RCANFD_CSTS_RECCNT(val);
+	return 0;
+}
+
+static const struct net_device_ops rcar_canfd_netdev_ops = {
+	.ndo_open = rcar_canfd_open,
+	.ndo_stop = rcar_canfd_close,
+	.ndo_start_xmit = rcar_canfd_start_xmit,
+	.ndo_change_mtu = can_change_mtu,
+};
+
+static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
+				    u32 fcan_freq)
+{
+	struct platform_device *pdev = gpriv->pdev;
+	struct rcar_canfd_channel *priv;
+	struct net_device *ndev;
+	int err = -ENODEV;
+
+	ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
+	if (!ndev) {
+		dev_err(&pdev->dev, "alloc_candev() failed\n");
+		err = -ENOMEM;
+		goto fail;
+	}
+	priv = netdev_priv(ndev);
+
+	ndev->netdev_ops = &rcar_canfd_netdev_ops;
+	ndev->flags |= IFF_ECHO;
+	priv->ndev = ndev;
+	priv->base = gpriv->base;
+	priv->channel = ch;
+	priv->can.clock.freq = fcan_freq;
+	dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
+
+	priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
+	priv->can.data_bittiming_const =
+		&rcar_canfd_data_bittiming_const;
+
+	/* Controller starts in CAN FD only mode */
+	can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
+	priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
+
+	priv->can.do_set_mode = rcar_canfd_do_set_mode;
+	priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
+	priv->gpriv = gpriv;
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+
+	netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
+		       RCANFD_NAPI_WEIGHT);
+	err = register_candev(ndev);
+	if (err) {
+		dev_err(&pdev->dev,
+			"register_candev() failed, error %d\n", err);
+		goto fail_candev;
+	}
+	spin_lock_init(&priv->tx_lock);
+	devm_can_led_init(ndev);
+	gpriv->ch[priv->channel] = priv;
+	dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
+	return 0;
+
+fail_candev:
+	netif_napi_del(&priv->napi);
+	free_candev(ndev);
+fail:
+	return err;
+}
+
+static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
+{
+	struct rcar_canfd_channel *priv = gpriv->ch[ch];
+
+	if (priv) {
+		unregister_candev(priv->ndev);
+		netif_napi_del(&priv->napi);
+		free_candev(priv->ndev);
+	}
+}
+
+static int rcar_canfd_probe(struct platform_device *pdev)
+{
+	struct resource *mem;
+	void __iomem *addr;
+	u32 sts, ch, fcan_freq;
+	struct rcar_canfd_global *gpriv;
+	struct device_node *of_child;
+	unsigned long channels_mask = 0;
+	int err, ch_irq, g_irq;
+
+	of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
+	if (of_child && of_device_is_available(of_child))
+		channels_mask |= BIT(0);	/* Channel 0 */
+
+	of_child = of_get_child_by_name(pdev->dev.of_node, "channel1");
+	if (of_child && of_device_is_available(of_child))
+		channels_mask |= BIT(1);	/* Channel 1 */
+
+	ch_irq = platform_get_irq(pdev, 0);
+	if (ch_irq < 0) {
+		dev_err(&pdev->dev, "no Channel IRQ resource\n");
+		err = ch_irq;
+		goto fail_dev;
+	}
+
+	g_irq = platform_get_irq(pdev, 1);
+	if (g_irq < 0) {
+		dev_err(&pdev->dev, "no Global IRQ resource\n");
+		err = g_irq;
+		goto fail_dev;
+	}
+
+	/* Global controller context */
+	gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
+	if (!gpriv) {
+		err = -ENOMEM;
+		goto fail_dev;
+	}
+	gpriv->pdev = pdev;
+	gpriv->channels_mask = channels_mask;
+
+	/* Peripheral clock */
+	gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
+	if (IS_ERR(gpriv->clkp)) {
+		err = PTR_ERR(gpriv->clkp);
+		dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
+			err);
+		goto fail_dev;
+	}
+
+	/* fCAN clock: Pick External clock. If not available fallback to
+	 * CANFD clock
+	 */
+	gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
+	if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
+		gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
+		if (IS_ERR(gpriv->can_clk)) {
+			err = PTR_ERR(gpriv->can_clk);
+			dev_err(&pdev->dev,
+				"cannot get canfd clock, error %d\n", err);
+			goto fail_dev;
+		}
+		gpriv->fcan = RCANFD_CANFDCLK;
+
+	} else {
+		gpriv->fcan = RCANFD_EXTCLK;
+	}
+	fcan_freq = clk_get_rate(gpriv->can_clk);
+
+	if (gpriv->fcan == RCANFD_CANFDCLK)
+		/* CANFD clock is further divided by (1/2) within the IP */
+		fcan_freq /= 2;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	addr = devm_ioremap_resource(&pdev->dev, mem);
+	if (IS_ERR(addr)) {
+		err = PTR_ERR(addr);
+		goto fail_dev;
+	}
+	gpriv->base = addr;
+
+	/* Request IRQ that's common for both channels */
+	err = devm_request_irq(&pdev->dev, ch_irq,
+			       rcar_canfd_channel_interrupt, 0,
+			       "canfd.chn", gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+			ch_irq, err);
+		goto fail_dev;
+	}
+	err = devm_request_irq(&pdev->dev, g_irq,
+			       rcar_canfd_global_interrupt, 0,
+			       "canfd.gbl", gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
+			g_irq, err);
+		goto fail_dev;
+	}
+
+	/* Enable peripheral clock for register access */
+	err = clk_prepare_enable(gpriv->clkp);
+	if (err) {
+		dev_err(&pdev->dev,
+			"failed to enable peripheral clock, error %d\n", err);
+		goto fail_dev;
+	}
+
+	err = rcar_canfd_reset_controller(gpriv);
+	if (err) {
+		dev_err(&pdev->dev, "reset controller failed\n");
+		goto fail_clk;
+	}
+
+	/* Controller in Global reset & Channel reset mode */
+	rcar_canfd_configure_controller(gpriv);
+
+	/* Configure per channel attributes */
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		/* Configure Channel's Rx fifo */
+		rcar_canfd_configure_rx(gpriv, ch);
+
+		/* Configure Channel's Tx (Common) fifo */
+		rcar_canfd_configure_tx(gpriv, ch);
+
+		/* Configure receive rules */
+		rcar_canfd_configure_afl_rules(gpriv, ch);
+	}
+
+	/* Configure common interrupts */
+	rcar_canfd_enable_global_interrupts(gpriv);
+
+	/* Start Global operation mode */
+	rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
+			      RCANFD_GCTR_GMDC_GOPM);
+
+	/* Verify mode change */
+	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
+				 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
+	if (err) {
+		dev_err(&pdev->dev, "global operational mode failed\n");
+		goto fail_mode;
+	}
+
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq);
+		if (err)
+			goto fail_channel;
+	}
+
+	platform_set_drvdata(pdev, gpriv);
+	dev_info(&pdev->dev, "global operational state (clk %d)\n",
+		 gpriv->fcan);
+	return 0;
+
+fail_channel:
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
+		rcar_canfd_channel_remove(gpriv, ch);
+fail_mode:
+	rcar_canfd_disable_global_interrupts(gpriv);
+fail_clk:
+	clk_disable_unprepare(gpriv->clkp);
+fail_dev:
+	return err;
+}
+
+static int rcar_canfd_remove(struct platform_device *pdev)
+{
+	struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
+	u32 ch;
+
+	rcar_canfd_reset_controller(gpriv);
+	rcar_canfd_disable_global_interrupts(gpriv);
+
+	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
+		rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
+		rcar_canfd_channel_remove(gpriv, ch);
+	}
+
+	/* Enter global sleep mode */
+	rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
+	clk_disable_unprepare(gpriv->clkp);
+	return 0;
+}
+
+static int __maybe_unused rcar_canfd_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int __maybe_unused rcar_canfd_resume(struct device *dev)
+{
+	return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
+			 rcar_canfd_resume);
+
+static const struct of_device_id rcar_canfd_of_table[] = {
+	{ .compatible = "renesas,rcar-gen3-canfd" },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
+
+static struct platform_driver rcar_canfd_driver = {
+	.driver = {
+		.name = RCANFD_DRV_NAME,
+		.of_match_table = of_match_ptr(rcar_canfd_of_table),
+		.pm = &rcar_canfd_pm_ops,
+	},
+	.probe = rcar_canfd_probe,
+	.remove = rcar_canfd_remove,
+};
+
+module_platform_driver(rcar_canfd_driver);
+
+MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
+MODULE_ALIAS("platform:" RCANFD_DRV_NAME);
-- 
1.9.1

[PATCH v6 2/2] can: rcar_can: Move Renesas CAN driver to rcar dir

[Ramesh Shanmugasundaram]

This patch clubs the Renesas controller drivers in one rcar dir.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
---
 drivers/net/can/Kconfig               | 10 ----------
 drivers/net/can/Makefile              |  1 -
 drivers/net/can/rcar/Kconfig          | 10 ++++++++++
 drivers/net/can/rcar/Makefile         |  3 ++-
 drivers/net/can/{ => rcar}/rcar_can.c |  0
 5 files changed, 12 insertions(+), 12 deletions(-)
 rename drivers/net/can/{ => rcar}/rcar_can.c (100%)

diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 13003a9..22570ea 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -104,16 +104,6 @@ config CAN_JANZ_ICAN3
 	  This driver can also be built as a module. If so, the module will be
 	  called janz-ican3.ko.
 
-config CAN_RCAR
-	tristate "Renesas R-Car CAN controller"
-	depends on ARCH_RENESAS || ARM
-	---help---
-	  Say Y here if you want to use CAN controller found on Renesas R-Car
-	  SoCs.
-
-	  To compile this driver as a module, choose M here: the module will
-	  be called rcar_can.
-
 config CAN_SUN4I
 	tristate "Allwinner A10 CAN controller"
 	depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index 226d5b5..26ba4b7 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_CAN_IFI_CANFD)	+= ifi_canfd/
 obj-$(CONFIG_CAN_JANZ_ICAN3)	+= janz-ican3.o
 obj-$(CONFIG_CAN_MSCAN)		+= mscan/
 obj-$(CONFIG_CAN_M_CAN)		+= m_can/
-obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
 obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
 obj-$(CONFIG_CAN_SUN4I)		+= sun4i_can.o
 obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
diff --git a/drivers/net/can/rcar/Kconfig b/drivers/net/can/rcar/Kconfig
index 6ea64d1..7b03a3a 100644
--- a/drivers/net/can/rcar/Kconfig
+++ b/drivers/net/can/rcar/Kconfig
@@ -1,3 +1,13 @@
+config CAN_RCAR
+	tristate "Renesas R-Car CAN controller"
+	depends on ARCH_RENESAS || ARM
+	---help---
+	  Say Y here if you want to use CAN controller found on Renesas R-Car
+	  SoCs.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called rcar_can.
+
 config CAN_RCAR_CANFD
 	tristate "Renesas R-Car CAN FD controller"
 	depends on ARCH_RENESAS || ARM
diff --git a/drivers/net/can/rcar/Makefile b/drivers/net/can/rcar/Makefile
index cbaf498e..08de36a 100644
--- a/drivers/net/can/rcar/Makefile
+++ b/drivers/net/can/rcar/Makefile
@@ -1,5 +1,6 @@
 #
-#  Makefile for the Renesas R-Car CAN FD controller driver
+#  Makefile for the Renesas R-Car CAN & CAN FD controller drivers
 #
 
+obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
 obj-$(CONFIG_CAN_RCAR_CANFD)	+= rcar_canfd.o
diff --git a/drivers/net/can/rcar_can.c b/drivers/net/can/rcar/rcar_can.c
similarity index 100%
rename from drivers/net/can/rcar_can.c
rename to drivers/net/can/rcar/rcar_can.c
-- 
1.9.1

RE: [PATCH v6 0/2] Add CAN FD driver support to r8a7795 SoC

[Chris Paterson]

Hello Ulrich, Oliver, David,

> 	* Addressed Ulrich's concerns on register, bits naming convention
Are Ramesh's proposed changes acceptable with you?


Kind regards, Chris


> -----Original Message-----
> From: Ramesh Shanmugasundaram
> [mailto:ramesh.shanmugasundaram@bp.renesas.com]
> Sent: 08 June 2016 07:38
> To: mkl@pengutronix.de; wg@grandegger.com; socketcan@hartkopp.net
> Cc: linux-can@vger.kernel.org; netdev@vger.kernel.org; Chris Paterson
> <Chris.Paterson2@renesas.com>; horms@verge.net.au;
> magnus.damm@gmail.com; ulrich.hecht@gmail.com; Ramesh
> Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
> Subject: [PATCH v6 0/2] Add CAN FD driver support to r8a7795 SoC
> 
> Hi All,
> 
>    This patch is based on can-next latest tag "linux-can-next-for-4.7-20160509"
> 
> Changes since v5:
> 	* Addressed Ulrich's concerns on register, bits naming convention
> 	* Rebased to latest tag (linux-can-next-for-4.7-20160509)
> 
> Changes since v4:
> 	* Rebased to latest can-next/testing branch
> 	* Addressed Marc K review comments on v2 patch
> 	* Use clk_get_rate() to find ext clock availability. Refer thread
> 	(https://lkml.org/lkml/2016/4/8/203)
> 
> Changes since v3:
> 	* Split v3 patch into two (Marc K)
> 	  (1) Introduce rcar_canfd.c driver in drivers/net/can/rcar dir
> 	  (2) Move rcar_can.c driver to new drivers/net/can/rcar dir
> 	* Added Acked-by Rob H for the bindings
> 	* Added comments on CAN FD only mode in driver & Kconfig (Oliver
> H)
> 
> Changes since v2:
> 	* Rebased to latest tag (linux-can-next-for-4.6-20160310)
> 	* Cleaned up leftover debugfs code (Thanks Oliver H)
> 	* Revised devicetree documentation text (as suggested by Rob H)
> 	  (https://www.mail-archive.com/linux-renesas-
> soc@vger.kernel.org/msg01597.html)
> 	* Used new can subsystem api to set static configuration & removed
> check in rcar_canfd_start (as suggested by Oliver H)
> 	  (Refer: http://comments.gmane.org/gmane.linux.can/9126 &
> 	   https://www.mail-archive.com/linux-renesas-
> soc@vger.kernel.org/msg01867.html)
> 	* Clubbed Renesas controller drivers to driver/net/can/rcar dir (as
> suggested by Oliver H)
> 	* Updated commit message
> 
> Changes since v1:
> 	* Removed testmodes & debugfs code (suggested by Oliver H)
> 	* Fixed tx path race issue by introducing lock (suggested by Marc K)
> 	* Removed __maybe_unused attribute of rcar_canfd_of_table
> 
> 
> Ramesh Shanmugasundaram (2):
>   can: rcar_canfd: Add Renesas R-Car CAN FD driver
>   can: rcar_can: Move Renesas CAN driver to rcar dir
> 
>  .../devicetree/bindings/net/can/rcar_canfd.txt     |   89 +
>  drivers/net/can/Kconfig                            |   11 +-
>  drivers/net/can/Makefile                           |    2 +-
>  drivers/net/can/rcar/Kconfig                       |   21 +
>  drivers/net/can/rcar/Makefile                      |    6 +
>  drivers/net/can/{ => rcar}/rcar_can.c              |    0
>  drivers/net/can/rcar/rcar_canfd.c                  | 1695 ++++++++++++++++++++
>  7 files changed, 1813 insertions(+), 11 deletions(-)  create mode 100644
> Documentation/devicetree/bindings/net/can/rcar_canfd.txt
>  create mode 100644 drivers/net/can/rcar/Kconfig  create mode 100644
> drivers/net/can/rcar/Makefile  rename drivers/net/can/{ => rcar}/rcar_can.c
> (100%)  create mode 100644 drivers/net/can/rcar/rcar_canfd.c
> 
> --
> 1.9.1

Re: [PATCH v6 1/2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ulrich Hecht]

Thanks for the patch, this is a lot easier to handle.

On Wed, Jun 8, 2016 at 8:38 AM, Ramesh Shanmugasundaram
<ramesh.shanmugasundaram@bp.renesas.com> wrote:
[...]
> diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
> new file mode 100644
> index 0000000..9f1f513
> --- /dev/null
> +++ b/drivers/net/can/rcar/rcar_canfd.c
> @@ -0,0 +1,1695 @@
> +/* Renesas R-Car CAN FD device driver
> + *
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +
> +/* The R-Car CAN FD controller can operate in either one of the below two modes
> + *  - CAN FD only mode
> + *  - Classical CAN (CAN 2.0) only mode
> + *
> + * This driver puts the controller in CAN FD only mode by default. In this
> + * mode, the controller acts as a CAN FD node that can also interoperate with
> + * CAN 2.0 nodes.
> + *
> + * As of now, this driver does not support the Classical CAN (CAN 2.0) mode,
> + * which is handled by a different register map compared to CAN FD only mode.
> + *
> + * Note: The h/w manual register naming convention is clumsy and not acceptable
> + * to use as it is in the driver. However, those names are added as comments
> + * wherever it is modified to a readable name.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/interrupt.h>
> +#include <linux/errno.h>
> +#include <linux/netdevice.h>
> +#include <linux/platform_device.h>
> +#include <linux/can/led.h>
> +#include <linux/can/dev.h>
> +#include <linux/clk.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/bitmap.h>
> +#include <linux/bitops.h>
> +#include <linux/iopoll.h>
> +
> +#define RCANFD_DRV_NAME                        "rcar_canfd"
> +
> +/* Global register bits */
> +
> +/* RSCFDnCFDGRMCFG */
> +#define RCANFD_GRMCFG_RCMC             BIT(0)
> +
> +/* RSCFDnCFDGCFG */
> +#define RCANFD_GCFG_CMPOC              BIT(5)
> +#define RCANFD_GCFG_DCS                        BIT(4)
> +#define RCANFD_GCFG_DCE                        BIT(1)
> +#define RCANFD_GCFG_TPRI               BIT(0)
> +
> +/* RSCFDnCFDGCTR */
> +#define RCANFD_GCTR_TSRST              BIT(16)
> +#define RCANFD_GCTR_CFMPOFIE           BIT(11)
> +#define RCANFD_GCTR_THLEIE             BIT(10)
> +#define RCANFD_GCTR_MEIE               BIT(9)
> +#define RCANFD_GCTR_DEIE               BIT(8)
> +#define RCANFD_GCTR_GSLPR              BIT(2)
> +#define RCANFD_GCTR_GMDC_MASK          (0x3)
> +#define RCANFD_GCTR_GMDC_GOPM          (0x0)
> +#define RCANFD_GCTR_GMDC_GRESET                (0x1)
> +#define RCANFD_GCTR_GMDC_GTEST         (0x2)
> +
> +/* RSCFDnCFDGSTS */
> +#define RCANFD_GSTS_GRAMINIT           BIT(3)
> +#define RCANFD_GSTS_GSLPSTS            BIT(2)
> +#define RCANFD_GSTS_GHLTSTS            BIT(1)
> +#define RCANFD_GSTS_GRSTSTS            BIT(0)
> +/* Non-operational status */
> +#define RCANFD_GSTS_GNOPM              (BIT(0) | BIT(1) | BIT(2) | BIT(3))
> +
> +/* RSCFDnCFDGERFL */
> +#define RCANFD_GERFL_EEF1              BIT(17)
> +#define RCANFD_GERFL_EEF0              BIT(16)
> +#define RCANFD_GERFL_CMPOF             BIT(3)
> +#define RCANFD_GERFL_THLES             BIT(2)
> +#define RCANFD_GERFL_MES               BIT(1)
> +#define RCANFD_GERFL_DEF               BIT(0)
> +
> +#define RCANFD_GERFL_ERR(x)            ((x) & (RCANFD_GERFL_EEF1 |\
> +                                               RCANFD_GERFL_EEF0 |\
> +                                               RCANFD_GERFL_MES |\
> +                                               RCANFD_GERFL_CMPOF))
> +
> +/* AFL Rx rules registers */
> +
> +/* RSCFDnCFDGAFLCFG0 */
> +#define RCANFD_GAFLCFG_SETRNC(n, x)    (((x) & 0xff) << (24 - n * 8))
> +#define RCANFD_GAFLCFG_GETRNC(n, x)    (((x) >> (24 - n * 8)) & 0xff)
> +
> +/* RSCFDnCFDGAFLECTR */
> +#define RCANFD_GAFLECTR_AFLDAE         BIT(8)
> +#define RCANFD_GAFLECTR_AFLPN(x)       ((x) & 0x1f)
> +
> +/* RSCFDnCFDGAFLIDj */
> +#define RCANFD_GAFLID_GAFLLB           BIT(29)
> +
> +/* RSCFDnCFDGAFLP1_j */
> +#define RCANFD_GAFLP1_GAFLFDP(x)       (1 << (x))
> +
> +/* Channel register bits */
> +
> +/* RSCFDnCFDCmNCFG */
> +#define RCANFD_NCFG_NTSEG2(x)          (((x) & 0x1f) << 24)
> +#define RCANFD_NCFG_NTSEG1(x)          (((x) & 0x7f) << 16)
> +#define RCANFD_NCFG_NSJW(x)            (((x) & 0x1f) << 11)
> +#define RCANFD_NCFG_NBRP(x)            (((x) & 0x3ff) << 0)
> +
> +/* RSCFDnCFDCmCTR */
> +#define RCANFD_CCTR_CTME               BIT(24)
> +#define RCANFD_CCTR_ERRD               BIT(23)
> +#define RCANFD_CCTR_BOM_MASK           (0x3 << 21)
> +#define RCANFD_CCTR_BOM_ISO            (0x0 << 21)
> +#define RCANFD_CCTR_BOM_BENTRY         (0x1 << 21)
> +#define RCANFD_CCTR_BOM_BEND           (0x2 << 21)
> +#define RCANFD_CCTR_TDCVFIE            BIT(19)
> +#define RCANFD_CCTR_SOCOIE             BIT(18)
> +#define RCANFD_CCTR_EOCOIE             BIT(17)
> +#define RCANFD_CCTR_TAIE               BIT(16)
> +#define RCANFD_CCTR_ALIE               BIT(15)
> +#define RCANFD_CCTR_BLIE               BIT(14)
> +#define RCANFD_CCTR_OLIE               BIT(13)
> +#define RCANFD_CCTR_BORIE              BIT(12)
> +#define RCANFD_CCTR_BOEIE              BIT(11)
> +#define RCANFD_CCTR_EPIE               BIT(10)
> +#define RCANFD_CCTR_EWIE               BIT(9)
> +#define RCANFD_CCTR_BEIE               BIT(8)
> +#define RCANFD_CCTR_CSLPR              BIT(2)
> +#define RCANFD_CCTR_CHMDC_MASK         (0x3)
> +#define RCANFD_CCTR_CHDMC_COPM         (0x0)
> +#define RCANFD_CCTR_CHDMC_CRESET       (0x1)
> +#define RCANFD_CCTR_CHDMC_CHLT         (0x2)
> +
> +/* RSCFDnCFDCmSTS */
> +#define RCANFD_CSTS_COMSTS             BIT(7)
> +#define RCANFD_CSTS_RECSTS             BIT(6)
> +#define RCANFD_CSTS_TRMSTS             BIT(5)
> +#define RCANFD_CSTS_BOSTS              BIT(4)
> +#define RCANFD_CSTS_EPSTS              BIT(3)
> +#define RCANFD_CSTS_SLPSTS             BIT(2)
> +#define RCANFD_CSTS_HLTSTS             BIT(1)
> +#define RCANFD_CSTS_CRSTSTS            BIT(0)
> +
> +#define RCANFD_CSTS_TECCNT(x)          (((x) >> 24) & 0xff)
> +#define RCANFD_CSTS_RECCNT(x)          (((x) >> 16) & 0xff)
> +
> +/* RSCFDnCFDCmERFL */
> +#define RCANFD_CERFL_ADERR             BIT(14)
> +#define RCANFD_CERFL_B0ERR             BIT(13)
> +#define RCANFD_CERFL_B1ERR             BIT(12)
> +#define RCANFD_CERFL_CERR              BIT(11)
> +#define RCANFD_CERFL_AERR              BIT(10)
> +#define RCANFD_CERFL_FERR              BIT(9)
> +#define RCANFD_CERFL_SERR              BIT(8)
> +#define RCANFD_CERFL_ALF               BIT(7)
> +#define RCANFD_CERFL_BLF               BIT(6)
> +#define RCANFD_CERFL_OVLF              BIT(5)
> +#define RCANFD_CERFL_BORF              BIT(4)
> +#define RCANFD_CERFL_BOEF              BIT(3)
> +#define RCANFD_CERFL_EPF               BIT(2)
> +#define RCANFD_CERFL_EWF               BIT(1)
> +#define RCANFD_CERFL_BEF               BIT(0)
> +
> +#define RCANFD_CERFL_ERR(x)            ((x) & (0x7fff)) /* above bits 14:0 */
> +
> +/* RSCFDnCFDCmDCFG */
> +#define RCANFD_DCFG_DSJW(x)            (((x) & 0x7) << 24)
> +#define RCANFD_DCFG_DTSEG2(x)          (((x) & 0x7) << 20)
> +#define RCANFD_DCFG_DTSEG1(x)          (((x) & 0xf) << 16)
> +#define RCANFD_DCFG_DBRP(x)            (((x) & 0xff) << 0)
> +
> +/* RSCFDnCFDCmFDCFG */
> +#define RCANFD_FDCFG_TDCE              BIT(9)
> +#define RCANFD_FDCFG_TDCOC             BIT(8)
> +#define RCANFD_FDCFG_TDCO(x)           (((x) & 0x7f) >> 16)
> +
> +/* RSCFDnCFDRFCCx */
> +#define RCANFD_RFCC_RFIM               BIT(12)
> +#define RCANFD_RFCC_RFDC(x)            (((x) & 0x7) << 8)
> +#define RCANFD_RFCC_RFPLS(x)           (((x) & 0x7) << 4)
> +#define RCANFD_RFCC_RFIE               BIT(1)
> +#define RCANFD_RFCC_RFE                        BIT(0)
> +
> +/* RSCFDnCFDRFSTSx */
> +#define RCANFD_RFSTS_RFIF              BIT(3)
> +#define RCANFD_RFSTS_RFMLT             BIT(2)
> +#define RCANFD_RFSTS_RFFLL             BIT(1)
> +#define RCANFD_RFSTS_RFEMP             BIT(0)
> +
> +/* RSCFDnCFDRFIDx */
> +#define RCANFD_RFID_RFIDE              BIT(31)
> +#define RCANFD_RFID_RFRTR              BIT(30)
> +
> +/* RSCFDnCFDRFPTRx */
> +#define RCANFD_RFPTR_RFDLC(x)          (((x) >> 28) & 0xf)
> +#define RCANFD_RFPTR_RFPTR(x)          (((x) >> 16) & 0xfff)
> +#define RCANFD_RFPTR_RFTS(x)           (((x) >> 0) & 0xff)

That should be "(((x) >> 0) & 0xffff)".

> +
> +/* RSCFDnCFDRFFDSTSx */
> +#define RCANFD_RFFDSTS_RFFDF           BIT(2)
> +#define RCANFD_RFFDSTS_RFBRS           BIT(1)
> +#define RCANFD_RFFDSTS_RFESI           BIT(0)
> +
> +/* Common FIFO bits */
> +
> +/* RSCFDnCFDCFCCk */
> +#define RCANFD_CFCC_CFTML(x)           (((x) & 0xf) << 20)
> +#define RCANFD_CFCC_CFM(x)             (((x) & 0x3) << 16)
> +#define RCANFD_CFCC_CFIM               BIT(12)
> +#define RCANFD_CFCC_CFDC(x)            (((x) & 0x7) << 8)
> +#define RCANFD_CFCC_CFPLS(x)           (((x) & 0x7) << 4)
> +#define RCANFD_CFCC_CFTXIE             BIT(2)
> +#define RCANFD_CFCC_CFE                        BIT(0)
> +
> +/* RSCFDnCFDCFSTSk */
> +#define RCANFD_CFSTS_CFMC(x)           (((x) >> 8) & 0xff)
> +#define RCANFD_CFSTS_CFTXIF            BIT(4)
> +#define RCANFD_CFSTS_CFMLT             BIT(2)
> +#define RCANFD_CFSTS_CFFLL             BIT(1)
> +#define RCANFD_CFSTS_CFEMP             BIT(0)
> +
> +/* RSCFDnCFDCFIDk */
> +#define RCANFD_CFID_CFIDE              BIT(31)
> +#define RCANFD_CFID_CFRTR              BIT(30)
> +#define RCANFD_CFID_CFID_MASK(x)       ((x) & 0x1fffffff)
> +
> +/* RSCFDnCFDCFPTRk */
> +#define RCANFD_CFPTR_CFDLC(x)          (((x) & 0xf) << 28)
> +#define RCANFD_CFPTR_CFPTR(x)          (((x) & 0xfff) << 16)
> +#define RCANFD_CFPTR_CFTS(x)           (((x) & 0xff) << 0)
> +
> +/* RSCFDnCFDCFFDCSTSk */
> +#define RCANFD_CFFDCSTS_CFFDF          BIT(2)
> +#define RCANFD_CFFDCSTS_CFBRS          BIT(1)
> +#define RCANFD_CFFDCSTS_CFESI          BIT(0)
> +
> +/* This controller supports classical CAN only mode or CAN FD only mode. These
> + * modes are supported in two separate set of register maps & names. However,
> + * some of the register offsets are common for both modes. Those offsets are
> + * listed below as Common registers.
> + *
> + * The CAN FD only specific registers are listed separately and their names
> + * starts with RCANFD_F_xxx names. When classical CAN only specific registers
> + * are added, those specific registers can be prefixed as RCANFD_C_xxx.
> + */
> +
> +/* Common registers */
> +
> +/* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
> +#define RCANFD_CCFG(m)                 (0x0000 + (0x10 * (m)))
> +/* RSCFDnCFDCmCTR / RSCFDnCmCTR */
> +#define RCANFD_CCTR(m)                 (0x0004 + (0x10 * (m)))
> +/* RSCFDnCFDCmSTS / RSCFDnCmSTS */
> +#define RCANFD_CSTS(m)                 (0x0008 + (0x10 * (m)))
> +/* RSCFDnCFDCmERFL / RSCFDnCmERFL */
> +#define RCANFD_CERFL(m)                        (0x000C + (0x10 * (m)))
> +
> +/* RSCFDnCFDGCFG / RSCFDnGCFG */
> +#define RCANFD_GCFG                    (0x0084)
> +/* RSCFDnCFDGCTR / RSCFDnGCTR */
> +#define RCANFD_GCTR                    (0x0088)
> +/* RSCFDnCFDGCTS / RSCFDnGCTS */
> +#define RCANFD_GSTS                    (0x008c)
> +/* RSCFDnCFDGERFL / RSCFDnGERFL */
> +#define RCANFD_GERFL                   (0x0090)
> +/* RSCFDnCFDGTSC / RSCFDnGTSC */
> +#define RCANFD_GTSC                    (0x0094)
> +/* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
> +#define RCANFD_GAFLECTR                        (0x0098)
> +/* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
> +#define RCANFD_GAFLCFG0                        (0x009c)
> +/* RSCFDnCFDGAFLCFG1 / RSCFDnGAFLCFG1 */
> +#define RCANFD_GAFLCFG1                        (0x00a0)
> +/* RSCFDnCFDRMNB / RSCFDnRMNB */
> +#define RCANFD_RMNB                    (0x00a4)
> +/* RSCFDnCFDRMND / RSCFDnRMND */
> +#define RCANFD_RMND(y)                 (0x00a8 + (0x04 * (y)))
> +
> +/* RSCFDnCFDRFCCx / RSCFDnRFCCx */
> +#define RCANFD_RFCC(x)                 (0x00b8 + (0x04 * (x)))
> +/* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
> +#define RCANFD_RFSTS(x)                        (0x00d8 + (0x04 * (x)))
> +/* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
> +#define RCANFD_RFPCTR(x)               (0x00f8 + (0x04 * (x)))
> +
> +/* Common FIFO Control registers */
> +
> +/* RSCFDnCFDCFCCx / RSCFDnCFCCx */
> +#define RCANFD_CFCC(ch, idx)           (0x0118 + (0x0c * (ch)) + \
> +                                        (0x04 * (idx)))
> +/* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
> +#define RCANFD_CFSTS(ch, idx)          (0x0178 + (0x0c * (ch)) + \
> +                                        (0x04 * (idx)))
> +/* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
> +#define RCANFD_CFPCTR(ch, idx)         (0x01d8 + (0x0c * (ch)) + \
> +                                        (0x04 * (idx)))
> +
> +/* RSCFDnCFDFESTS / RSCFDnFESTS */
> +#define RCANFD_FESTS                   (0x0238)
> +/* RSCFDnCFDFFSTS / RSCFDnFFSTS */
> +#define RCANFD_FFSTS                   (0x023c)
> +/* RSCFDnCFDFMSTS / RSCFDnFMSTS */
> +#define RCANFD_FMSTS                   (0x0240)
> +/* RSCFDnCFDRFISTS / RSCFDnRFISTS */
> +#define RCANFD_RFISTS                  (0x0244)
> +/* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */
> +#define RCANFD_CFRISTS                 (0x0248)
> +/* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */
> +#define RCANFD_CFTISTS                 (0x024c)
> +
> +/* RSCFDnCFDTMCp / RSCFDnTMCp */
> +#define RCANFD_TMC(p)                  (0x0250 + (0x01 * (p)))
> +/* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */
> +#define RCANFD_TMSTS(p)                        (0x02d0 + (0x01 * (p)))
> +
> +/* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */
> +#define RCANFD_TMTRSTS(y)              (0x0350 + (0x04 * (y)))
> +/* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */
> +#define RCANFD_TMTARSTS(y)             (0x0360 + (0x04 * (y)))
> +/* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */
> +#define RCANFD_TMTCSTS(y)              (0x0370 + (0x04 * (y)))
> +/* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */
> +#define RCANFD_TMTASTS(y)              (0x0380 + (0x04 * (y)))
> +/* RSCFDnCFDTMIECy / RSCFDnTMIECy */
> +#define RCANFD_TMIEC(y)                        (0x0390 + (0x04 * (y)))
> +
> +/* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */
> +#define RCANFD_TXQCC(m)                        (0x03a0 + (0x04 * (m)))
> +/* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */
> +#define RCANFD_TXQSTS(m)               (0x03c0 + (0x04 * (m)))
> +/* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */
> +#define RCANFD_TXQPCTR(m)              (0x03e0 + (0x04 * (m)))
> +
> +/* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */
> +#define RCANFD_THLCC(m)                        (0x0400 + (0x04 * (m)))
> +/* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */
> +#define RCANFD_THLSTS(m)               (0x0420 + (0x04 * (m)))
> +/* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */
> +#define RCANFD_THLPCTR(m)              (0x0440 + (0x04 * (m)))
> +
> +/* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */
> +#define RCANFD_GTINTSTS0               (0x0460)
> +/* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */
> +#define RCANFD_GTINTSTS1               (0x0464)
> +/* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */
> +#define RCANFD_GTSTCFG                 (0x0468)
> +/* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */
> +#define RCANFD_GTSTCTR                 (0x046c)
> +/* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
> +#define RCANFD_GLOCKK                  (0x047c)
> +/* RSCFDnCFDGRMCFG / RSCFDnGRMCFG */
> +#define RCANFD_GRMCFG                  (0x04fc)
> +
> +/* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
> +#define RCANFD_GAFLID(offset, j)       ((offset) + (0x10 * (j)))
> +/* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
> +#define RCANFD_GAFLM(offset, j)                ((offset) + 0x04 + (0x10 * (j)))
> +/* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
> +#define RCANFD_GAFLP0(offset, j)       ((offset) + 0x08 + (0x10 * (j)))
> +/* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
> +#define RCANFD_GAFLP1(offset, j)       ((offset) + 0x0c + (0x10 * (j)))
> +
> +/* CAN FD mode specific regsiter map */
> +
> +/* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
> +#define RCANFD_F_DCFG(m)               (0x0500 + (0x20 * (m)))
> +#define RCANFD_F_CFDCFG(m)             (0x0504 + (0x20 * (m)))
> +#define RCANFD_F_CFDCTR(m)             (0x0508 + (0x20 * (m)))
> +#define RCANFD_F_CFDSTS(m)             (0x050c + (0x20 * (m)))
> +#define RCANFD_F_CFDCRC(m)             (0x0510 + (0x20 * (m)))
> +
> +/* RSCFDnCFDGAFLXXXj offset */
> +#define RCANFD_F_GAFL_OFFSET           (0x1000)
> +
> +/* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
> +#define RCANFD_F_RMID(q)               (0x2000 + (0x10 * (q)))
> +#define RCANFD_F_RMPTR(q)              (0x2004 + (0x10 * (q)))
> +#define RCANFD_F_RMFDSTS(q)            (0x2008 + (0x10 * (q)))

These should all be "+ (0x20 * (q))".

> +#define RCANFD_F_RMDF(q, b)            (0x200c + (0x04 * (b)) + (0x20 * (q)))
> +
> +/* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
> +#define RCANFD_F_RFOFFSET              (0x3000)
> +#define RCANFD_F_RFID(x)               (RCANFD_F_RFOFFSET + (0x80 * (x)))
> +#define RCANFD_F_RFPTR(x)              (RCANFD_F_RFOFFSET + 0x04 + \
> +                                        (0x80 * (x)))
> +#define RCANFD_F_RFFDSTS(x)            (RCANFD_F_RFOFFSET + 0x08 + \
> +                                        (0x80 * (x)))
> +#define RCANFD_F_RFDF(x, df)           (RCANFD_F_RFOFFSET + 0x0c + \
> +                                        (0x80 * (x)) + (0x04 * (df)))
> +
> +/* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
> +#define RCANFD_F_CFOFFSET              (0x3400)
> +#define RCANFD_F_CFID(ch, idx)         (RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
> +                                        (0x80 * (idx)))
> +#define RCANFD_F_CFPTR(ch, idx)                (RCANFD_F_CFOFFSET + 0x04 + \
> +                                        (0x180 * (ch)) + (0x80 * (idx)))
> +#define RCANFD_F_CFFDCSTS(ch, idx)     (RCANFD_F_CFOFFSET + 0x08 + \
> +                                        (0x180 * (ch)) + (0x80 * (idx)))
> +#define RCANFD_F_CFDF(ch, idx, df)     (RCANFD_F_CFOFFSET + 0x0c + \
> +                                        (0x180 * (ch)) + (0x80 * (idx)) + \
> +                                        (0x04 * (df)))
> +
> +/* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
> +#define RCANFD_F_TMID(p)               (0x4000 + (0x20 * (p)))
> +#define RCANFD_F_TMPTR(p)              (0x4004 + (0x20 * (p)))
> +#define RCANFD_F_TMFDCTR(p)            (0x4008 + (0x20 * (p)))
> +#define RCANFD_F_TMDF(p, b)            (0x400c + (0x20 * (p)) + (0x04 * (b)))
> +
> +/* RSCFDnCFDTHLACCm */
> +#define RCANFD_F_THLACC(m)             (0x6000 + (0x04 * (m)))
> +/* RSCFDnCFDRPGACCr */
> +#define RCANFD_F_RPGACC(r)             (0x6400 + (0x04 * (r)))
[...]

Apart from that, all register addresses, offsets, bit positions and
masks check out. With the two issues fixed:

Reviewed-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>

CU
Uli

RE: [PATCH v6 1/2] can: rcar_canfd: Add Renesas R-Car CAN FD driver

[Ramesh Shanmugasundaram]

Hi Ulrich,

> Thanks for the patch, this is a lot easier to handle.
> 
[...]
> > +#define RCANFD_RFPTR_RFTS(x)           (((x) >> 0) & 0xff)
> 
> That should be "(((x) >> 0) & 0xffff)".
> 
> > +
[...]

> > +/* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
> > +#define RCANFD_F_RMID(q)               (0x2000 + (0x10 * (q)))
> > +#define RCANFD_F_RMPTR(q)              (0x2004 + (0x10 * (q)))
> > +#define RCANFD_F_RMFDSTS(q)            (0x2008 + (0x10 * (q)))
> 
> These should all be "+ (0x20 * (q))".
> 
[...]
> 
> Apart from that, all register addresses, offsets, bit positions and masks
> check out. With the two issues fixed:
> 
> Reviewed-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>

Thank you for your time & review comments. I have fixed these typos and sent out a v7 patch set adding your Reviewed-by tag.

Thanks,
Ramesh