From: Claudiu Manoil <claudiu.manoil@nxp.com>
To: "HEMANT RAMDASI (hramdasi)" <hramdasi@cisco.com>,
"Daniel Walker (danielwa)" <danielwa@cisco.com>
Cc: "David S . Miller" <davem@davemloft.net>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"Sathish Jarugumalli -X (sjarugum - ARICENT TECHNOLOGIES
HOLDINGS LIMITED at Cisco)" <sjarugum@cisco.com>
Subject: RE: [PATCH net] gianfar: Don't force RGMII mode after reset, use defaults
Date: Tue, 12 Nov 2019 17:09:18 +0000 [thread overview]
Message-ID: <VI1PR04MB4880787A714A9E49A436AD2496770@VI1PR04MB4880.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <E84DB6A8-AB7F-428C-8A90-46A7A982D4BF@cisco.com>
>-----Original Message-----
>From: HEMANT RAMDASI (hramdasi) <hramdasi@cisco.com>
>Sent: Tuesday, November 12, 2019 6:56 PM
>To: Daniel Walker (danielwa) <danielwa@cisco.com>; Claudiu Manoil
><claudiu.manoil@nxp.com>
>Cc: David S . Miller <davem@davemloft.net>; netdev@vger.kernel.org;
>Sathish Jarugumalli -X (sjarugum - ARICENT TECHNOLOGIES HOLDINGS
>LIMITED at Cisco) <sjarugum@cisco.com>
>Subject: Re: [PATCH net] gianfar: Don't force RGMII mode after reset, use
>defaults
>
> > Reported-by: Daniel Walker <danielwa@cisco.com>
> > Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
> > ---
> > drivers/net/ethernet/freescale/gianfar.c | 3 ++-
> > drivers/net/ethernet/freescale/gianfar.h | 2 +-
> > 2 files changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/freescale/gianfar.c
>b/drivers/net/ethernet/freescale/gianfar.c
> > index 51ad864..0f4d13d 100644
> > --- a/drivers/net/ethernet/freescale/gianfar.c
> > +++ b/drivers/net/ethernet/freescale/gianfar.c
> > @@ -3173,7 +3173,8 @@ void gfar_mac_reset(struct gfar_private *priv)
> > gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
> >
> > /* Initialize MACCFG2. */
> > - tempval = MACCFG2_INIT_SETTINGS;
> > + tempval = gfar_read(®s->maccfg2);
> > + tempval |= MACCFG2_PAD_CRC;
>
>This is not in sync with PAD/CRC definition of maccfg2 mentioned in p202 rm.
>
I don know what you mean. The definition of this bit is:
" Pad and append CRC . This bit is cleared by default.
This bit must be set when in half-duplex mode (MACCFG2[Full_Duplex] is cleared).
0 Frames presented to the MAC have a valid length and contain a CRC.
1 The MAC pads all transmitted short frames and appends a CRC to every frame regardless of padding
requirement."
So the driver sets this bit to have small frames padded. It always worked this way,
and I retested on P2020RDB and LS1021RDB and works.
Are you saying that padding does not work on your board with the current upstream code?
-Claudiu
next prev parent reply other threads:[~2019-11-12 17:09 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-12 14:55 [PATCH net] gianfar: Don't force RGMII mode after reset, use defaults Claudiu Manoil
2019-11-12 16:47 ` Daniel Walker
2019-11-12 16:55 ` HEMANT RAMDASI (hramdasi)
2019-11-12 17:09 ` Claudiu Manoil [this message]
2019-11-12 17:28 ` HEMANT RAMDASI (hramdasi)
2019-11-13 14:00 ` Claudiu Manoil
2019-11-13 14:21 ` HEMANT RAMDASI (hramdasi)
2019-11-13 16:01 ` Claudiu Manoil
2020-02-19 18:57 ` Daniel Walker (danielwa)
2020-02-20 11:42 ` Claudiu Manoil
2019-11-21 15:58 ` Daniel Walker (danielwa)
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