Re: [PATCH] phy: aquantia: Configure SERDES mode by default

From: Andrew Lunn <andrew@lunn.ch>
To: Vladimir Oltean <olteanv@gmail.com>
Cc: Sean Anderson <sean.anderson@seco.com>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	netdev@vger.kernel.org, Eric Dumazet <edumazet@google.com>,
	Tim Harvey <tharvey@gateworks.com>,
	"David S . Miller" <davem@davemloft.net>,
	linux-kernel@vger.kernel.org, Paolo Abeni <pabeni@redhat.com>,
	Jakub Kicinski <kuba@kernel.org>
Subject: Re: [PATCH] phy: aquantia: Configure SERDES mode by default
Date: Fri, 18 Nov 2022 19:56:58 +0100	[thread overview]
Message-ID: <Y3fVej+tsB8FP2kf@lunn.ch> (raw)
In-Reply-To: <20221118171643.vu6uxbnmog4sna65@skbuf>

> What might be an even bigger offence than giving different provisioning
> to different customers is giving different documentation to different
> customers. In the Aquantia Register Specification for Gen4 PHYs given
> to NXP, the SerDes mode field in register 1E.31C cannot even _take_ the
> value of 6. They're all documented only from 0 to 5. I only learned that
> 6 (XFI/2) was a thing from the discussion between Sean and Tim.

At some point we just have to declare the hardware unsupportable in
mainline, too many landmines. We simply stop any further development
on it. If it works for you, great. Otherwise use the vendor crap
driver and complain loudly to the vendor.

The way out could be Marvell puts firmware in linux-firmware with no
provisioning, or a known provisioning. We load that firmware at probe
time, and we only support that.

But do Marvell actually care about mainline? I guess not.

Microchip seem like the better vendor if you care about mainline.
Open datasheets, engagement with the community, etc.

    Andrew