From: Andrew Lunn <andrew@lunn.ch>
To: "Michal Vokáč" <michal.vokac@ysoft.com>
Cc: Jonathan McDowell <noodles@earth.li>,
Florian Fainelli <f.fainelli@gmail.com>,
David Miller <davem@davemloft.net>,
netdev@vger.kernel.org
Subject: Re: Broken imx6 to QCA8334 connection since PHYLIB to PHYLINK conversion
Date: Mon, 12 Apr 2021 16:14:23 +0200 [thread overview]
Message-ID: <YHRVv/GwCmnRN14j@lunn.ch> (raw)
In-Reply-To: <b7f5842a-c7b7-6439-ae68-51e1690d2507@ysoft.com>
> [1] https://elixir.bootlin.com/linux/v5.12-rc7/source/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi#L101
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-reset-duration = <20>;
phy-supply = <&sw2_reg>;
phy-handle = <ðphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
switch@10 {
compatible = "qca,qca8334";
reg = <10>;
switch_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: port@0 {
reg = <0>;
label = "cpu";
phy-mode = "rgmii-id";
ethernet = <&fec>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
The fec phy-handle = <ðphy0>; is pointing to the PHY of switch port
0. This seems wrong. Does the FEC have a PHY? Do you connect the FEC
and the SWITCH at the RGMII level? Or with two back to back PHYs?
If you are doing it RGMII level, the FEC also needs a fixed-link.
Andrew
next prev parent reply other threads:[~2021-04-12 14:14 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-12 13:28 Broken imx6 to QCA8334 connection since PHYLIB to PHYLINK conversion Michal Vokáč
2021-04-12 14:14 ` Andrew Lunn [this message]
2021-04-13 7:09 ` Michal Vokáč
2021-04-13 12:44 ` Andrew Lunn
2021-04-13 13:26 ` Michal Vokáč
2021-04-13 17:49 ` Ioana Ciornei
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