Re: [PATCH 2/9] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC

[Sergey Shtylyov <s.shtylyov@omp.ru>]

Hello!

On 5/4/22 5:54 PM, Phil Edworthy wrote:

> Document the Ethernet AVB IP found on RZ/V2M SoC.
> It includes the Ethernet controller (E-MAC) and Dedicated Direct memory
> access controller (DMAC) for transferring transmitted Ethernet frames
> to and received Ethernet frames from respective storage areas in the
> URAM at high speed.

   I think nobody knows what exactly URAM stands for... you better call it
just RAM. :-)

> The AVB-DMAC is compliant with IEEE 802.1BA, IEEE 802.1AS timing and
> synchronization protocol, IEEE 802.1Qav real-time transfer, and the
> IEEE 802.1Qat stream reservation protocol.
> 
> R-Car has a pair of combined interrupt lines:
>  ch22 = Line0_DiA | Line1_A | Line2_A
>  ch23 = Line0_DiB | Line1_B | Line2_B
> Line0 for descriptor interrupts.
> Line1 for error related interrupts (which we call err_a and err_b).
> Line2 for management and gPTP related interrupts (mgmt_a and mgmt_b).
> 
> RZ/V2M hardware has separate interrupt lines for each of these, but
> we keep the "ch22" name for Line0_DiA.

   Not sure I agree here...
   BTW, aren't the interrupts called "Ethernet ABV.ch<n>" (as on R-Car gen3)
in your (complete?) manual?

> We also keep the "ch24" name for the Line3 (MAC) interrupt.
> 
> It has 3 clocks; the main AXI clock, the AMBA CHI clock and a gPTP

   Could you spell out CHI like below?

> reference clock.
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
[...]

MBR, Sergey