[PATCH 0/2] mtd: spi-nor: aspeed: introduce a "spi-max-frequency" property

[PATCH 0/2] mtd: spi-nor: aspeed: introduce a "spi-max-frequency" property

[Cédric Le Goater]

Hello,

The property protects some optimistic settings of optimize read algo
on certain chips (old ones). It also makes the read access to the
alternate FMC chip 3 times faster.

Thanks,

C.

Cédric Le Goater (2):
  ARM: dts: aspeed: Add "spi-max-frequency" property
  mtd: spi-nor: aspeed: limit the maximum SPI frequency

 drivers/mtd/spi-nor/aspeed-smc.c                 | 18 ++++++++++++++----
 arch/arm/boot/dts/aspeed-ast2500-evb.dts         |  2 ++
 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts    |  2 ++
 arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts     |  2 ++
 arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts |  3 +++
 arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts       |  2 ++
 arch/arm/boot/dts/aspeed-g4.dtsi                 |  2 ++
 arch/arm/boot/dts/aspeed-g5.dtsi                 |  7 +++++++
 8 files changed, 34 insertions(+), 4 deletions(-)

-- 
2.13.6

[PATCH 1/2] ARM: dts: aspeed: Add "spi-max-frequency" property

[Cédric Le Goater]

Keep the FMC controller chips at a safe 50 MHz rate but use 100 MHz
for the PNOR.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 arch/arm/boot/dts/aspeed-ast2500-evb.dts         | 2 ++
 arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts    | 2 ++
 arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts     | 2 ++
 arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 3 +++
 arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts       | 2 ++
 arch/arm/boot/dts/aspeed-g4.dtsi                 | 2 ++
 arch/arm/boot/dts/aspeed-g5.dtsi                 | 7 +++++++
 7 files changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index c0a7f51e7eb6..6b78e40d3259 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -41,6 +41,7 @@
 		status = "okay";
 		m25p,fast-read;
 		label = "bmc";
+		spi-max-frequency = <50000000>;
 #include "openbmc-flash-layout.dtsi"
 	};
 };
@@ -51,6 +52,7 @@
 		status = "okay";
 		m25p,fast-read;
 		label = "pnor";
+		spi-max-frequency = <100000000>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index 9e2bb8053f74..76098ebc03bf 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -66,6 +66,7 @@
 		status = "okay";
 		m25p,fast-read;
 		label = "bmc";
+		spi-max-frequency = <50000000>;
 #include "openbmc-flash-layout.dtsi"
 	};
 };
@@ -78,6 +79,7 @@
 	flash@0 {
 		status = "okay";
 		m25p,fast-read;
+		spi-max-frequency = <50000000>;
 		label = "pnor";
 	};
 };
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index 0fdf08077ed3..fd909ebfed5b 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -93,6 +93,7 @@
 		status = "okay";
 		m25p,fast-read;
 		label = "bmc";
+		spi-max-frequency = <50000000>;
 #include "openbmc-flash-layout.dtsi"
 
 	};
@@ -107,6 +108,7 @@
 		status = "okay";
 		m25p,fast-read;
 		label = "pnor";
+		spi-max-frequency = <100000000>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
index 214718b7784d..ee7e99bbbc05 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -190,6 +190,7 @@
 		status = "okay";
 		label = "bmc";
 		m25p,fast-read;
+		spi-max-frequency = <50000000>;
 #include "openbmc-flash-layout.dtsi"
 	};
 
@@ -197,6 +198,7 @@
 		status = "okay";
 		label = "alt";
 		m25p,fast-read;
+		spi-max-frequency = <50000000>;
 	};
 };
 
@@ -209,6 +211,7 @@
 		status = "okay";
 		label = "pnor";
 		m25p,fast-read;
+		spi-max-frequency = <100000000>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
index 085926935574..1eae30727fc2 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
@@ -124,6 +124,7 @@
 		status = "okay";
 		label = "bmc";
 		m25p,fast-read;
+		spi-max-frequency = <50000000>;
 #include "openbmc-flash-layout.dtsi"
 	};
 };
@@ -137,6 +138,7 @@
 		status = "okay";
 		label = "pnor";
 		m25p,fast-read;
+		spi-max-frequency = <100000000>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 9354ac92d928..fd14eb1b8c22 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -60,6 +60,7 @@
 			flash@0 {
 				reg = < 0 >;
 				compatible = "jedec,spi-nor";
+				spi-max-frequency = <50000000>;
 				status = "disabled";
 			};
 		};
@@ -75,6 +76,7 @@
 			flash@0 {
 				reg = < 0 >;
 				compatible = "jedec,spi-nor";
+				spi-max-frequency = <50000000>;
 				status = "disabled";
 			};
 		};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index f7c33fbcdaee..f155c32aefbc 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -60,16 +60,19 @@
 			flash@0 {
 				reg = < 0 >;
 				compatible = "jedec,spi-nor";
+				spi-max-frequency = <50000000>;
 				status = "disabled";
 			};
 			flash@1 {
 				reg = < 1 >;
 				compatible = "jedec,spi-nor";
+				spi-max-frequency = <50000000>;
 				status = "disabled";
 			};
 			flash@2 {
 				reg = < 2 >;
 				compatible = "jedec,spi-nor";
+				spi-max-frequency = <50000000>;
 				status = "disabled";
 			};
 		};
@@ -85,11 +88,13 @@
 			flash@0 {
 				reg = < 0 >;
 				compatible = "jedec,spi-nor";
+				spi-max-frequency = <50000000>;
 				status = "disabled";
 			};
 			flash@1 {
 				reg = < 1 >;
 				compatible = "jedec,spi-nor";
+				spi-max-frequency = <50000000>;
 				status = "disabled";
 			};
 		};
@@ -105,11 +110,13 @@
 			flash@0 {
 				reg = < 0 >;
 				compatible = "jedec,spi-nor";
+				spi-max-frequency = <50000000>;
 				status = "disabled";
 			};
 			flash@1 {
 				reg = < 1 >;
 				compatible = "jedec,spi-nor";
+				spi-max-frequency = <50000000>;
 				status = "disabled";
 			};
 		};
-- 
2.13.6

[PATCH 2/2] mtd: spi-nor: aspeed: limit the maximum SPI frequency

[Cédric Le Goater]

The optimize read algo can choose a 100MHz SPI frequency which might
be a bit too high for dual output IO on some chips, for the W25Q256 on
palmetto for instance. The MX66L1G45G on witherspoon should be fine
though. Also, the second chip of the FMC controller does not get any
optimize settings for reads. Only the first is configured by U-Boot.

To fix these two issues, we introduce a "spi-max-frequency" property
in the device tree which will be used to cap the optimize read
algorithm and we run the algo on the FMC controller chips as well.

By default, the frequency setting is 50MHz.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 drivers/mtd/spi-nor/aspeed-smc.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
index a301895d1f06..e4a0123b12b3 100644
--- a/drivers/mtd/spi-nor/aspeed-smc.c
+++ b/drivers/mtd/spi-nor/aspeed-smc.c
@@ -83,6 +83,7 @@ static const struct aspeed_smc_info fmc_2500_info = {
 	.ctl0 = 0x10,
 	.timing = 0x94,
 	.set_4b = aspeed_smc_chip_set_4b,
+	.optimize_read = aspeed_smc_optimize_read,
 };
 
 static const struct aspeed_smc_info spi_2500_info = {
@@ -114,6 +115,7 @@ struct aspeed_smc_chip {
 	u32 ctl_val[smc_max];			/* control settings */
 	enum aspeed_smc_flash_type type;	/* what type of flash */
 	struct spi_nor nor;
+	u32 clk_rate;
 };
 
 struct aspeed_smc_controller {
@@ -130,6 +132,8 @@ struct aspeed_smc_controller {
 	struct aspeed_smc_chip *chips[0];	/* pointers to attached chips */
 };
 
+#define ASPEED_SPI_DEFAULT_FREQ		50000000
+
 /*
  * SPI Flash Configuration Register (AST2500 SPI)
  *     or
@@ -993,11 +997,10 @@ static int aspeed_smc_chip_setup_finish(struct aspeed_smc_chip *chip)
 	dev_info(controller->dev, "read control register: %08x\n",
 		chip->ctl_val[smc_read]);
 
-	/*
-	 * TODO: get max freq from chip
-	 */
+
 	if (optimize_read && info->optimize_read)
-		info->optimize_read(chip, 104000000);
+		info->optimize_read(chip, chip->clk_rate);
+
 	return 0;
 }
 
@@ -1051,6 +1054,13 @@ static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller,
 			break;
 		}
 
+		if (of_property_read_u32(child, "spi-max-frequency",
+					 &chip->clk_rate)) {
+			chip->clk_rate = ASPEED_SPI_DEFAULT_FREQ;
+		}
+		dev_info(dev, "Using %d MHz SPI frequency\n",
+			 chip->clk_rate / 1000000);
+
 		chip->controller = controller;
 		chip->ctl = controller->regs + info->ctl0 + cs * 4;
 		chip->cs = cs;
-- 
2.13.6

Re: [PATCH 0/2] mtd: spi-nor: aspeed: introduce a "spi-max-frequency" property

[Joel Stanley]

Hi Cedric,

On 8 June 2018 at 22:29, Cédric Le Goater <clg@kaod.org> wrote:
> Hello,
>
> The property protects some optimistic settings of optimize read algo
> on certain chips (old ones). It also makes the read access to the
> alternate FMC chip 3 times faster.

The changes look okay to me. Do you plan to submit them for upstream inclusion?

I'd feel happier if we had some review on them before merging device
tree changes.

Cheers,

Joel

>
> Thanks,
>
> C.
>
> Cédric Le Goater (2):
>   ARM: dts: aspeed: Add "spi-max-frequency" property
>   mtd: spi-nor: aspeed: limit the maximum SPI frequency
>
>  drivers/mtd/spi-nor/aspeed-smc.c                 | 18 ++++++++++++++----
>  arch/arm/boot/dts/aspeed-ast2500-evb.dts         |  2 ++
>  arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts    |  2 ++
>  arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts     |  2 ++
>  arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts |  3 +++
>  arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts       |  2 ++
>  arch/arm/boot/dts/aspeed-g4.dtsi                 |  2 ++
>  arch/arm/boot/dts/aspeed-g5.dtsi                 |  7 +++++++
>  8 files changed, 34 insertions(+), 4 deletions(-)
>
> --
> 2.13.6
>

Re: [PATCH 0/2] mtd: spi-nor: aspeed: introduce a "spi-max-frequency" property

[Cédric Le Goater]

On 06/13/2018 05:00 PM, Joel Stanley wrote:
> Hi Cedric,
> 
> On 8 June 2018 at 22:29, Cédric Le Goater <clg@kaod.org> wrote:
>> Hello,
>>
>> The property protects some optimistic settings of optimize read algo
>> on certain chips (old ones). It also makes the read access to the
>> alternate FMC chip 3 times faster.
> 
> The changes look okay to me. Do you plan to submit them for upstream inclusion?

yes. I would like to have some testing first and also make sure
it fits OpenBMC needs.

Thanks,

C.
 
> 
> I'd feel happier if we had some review on them before merging device
> tree changes.
> 
> Cheers,
> 
> Joel
> 
>>
>> Thanks,
>>
>> C.
>>
>> Cédric Le Goater (2):
>>   ARM: dts: aspeed: Add "spi-max-frequency" property
>>   mtd: spi-nor: aspeed: limit the maximum SPI frequency
>>
>>  drivers/mtd/spi-nor/aspeed-smc.c                 | 18 ++++++++++++++----
>>  arch/arm/boot/dts/aspeed-ast2500-evb.dts         |  2 ++
>>  arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts    |  2 ++
>>  arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts     |  2 ++
>>  arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts |  3 +++
>>  arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts       |  2 ++
>>  arch/arm/boot/dts/aspeed-g4.dtsi                 |  2 ++
>>  arch/arm/boot/dts/aspeed-g5.dtsi                 |  7 +++++++
>>  8 files changed, 34 insertions(+), 4 deletions(-)
>>
>> --
>> 2.13.6
>>

Re: [PATCH 0/2] mtd: spi-nor: aspeed: introduce a "spi-max-frequency" property

[Joel Stanley]

On 14 June 2018 at 14:52, Cédric Le Goater <clg@kaod.org> wrote:
> On 06/13/2018 05:00 PM, Joel Stanley wrote:
>> Hi Cedric,
>>
>> On 8 June 2018 at 22:29, Cédric Le Goater <clg@kaod.org> wrote:
>>> Hello,
>>>
>>> The property protects some optimistic settings of optimize read algo
>>> on certain chips (old ones). It also makes the read access to the
>>> alternate FMC chip 3 times faster.
>>
>> The changes look okay to me. Do you plan to submit them for upstream inclusion?
>
> yes. I would like to have some testing first and also make sure
> it fits OpenBMC needs.

Okay.

I suggest we wait until openbmc has moved to the new 4.17 tree
(probably next week), and once we've verified there are no
regressions, we can add your patches in.

Re: [PATCH 0/2] mtd: spi-nor: aspeed: introduce a "spi-max-frequency" property

[Cédric Le Goater]

On 06/14/2018 07:48 AM, Joel Stanley wrote:
> On 14 June 2018 at 14:52, Cédric Le Goater <clg@kaod.org> wrote:
>> On 06/13/2018 05:00 PM, Joel Stanley wrote:
>>> Hi Cedric,
>>>
>>> On 8 June 2018 at 22:29, Cédric Le Goater <clg@kaod.org> wrote:
>>>> Hello,
>>>>
>>>> The property protects some optimistic settings of optimize read algo
>>>> on certain chips (old ones). It also makes the read access to the
>>>> alternate FMC chip 3 times faster.
>>>
>>> The changes look okay to me. Do you plan to submit them for upstream inclusion?
>>
>> yes. I would like to have some testing first and also make sure
>> it fits OpenBMC needs.
> 
> Okay.
> 
> I suggest we wait until openbmc has moved to the new 4.17 tree
> (probably next week), and once we've verified there are no
> regressions, we can add your patches in.
> 

Good. Being on a 4.17 tree would be even better.

Thanks,

C. 

Re: [PATCH 2/2] mtd: spi-nor: aspeed: limit the maximum SPI frequency

[Andrew Jeffery]

On Fri, 8 Jun 2018, at 22:30, Cédric Le Goater wrote:
> The optimize read algo can choose a 100MHz SPI frequency which might
> be a bit too high for dual output IO on some chips, for the W25Q256 on
> palmetto for instance. The MX66L1G45G on witherspoon should be fine
> though. Also, the second chip of the FMC controller does not get any
> optimize settings for reads. Only the first is configured by U-Boot.
> 
> To fix these two issues, we introduce a "spi-max-frequency" property
> in the device tree which will be used to cap the optimize read
> algorithm and we run the algo on the FMC controller chips as well.

Might be a silly question, but why didn't you add support for optimized reads for the AST2400 FMC given we can limit the speed through the devicetree property?

> 
> By default, the frequency setting is 50MHz.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  drivers/mtd/spi-nor/aspeed-smc.c | 18 ++++++++++++++----
>  1 file changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
> index a301895d1f06..e4a0123b12b3 100644
> --- a/drivers/mtd/spi-nor/aspeed-smc.c
> +++ b/drivers/mtd/spi-nor/aspeed-smc.c
> @@ -83,6 +83,7 @@ static const struct aspeed_smc_info fmc_2500_info = {
>  	.ctl0 = 0x10,
>  	.timing = 0x94,
>  	.set_4b = aspeed_smc_chip_set_4b,
> +	.optimize_read = aspeed_smc_optimize_read,

i.e. here you add the support for the 2500 FMC, but the 2400 FMC info struct is unchanged.

>  };
>  
>  static const struct aspeed_smc_info spi_2500_info = {
> @@ -114,6 +115,7 @@ struct aspeed_smc_chip {
>  	u32 ctl_val[smc_max];			/* control settings */
>  	enum aspeed_smc_flash_type type;	/* what type of flash */
>  	struct spi_nor nor;
> +	u32 clk_rate;
>  };
>  
>  struct aspeed_smc_controller {
> @@ -130,6 +132,8 @@ struct aspeed_smc_controller {
>  	struct aspeed_smc_chip *chips[0];	/* pointers to attached chips */
>  };
>  
> +#define ASPEED_SPI_DEFAULT_FREQ		50000000
> +
>  /*
>   * SPI Flash Configuration Register (AST2500 SPI)
>   *     or
> @@ -993,11 +997,10 @@ static int aspeed_smc_chip_setup_finish(struct 
> aspeed_smc_chip *chip)
>  	dev_info(controller->dev, "read control register: %08x\n",
>  		chip->ctl_val[smc_read]);
>  
> -	/*
> -	 * TODO: get max freq from chip
> -	 */
> +
>  	if (optimize_read && info->optimize_read)
> -		info->optimize_read(chip, 104000000);
> +		info->optimize_read(chip, chip->clk_rate);
> +
>  	return 0;
>  }
>  
> @@ -1051,6 +1054,13 @@ static int aspeed_smc_setup_flash(struct 
> aspeed_smc_controller *controller,
>  			break;
>  		}
>  
> +		if (of_property_read_u32(child, "spi-max-frequency",
> +					 &chip->clk_rate)) {
> +			chip->clk_rate = ASPEED_SPI_DEFAULT_FREQ;
> +		}
> +		dev_info(dev, "Using %d MHz SPI frequency\n",
> +			 chip->clk_rate / 1000000);
> +
>  		chip->controller = controller;
>  		chip->ctl = controller->regs + info->ctl0 + cs * 4;
>  		chip->cs = cs;
> -- 
> 2.13.6
> 

Re: [PATCH 2/2] mtd: spi-nor: aspeed: limit the maximum SPI frequency

[Cédric Le Goater]

On 06/18/2018 05:38 AM, Andrew Jeffery wrote:
> On Fri, 8 Jun 2018, at 22:30, Cédric Le Goater wrote:
>> The optimize read algo can choose a 100MHz SPI frequency which might
>> be a bit too high for dual output IO on some chips, for the W25Q256 on
>> palmetto for instance. The MX66L1G45G on witherspoon should be fine
>> though. Also, the second chip of the FMC controller does not get any
>> optimize settings for reads. Only the first is configured by U-Boot.
>>
>> To fix these two issues, we introduce a "spi-max-frequency" property
>> in the device tree which will be used to cap the optimize read
>> algorithm and we run the algo on the FMC controller chips as well.
> 
> Might be a silly question, but why didn't you add support for optimized 
> reads for the AST2400 FMC given we can limit the speed through the 
> devicetree property ? >
>>
>> By default, the frequency setting is 50MHz.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>>  drivers/mtd/spi-nor/aspeed-smc.c | 18 ++++++++++++++----
>>  1 file changed, 14 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
>> index a301895d1f06..e4a0123b12b3 100644
>> --- a/drivers/mtd/spi-nor/aspeed-smc.c
>> +++ b/drivers/mtd/spi-nor/aspeed-smc.c
>> @@ -83,6 +83,7 @@ static const struct aspeed_smc_info fmc_2500_info = {
>>  	.ctl0 = 0x10,
>>  	.timing = 0x94,
>>  	.set_4b = aspeed_smc_chip_set_4b,
>> +	.optimize_read = aspeed_smc_optimize_read,
> 
> i.e. here you add the support for the 2500 FMC, but the 2400 FMC info struct is unchanged.

Ah I understand now your remark. It is missing indeed. I didn't notice 
because I was targeting the alt fmc chip on the witherspoon and too 
high frequencies on the PNOR. I will check how it behaves on the new 
4.17 tree.

Thanks !

C. 
  
> 
>>  };
>>  
>>  static const struct aspeed_smc_info spi_2500_info = {
>> @@ -114,6 +115,7 @@ struct aspeed_smc_chip {
>>  	u32 ctl_val[smc_max];			/* control settings */
>>  	enum aspeed_smc_flash_type type;	/* what type of flash */
>>  	struct spi_nor nor;
>> +	u32 clk_rate;
>>  };
>>  
>>  struct aspeed_smc_controller {
>> @@ -130,6 +132,8 @@ struct aspeed_smc_controller {
>>  	struct aspeed_smc_chip *chips[0];	/* pointers to attached chips */
>>  };
>>  
>> +#define ASPEED_SPI_DEFAULT_FREQ		50000000
>> +
>>  /*
>>   * SPI Flash Configuration Register (AST2500 SPI)
>>   *     or
>> @@ -993,11 +997,10 @@ static int aspeed_smc_chip_setup_finish(struct 
>> aspeed_smc_chip *chip)
>>  	dev_info(controller->dev, "read control register: %08x\n",
>>  		chip->ctl_val[smc_read]);
>>  
>> -	/*
>> -	 * TODO: get max freq from chip
>> -	 */
>> +
>>  	if (optimize_read && info->optimize_read)
>> -		info->optimize_read(chip, 104000000);
>> +		info->optimize_read(chip, chip->clk_rate);
>> +
>>  	return 0;
>>  }
>>  
>> @@ -1051,6 +1054,13 @@ static int aspeed_smc_setup_flash(struct 
>> aspeed_smc_controller *controller,
>>  			break;
>>  		}
>>  
>> +		if (of_property_read_u32(child, "spi-max-frequency",
>> +					 &chip->clk_rate)) {
>> +			chip->clk_rate = ASPEED_SPI_DEFAULT_FREQ;
>> +		}
>> +		dev_info(dev, "Using %d MHz SPI frequency\n",
>> +			 chip->clk_rate / 1000000);
>> +
>>  		chip->controller = controller;
>>  		chip->ctl = controller->regs + info->ctl0 + cs * 4;
>>  		chip->cs = cs;
>> -- 
>> 2.13.6
>>