[PATCH u-boot v2019.04-aspeed-openbmc 0/5] AST2600: Boot from eMMC

[PATCH u-boot v2019.04-aspeed-openbmc 0/5] AST2600: Boot from eMMC

[Eddie James]

This series includes the necessary fixes and features to boot SPL
and U-Boot from the eMMC chip for Tacoma and Rainier systems.

Eddie James (5):
  ARM: Aspeed: AST2600: Support booting from eMMC
  spl: mmc: Switch partition error to debug
  mmc: Add support for devicetree parameters for Aspeed controller
  ARM: dts: Aspeed: Tacoma and Rainier: Add eMMC nodes and parameters
  configs: AST2600 Openbmc: Update config for eMMC boot

 arch/arm/dts/ast2600-rainier.dts            |  8 +++
 arch/arm/dts/ast2600-tacoma.dts             |  8 +++
 arch/arm/include/asm/arch-aspeed/boot0.h    |  2 +-
 arch/arm/mach-aspeed/ast2600/board_common.c | 72 +++++++++++++++++++++
 arch/arm/mach-aspeed/ast2600/spl.c          |  9 +--
 common/spl/spl_mmc.c                        |  4 +-
 configs/ast2600_openbmc_spl_defconfig       |  7 +-
 drivers/mmc/aspeed_sdhci.c                  |  2 +
 drivers/mmc/aspeed_sdhci_ic.c               | 16 +++++
 drivers/mmc/sdhci.c                         |  8 +++
 include/configs/aspeed-common.h             |  3 +
 include/mmc.h                               |  1 +
 include/sdhci.h                             |  6 +-
 13 files changed, 132 insertions(+), 14 deletions(-)
 mode change 100755 => 100644 drivers/mmc/aspeed_sdhci.c

-- 
2.26.2

[PATCH u-boot v2019.04-aspeed-openbmc 1/5] ARM: Aspeed: AST2600: Support booting from eMMC

[Eddie James]

Fix a number of things in the platform code for the AST2600 to
support booting the SPL from eMMC and then loading U-Boot from
eMMC.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
 arch/arm/include/asm/arch-aspeed/boot0.h    |  2 +-
 arch/arm/mach-aspeed/ast2600/board_common.c | 72 +++++++++++++++++++++
 arch/arm/mach-aspeed/ast2600/spl.c          |  9 +--
 include/configs/aspeed-common.h             |  3 +
 4 files changed, 78 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/arch-aspeed/boot0.h b/arch/arm/include/asm/arch-aspeed/boot0.h
index ecd1e927c7..7fd5208773 100644
--- a/arch/arm/include/asm/arch-aspeed/boot0.h
+++ b/arch/arm/include/asm/arch-aspeed/boot0.h
@@ -13,7 +13,7 @@ _start:
 #ifdef CONFIG_SPL_BUILD
 	.word	0x0	/* Key location */
 	.word	0x0	/* start address of image */
-	.word	0X0	/* image size */
+	.word	0Xfc00	/* image size 63KB */
 	.word	0x0	/* signature address */
 	.word	0x0	/* header revision ID low */
 	.word	0x0	/* header revision ID high */
diff --git a/arch/arm/mach-aspeed/ast2600/board_common.c b/arch/arm/mach-aspeed/ast2600/board_common.c
index 449c7d0a23..a6ca8d33f8 100644
--- a/arch/arm/mach-aspeed/ast2600/board_common.c
+++ b/arch/arm/mach-aspeed/ast2600/board_common.c
@@ -8,6 +8,7 @@
 #include <timer.h>
 #include <asm/io.h>
 #include <asm/arch/timer.h>
+#include <linux/bitops.h>
 #include <linux/err.h>
 #include <dm/uclass.h>
 
@@ -110,3 +111,74 @@ int arch_early_init_r(void)
 	return 0;
 }
 
+union ast2600_pll_reg {
+	unsigned int w;
+	struct {
+		unsigned int m : 13;		/* bit[12:0]	*/
+		unsigned int n : 6;		/* bit[18:13]	*/
+		unsigned int p : 4;		/* bit[22:19]	*/
+		unsigned int off : 1;		/* bit[23]	*/
+		unsigned int bypass : 1;	/* bit[24]	*/
+		unsigned int reset : 1;		/* bit[25]	*/
+		unsigned int reserved : 6;	/* bit[31:26]	*/
+	} b;
+};
+
+void aspeed_mmc_init(void)
+{
+	u32 reset_bit;
+	u32 clkstop_bit;
+	u32 clkin = 25000000;
+	u32 pll_reg = 0;
+	u32 enableclk_bit;
+	u32 rate = 0;
+	u32 div = 0;
+	u32 i = 0;
+	u32 mult;
+	u32 clk_sel = readl(0x1e6e2300);
+
+	/* check whether boot from eMMC is enabled */
+	if ((readl(0x1e6e2500) & 0x4) == 0)
+		return;
+
+	/* disable eMMC boot controller engine */
+	*(volatile int *)0x1e6f500C &= ~0x90000000;
+	/* set pinctrl for eMMC */
+	*(volatile int *)0x1e6e2400 |= 0xff000000;
+
+	/* clock setting for eMMC */
+	enableclk_bit = BIT(15);
+
+	reset_bit = BIT(16);
+	clkstop_bit = BIT(27);
+	writel(reset_bit, 0x1e6e2040);
+	udelay(100);
+	writel(clkstop_bit, 0x1e6e2084);
+	mdelay(10);
+	writel(reset_bit, 0x1e6e2044);
+
+	pll_reg = readl(0x1e6e2220);
+	if (pll_reg & BIT(24)) {
+		/* Pass through mode */
+		mult = div = 1;
+	} else {
+		/* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
+		union ast2600_pll_reg reg;
+		reg.w = pll_reg;
+		mult = (reg.b.m + 1) / (reg.b.n + 1);
+		div = (reg.b.p + 1);
+	}
+	rate = ((clkin * mult)/div);
+
+	for(i = 0; i < 8; i++) {
+		div = (i + 1) * 2;
+		if ((rate / div) <= 200000000)
+			break;
+	}
+
+	clk_sel &= ~(0x7 << 12);
+	clk_sel |= (i << 12) | BIT(11);
+	writel(clk_sel, 0x1e6e2300);
+
+	setbits_le32(0x1e6e2300, enableclk_bit);
+}
diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c
index 27796b7385..1a248724ee 100644
--- a/arch/arm/mach-aspeed/ast2600/spl.c
+++ b/arch/arm/mach-aspeed/ast2600/spl.c
@@ -18,6 +18,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define AST_BOOTMODE_UART	2
 
 u32 aspeed_bootmode(void);
+void aspeed_mmc_init(void);
 
 void board_init_f(ulong dummy)
 {
@@ -26,6 +27,7 @@ void board_init_f(ulong dummy)
 	timer_init();
 	preloader_console_init();
 	dram_init();
+	aspeed_mmc_init();
 #endif
 }
 
@@ -68,13 +70,6 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 }
 #endif
 
-#ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(const u32 boot_device)
-{
-	return MMCSD_MODE_RAW;
-}
-#endif
-
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {
diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h
index cdbffc97a2..7901bc2aff 100644
--- a/include/configs/aspeed-common.h
+++ b/include/configs/aspeed-common.h
@@ -11,6 +11,8 @@
 
 #include <asm/arch/platform.h>
 
+#define CONFIG_SUPPORT_EMMC_BOOT
+
 #define CONFIG_BOOTFILE		"all.bin"
 
 #define CONFIG_GATEWAYIP	192.168.0.1
@@ -40,6 +42,7 @@
 
 #define CONFIG_SYS_BOOTMAPSZ		(256 * 1024 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(32 << 20)
+#define CONFIG_SYS_MONITOR_LEN		0xD0000
 
 /*
  * BOOTP options
-- 
2.26.2

[PATCH u-boot v2019.04-aspeed-openbmc 2/5] spl: mmc: Switch partition error to debug

[Eddie James]

The partition error is normal when loading U-Boot from the eMMC
boot partition. This is because the partition is switched first,
and then the SPL attempts to get partition info, but it will read
it from the wrong spot. The raw load will still work after the
error, so make it a debug statement.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
 common/spl/spl_mmc.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 324d91c884..aa0bcea937 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -173,9 +173,7 @@ static int mmc_load_image_raw_partition(struct spl_image_info *spl_image,
 
 	err = part_get_info(mmc_get_blk_desc(mmc), partition, &info);
 	if (err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-		puts("spl: partition error\n");
-#endif
+		debug("spl: partition error\n");
 		return -1;
 	}
 
-- 
2.26.2

[PATCH u-boot v2019.04-aspeed-openbmc 3/5] mmc: Add support for devicetree parameters for Aspeed controller

[Eddie James]

The Aspeed SDHC needs some additional parameters set to function
correctly. These should be encoded in the devicetree.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
 drivers/mmc/aspeed_sdhci.c    |  2 ++
 drivers/mmc/aspeed_sdhci_ic.c | 16 ++++++++++++++++
 drivers/mmc/sdhci.c           |  8 ++++++++
 include/mmc.h                 |  1 +
 include/sdhci.h               |  6 +++++-
 5 files changed, 32 insertions(+), 1 deletion(-)
 mode change 100755 => 100644 drivers/mmc/aspeed_sdhci.c

diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c
old mode 100755
new mode 100644
index f4cdfe039f..36cbf29db5
--- a/drivers/mmc/aspeed_sdhci.c
+++ b/drivers/mmc/aspeed_sdhci.c
@@ -93,6 +93,8 @@ static int aspeed_sdhci_probe(struct udevice *dev)
 	host->mmc = &plat->mmc;
 	if (ret)
 		return ret;
+
+	host->mmc->drv_type = dev_read_u32_default(dev, "sdhci-drive-type", 0);
 	host->mmc->priv = host;
 	host->mmc->dev = dev;
 	upriv->mmc = host->mmc;
diff --git a/drivers/mmc/aspeed_sdhci_ic.c b/drivers/mmc/aspeed_sdhci_ic.c
index fd62ab3eae..b8dd5d52f9 100644
--- a/drivers/mmc/aspeed_sdhci_ic.c
+++ b/drivers/mmc/aspeed_sdhci_ic.c
@@ -9,6 +9,10 @@
 #include <errno.h>
 #include <fdtdec.h>
 #include <asm/io.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+
+#define TIMING_PHASE_OFFSET 0xf4
 
 struct aspeed_sdhci_general_reg {
 	u32 genreal_info;
@@ -32,6 +36,9 @@ static int aspeed_sdhci_irq_probe(struct udevice *dev)
 {
 	struct aspeed_sdhci_general_data *priv = dev_get_priv(dev);
 	int ret = 0;
+	struct resource regs;
+	void __iomem  *sdhci_ctrl_base;
+	u32 timing_phase;
 
 	debug("%s(dev=%p) \n", __func__, dev);
 
@@ -41,6 +48,15 @@ static int aspeed_sdhci_irq_probe(struct udevice *dev)
 		return ret;
 	}
 
+	ret = dev_read_resource(dev, 0, &regs);
+	if (ret < 0)
+		return ret;
+
+	sdhci_ctrl_base = (void __iomem  *)regs.start;
+
+	timing_phase = dev_read_u32_default(dev, "timing-phase", 0);
+	writel(timing_phase, sdhci_ctrl_base + TIMING_PHASE_OFFSET);
+
 	return 0;
 }
 
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index ff506cdf9d..2505d5b8be 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -460,6 +460,7 @@ static int sdhci_set_ios(struct mmc *mmc)
 #endif
 	u32 ctrl;
 	u32 gen_addr, gen_ctrl;
+	u16 ctrl_2;
 	struct sdhci_host *host = mmc->priv;
 
 	if (host->ops && host->ops->set_control_reg)
@@ -518,6 +519,13 @@ static int sdhci_set_ios(struct mmc *mmc)
 
 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 
+	if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)) {
+		ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL_2);
+		ctrl_2 &= ~SDHCI_DRIVER_STRENGTH_MASK;
+		ctrl_2 |= host->mmc->drv_type << SDHCI_DRIVER_STRENGTH_SHIFT;
+		sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL_2);
+	}
+
 	/* If available, call the driver specific "post" set_ios() function */
 	if (host->ops && host->ops->set_ios_post)
 		host->ops->set_ios_post(host);
diff --git a/include/mmc.h b/include/mmc.h
index 1f30f71d25..4834dbaf81 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -639,6 +639,7 @@ struct mmc {
 				  * accessing the boot partitions
 				  */
 	u32 quirks;
+	int drv_type;
 };
 
 struct mmc_hwpart_conf {
diff --git a/include/sdhci.h b/include/sdhci.h
index 14884e4dbb..6f85895480 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -144,7 +144,11 @@
 
 #define SDHCI_ACMD12_ERR	0x3C
 
-/* 3E-3F reserved */
+#define SDHCI_HOST_CONTROL_2        0x3E
+#define SDHCI_DRIVER_STRENGTH_MASK  0x30
+#define SDHCI_DRIVER_STRENGTH_SHIFT 4
+
+/* 3F reserved */
 
 #define SDHCI_CAPABILITIES	0x40
 #define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
-- 
2.26.2

[PATCH u-boot v2019.04-aspeed-openbmc 4/5] ARM: dts: Aspeed: Tacoma and Rainier: Add eMMC nodes and parameters

[Eddie James]

Add the necessary eMMC/SDHC nodes and information to use the eMMC
from SPL and U-Boot.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
 arch/arm/dts/ast2600-rainier.dts | 8 ++++++++
 arch/arm/dts/ast2600-tacoma.dts  | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/dts/ast2600-rainier.dts b/arch/arm/dts/ast2600-rainier.dts
index ce530eb92b..67e177baf1 100644
--- a/arch/arm/dts/ast2600-rainier.dts
+++ b/arch/arm/dts/ast2600-rainier.dts
@@ -18,6 +18,7 @@
 	};
 
 	aliases {
+		mmc0 = &emmc_slot0;
 		spi0 = &fmc;
 		spi1 = &spi1;
 	};
@@ -89,9 +90,16 @@
 	};
 };
 
+&emmc {
+	u-boot,dm-pre-reloc;
+	timing-phase = <0x700ff>;
+};
+
 &emmc_slot0 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 	bus-width = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_emmc_default>;
+	sdhci-drive-type = <1>;
 };
diff --git a/arch/arm/dts/ast2600-tacoma.dts b/arch/arm/dts/ast2600-tacoma.dts
index 22b9f39fa2..85d1e3902b 100644
--- a/arch/arm/dts/ast2600-tacoma.dts
+++ b/arch/arm/dts/ast2600-tacoma.dts
@@ -18,6 +18,7 @@
 	};
 
 	aliases {
+		mmc0 = &emmc_slot0;
 		spi0 = &fmc;
 		spi1 = &spi1;
 	};
@@ -80,9 +81,16 @@
 	};
 };
 
+&emmc {
+	u-boot,dm-pre-reloc;
+	timing-phase = <0x700ff>;
+};
+
 &emmc_slot0 {
+	u-boot,dm-pre-reloc;
 	status = "okay";
 	bus-width = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_emmc_default>;
+	sdhci-drive-type = <1>;
 };
-- 
2.26.2

[PATCH u-boot v2019.04-aspeed-openbmc 5/5] configs: AST2600 Openbmc: Update config for eMMC boot

[Eddie James]

Set some additional parameters to boot eMMC.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
 configs/ast2600_openbmc_spl_defconfig | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/configs/ast2600_openbmc_spl_defconfig b/configs/ast2600_openbmc_spl_defconfig
index c2e3393708..86e3ea289d 100644
--- a/configs/ast2600_openbmc_spl_defconfig
+++ b/configs/ast2600_openbmc_spl_defconfig
@@ -3,9 +3,10 @@ CONFIG_SYS_CONFIG_NAME="evb_ast2600a1_spl"
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_POSITION_INDEPENDENT=y
 CONFIG_SPL_SYS_THUMB_BUILD=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/mach-aspeed/ast2600/u-boot-spl.lds"
 CONFIG_ARCH_ASPEED=y
-CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_SYS_TEXT_BASE=0x8b000000
 CONFIG_ASPEED_AST2600=y
 CONFIG_TARGET_EVB_AST2600A1=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -33,8 +34,9 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=1
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
@@ -80,6 +82,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_DM_GPIO=y
-- 
2.26.2

Re: [PATCH u-boot v2019.04-aspeed-openbmc 3/5] mmc: Add support for devicetree parameters for Aspeed controller

[Joel Stanley]

On Mon, 31 Aug 2020 at 19:01, Eddie James <eajames@linux.ibm.com> wrote:
>
> The Aspeed SDHC needs some additional parameters set to function
> correctly. These should be encoded in the devicetree.
>
> Signed-off-by: Eddie James <eajames@linux.ibm.com>

Does this use the same binding as the kernel patches that Andrew is
going to send upstream?

Can this one go straight to upstream u-boot?

> ---
>  drivers/mmc/aspeed_sdhci.c    |  2 ++
>  drivers/mmc/aspeed_sdhci_ic.c | 16 ++++++++++++++++
>  drivers/mmc/sdhci.c           |  8 ++++++++
>  include/mmc.h                 |  1 +
>  include/sdhci.h               |  6 +++++-
>  5 files changed, 32 insertions(+), 1 deletion(-)
>  mode change 100755 => 100644 drivers/mmc/aspeed_sdhci.c
>
> diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c
> old mode 100755
> new mode 100644
> index f4cdfe039f..36cbf29db5
> --- a/drivers/mmc/aspeed_sdhci.c
> +++ b/drivers/mmc/aspeed_sdhci.c
> @@ -93,6 +93,8 @@ static int aspeed_sdhci_probe(struct udevice *dev)
>         host->mmc = &plat->mmc;
>         if (ret)
>                 return ret;
> +
> +       host->mmc->drv_type = dev_read_u32_default(dev, "sdhci-drive-type", 0);
>         host->mmc->priv = host;
>         host->mmc->dev = dev;
>         upriv->mmc = host->mmc;
> diff --git a/drivers/mmc/aspeed_sdhci_ic.c b/drivers/mmc/aspeed_sdhci_ic.c
> index fd62ab3eae..b8dd5d52f9 100644
> --- a/drivers/mmc/aspeed_sdhci_ic.c
> +++ b/drivers/mmc/aspeed_sdhci_ic.c
> @@ -9,6 +9,10 @@
>  #include <errno.h>
>  #include <fdtdec.h>
>  #include <asm/io.h>
> +#include <linux/io.h>
> +#include <linux/ioport.h>
> +
> +#define TIMING_PHASE_OFFSET 0xf4
>
>  struct aspeed_sdhci_general_reg {
>         u32 genreal_info;
> @@ -32,6 +36,9 @@ static int aspeed_sdhci_irq_probe(struct udevice *dev)
>  {
>         struct aspeed_sdhci_general_data *priv = dev_get_priv(dev);
>         int ret = 0;
> +       struct resource regs;
> +       void __iomem  *sdhci_ctrl_base;
> +       u32 timing_phase;
>
>         debug("%s(dev=%p) \n", __func__, dev);
>
> @@ -41,6 +48,15 @@ static int aspeed_sdhci_irq_probe(struct udevice *dev)
>                 return ret;
>         }
>
> +       ret = dev_read_resource(dev, 0, &regs);
> +       if (ret < 0)
> +               return ret;
> +
> +       sdhci_ctrl_base = (void __iomem  *)regs.start;
> +
> +       timing_phase = dev_read_u32_default(dev, "timing-phase", 0);
> +       writel(timing_phase, sdhci_ctrl_base + TIMING_PHASE_OFFSET);
> +
>         return 0;
>  }
>
> diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
> index ff506cdf9d..2505d5b8be 100644
> --- a/drivers/mmc/sdhci.c
> +++ b/drivers/mmc/sdhci.c
> @@ -460,6 +460,7 @@ static int sdhci_set_ios(struct mmc *mmc)
>  #endif
>         u32 ctrl;
>         u32 gen_addr, gen_ctrl;
> +       u16 ctrl_2;
>         struct sdhci_host *host = mmc->priv;
>
>         if (host->ops && host->ops->set_control_reg)
> @@ -518,6 +519,13 @@ static int sdhci_set_ios(struct mmc *mmc)
>
>         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
>
> +       if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)) {
> +               ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL_2);
> +               ctrl_2 &= ~SDHCI_DRIVER_STRENGTH_MASK;
> +               ctrl_2 |= host->mmc->drv_type << SDHCI_DRIVER_STRENGTH_SHIFT;
> +               sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL_2);
> +       }
> +
>         /* If available, call the driver specific "post" set_ios() function */
>         if (host->ops && host->ops->set_ios_post)
>                 host->ops->set_ios_post(host);
> diff --git a/include/mmc.h b/include/mmc.h
> index 1f30f71d25..4834dbaf81 100644
> --- a/include/mmc.h
> +++ b/include/mmc.h
> @@ -639,6 +639,7 @@ struct mmc {
>                                   * accessing the boot partitions
>                                   */
>         u32 quirks;
> +       int drv_type;
>  };
>
>  struct mmc_hwpart_conf {
> diff --git a/include/sdhci.h b/include/sdhci.h
> index 14884e4dbb..6f85895480 100644
> --- a/include/sdhci.h
> +++ b/include/sdhci.h
> @@ -144,7 +144,11 @@
>
>  #define SDHCI_ACMD12_ERR       0x3C
>
> -/* 3E-3F reserved */
> +#define SDHCI_HOST_CONTROL_2        0x3E
> +#define SDHCI_DRIVER_STRENGTH_MASK  0x30
> +#define SDHCI_DRIVER_STRENGTH_SHIFT 4
> +
> +/* 3F reserved */
>
>  #define SDHCI_CAPABILITIES     0x40
>  #define  SDHCI_TIMEOUT_CLK_MASK        0x0000003F
> --
> 2.26.2
>

Re: [PATCH u-boot v2019.04-aspeed-openbmc 4/5] ARM: dts: Aspeed: Tacoma and Rainier: Add eMMC nodes and parameters

[Joel Stanley]

On Mon, 31 Aug 2020 at 19:01, Eddie James <eajames@linux.ibm.com> wrote:
>
> Add the necessary eMMC/SDHC nodes and information to use the eMMC
> from SPL and U-Boot.

I assume these are the same values we use in the kernel?

>
> Signed-off-by: Eddie James <eajames@linux.ibm.com>
> ---
>  arch/arm/dts/ast2600-rainier.dts | 8 ++++++++
>  arch/arm/dts/ast2600-tacoma.dts  | 8 ++++++++
>  2 files changed, 16 insertions(+)
>
> diff --git a/arch/arm/dts/ast2600-rainier.dts b/arch/arm/dts/ast2600-rainier.dts
> index ce530eb92b..67e177baf1 100644
> --- a/arch/arm/dts/ast2600-rainier.dts
> +++ b/arch/arm/dts/ast2600-rainier.dts
> @@ -18,6 +18,7 @@
>         };
>
>         aliases {
> +               mmc0 = &emmc_slot0;
>                 spi0 = &fmc;
>                 spi1 = &spi1;
>         };
> @@ -89,9 +90,16 @@
>         };
>  };
>
> +&emmc {
> +       u-boot,dm-pre-reloc;
> +       timing-phase = <0x700ff>;
> +};
> +
>  &emmc_slot0 {
> +       u-boot,dm-pre-reloc;
>         status = "okay";
>         bus-width = <4>;
>         pinctrl-names = "default";
>         pinctrl-0 = <&pinctrl_emmc_default>;
> +       sdhci-drive-type = <1>;
>  };
> diff --git a/arch/arm/dts/ast2600-tacoma.dts b/arch/arm/dts/ast2600-tacoma.dts
> index 22b9f39fa2..85d1e3902b 100644
> --- a/arch/arm/dts/ast2600-tacoma.dts
> +++ b/arch/arm/dts/ast2600-tacoma.dts
> @@ -18,6 +18,7 @@
>         };
>
>         aliases {
> +               mmc0 = &emmc_slot0;
>                 spi0 = &fmc;
>                 spi1 = &spi1;
>         };
> @@ -80,9 +81,16 @@
>         };
>  };
>
> +&emmc {
> +       u-boot,dm-pre-reloc;
> +       timing-phase = <0x700ff>;
> +};
> +
>  &emmc_slot0 {
> +       u-boot,dm-pre-reloc;
>         status = "okay";
>         bus-width = <4>;
>         pinctrl-names = "default";
>         pinctrl-0 = <&pinctrl_emmc_default>;
> +       sdhci-drive-type = <1>;
>  };
> --
> 2.26.2
>