* [PATCH] ARM: dts: aspeed: rainier: Add N_MODE_VREF gpio
@ 2021-09-10 13:59 Adriana Kobylak
0 siblings, 0 replies; only message in thread
From: Adriana Kobylak @ 2021-09-10 13:59 UTC (permalink / raw)
To: joel, linux-arm-kernel, linux-aspeed
Cc: spinler, derekh, openbmc, Adriana Kobylak, bjwyman, shawnmm
From: Adriana Kobylak <anoo@us.ibm.com>
The N_MODE_VREF gpio is designed to be used to notify the Onboard Chip
Controller how many power supplies the system should have (2 or 4). This
gpio is on a 9552, populate all the gpios on that chip for completeness.
Signed-off-by: Adriana Kobylak <anoo@us.ibm.com>
---
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 103 +++++++++++++++++++
1 file changed, 103 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
index 6fd3ddf97a21..d5eea86dc260 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
@@ -1502,6 +1502,109 @@ eeprom@51 {
reg = <0x51>;
};
+ pca_pres3: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "",
+ "APSS_RESET_N",
+ "", "", "", "",
+ "P10_DCM0_PRES",
+ "P10_DCM1_PRES",
+ "", "",
+ "N_MODE_CPU_N",
+ "",
+ "PRESENT_VRM_DCM0_N",
+ "PRESENT_VRM_DCM1_N",
+ "N_MODE_VREF",
+ "";
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
pca_pres2: pca9552@61 {
compatible = "nxp,pca9552";
reg = <0x61>;
--
2.25.1
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