From: "Andrew Jeffery" <andrew@aj.id.au>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
openbmc@lists.ozlabs.org, "Cédric Le Goater" <clg@kaod.org>
Subject: Re: [PATCH 0/3] hw: aspeed_gpio: Model new interface for the AST2600
Date: Wed, 09 Feb 2022 21:39:36 +1030 [thread overview]
Message-ID: <6706daf1-f289-41d4-980a-98a5b59b45fe@www.fastmail.com> (raw)
In-Reply-To: <20220207150409.358888-1-andrew@aj.id.au>
On Tue, 8 Feb 2022, at 01:34, Andrew Jeffery wrote:
> Hello,
>
> This series adds support for a new register interface supported by the
> Aspeed GPIO controller, present in at least the AST2600.
>
> The new interface is a single register implementing an indirect command
> protocol that allows us to manipulate up to (at least) 208 GPIOs. This
> makes it possible to write very simple drivers for e.g. u-boot and
> jettison the need for the tedious data model required to deal with the
> old register layout.
>
> I've lightly tested the device consistency under Linux. The Linux
> driver is implemented in terms of the old interface, so data model
> consistency can be tested one way by poking the driver using the
> libgpiod tools and then the other using devmem to drive the new
> interface.
>
> Please review!
Naturally further testing revealed some quirks that require further
enhancements to the modelling.
Hold off on doing anything with this series for the moment.
Cheers,
Andrew
prev parent reply other threads:[~2022-02-09 11:10 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-07 15:04 [PATCH 0/3] hw: aspeed_gpio: Model new interface for the AST2600 Andrew Jeffery
2022-02-07 15:04 ` [PATCH 1/3] hw: aspeed_gpio: Cleanup stray semicolon after switch Andrew Jeffery
2022-02-07 15:04 ` [PATCH 2/3] hw: aspeed_gpio: Split GPIOSet handling from accessors Andrew Jeffery
2022-02-07 15:04 ` [PATCH 3/3] hw: aspeed_gpio: Support the AST2600's indexed register interface Andrew Jeffery
2022-02-09 11:09 ` Andrew Jeffery [this message]
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