dbus-top Design Proposal

dbus-top Design Proposal

[adedeji adebisi]

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Hello,

My name is Adedeji Adebisi and I am working on a top-like tool for dbus.
This tool will show metrics of a dbus connection, in an attempt to
understand some performance related issues.


Currently, we have a mock version of the proposed tool that runs on a PCAP
replay and below is a representation of what we have implemented so far:


+----------------------------------------------------------------------------+

|Message Type          | msg/s        History                 (Total msg/s)
 |

|Method Call             45.00        -  .       .       .       .    -2300
 |

|Method Return           45.00        -  :       :       :       :    -1750
 |

|Signal                  53.00        -  :       :       :       :    -1200
 |

|Error                    0.00        -  :       :       :       :    -650
  |

|Total                  142.99        -:::.....:::.....:::.....:::....-100
  |

+-------------------------------------+--------------------------------------+

| Columns 1-2 of 6      84 sensors    |   Msg/s   Sender  Destination
 |

|   vddq_efgh_out     vddcr_cpu1_in   |   7.50    :1.14   :1.48
 |

|   vddcr_cpu0_out    vddcr_soc1_out  |   7.50    :1.14
org.freedesktop.DB>|

|   vddq_mnop_out     vddq_efgh_in    |   7.50    :1.48   :1.52
 |

|   vddcr_soc0_out    vddq_abcd_in    |   7.50    :1.48
org.freedesktop.DB>|

|   vddq_ijkl_in      vddq_efgh_out   |   1.00    :1.48
xyz.openbmc_projec>|

|   vddcr_soc0_in     hotswap_pout    |   1.00    :1.48
xyz.openbmc_projec>|

|   vddcr_cpu0_in     vddcr_cpu1_in   |   1.00    :1.48
xyz.openbmc_projec>|

|   vddq_ijkl_out     vddq_efgh_in    |   5.00    :1.48
xyz.openbmc_projec>|

|   vddcr_soc1_in     vddq_ijkl_out   |   5.00    :1.48
xyz.openbmc_projec>|

|   hotswap_iout      vddcr_soc0_out  |   1.00    :1.48
xyz.openbmc_projec>|

|   vddq_abcd_in      vddcr_soc1_in   |   7.50    :1.48
xyz.openbmc_projec>|

|   vddq_mnop_in      vddq_mnop_in    |   7.50    :1.52
xyz.openbmc_projec>|

|   vddcr_cpu1_out    vddcr_cpu1_out  |   1.00    :1.70   (null)
  |

|   vddq_abcd_out     vddcr_cpu0_out  |   1.00    :1.70   :1.48
 |

+-------------------------------------+--------------------------------------+

 Fri Jul  2 15:50:08 2021                                    PRESS ? FOR
HELP


The design document for this project that highlights more specifications
can be found in the link below.

https://gerrit.openbmc-project.xyz/c/openbmc/docs/+/44779


Please let me know if you have any questions.

Thank you for your interest in my project,

Adedeji Adebisi.

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