From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@kernel.org>, "H . Peter Anvin" <hpa@zytor.com>,
Andi Kleen <ak@linux.intel.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>,
Markus T Metzger <markus.t.metzger@intel.com>,
Ravi Shankar <ravi.v.shankar@intel.com>,
"Chang S . Bae" <chang.seok.bae@intel.com>,
LKML <linux-kernel@vger.kernel.org>
Subject: [PATCH v4 08/13] x86/fsgsbase/64: Introduce the FIND_PERCPU_BASE macro
Date: Wed, 16 Jan 2019 14:48:44 -0800 [thread overview]
Message-ID: <20190116224849.8617-9-chang.seok.bae@intel.com> (raw)
In-Reply-To: <20190116224849.8617-1-chang.seok.bae@intel.com>
GSBASE is used to find per-CPU data in the kernel. But when it is unknown,
the per-CPU base can be found from the per_cpu_offset table with a CPU NR.
The CPU NR is extracted from the limit field of the CPUNODE entry in GDT,
or by the RDPID instruction.
Also, add the GAS-compatible RDPID macro.
The new macro will be used on a following patch.
Suggested-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
---
arch/x86/include/asm/fsgsbase.h | 38 +++++++++++++++++++++++++++++++++
arch/x86/include/asm/inst.h | 15 +++++++++++++
2 files changed, 53 insertions(+)
diff --git a/arch/x86/include/asm/fsgsbase.h b/arch/x86/include/asm/fsgsbase.h
index 3611bd781088..a67531ebac35 100644
--- a/arch/x86/include/asm/fsgsbase.h
+++ b/arch/x86/include/asm/fsgsbase.h
@@ -110,6 +110,44 @@ extern void x86_gsbase_write_cpu_inactive(unsigned long gsbase);
MODRM 0xd0 wrgsbase_opd 1
.endm
+#if CONFIG_SMP
+
+/*
+ * CPU/node NR is loaded from the limit (size) field of a special segment
+ * descriptor entry in GDT.
+ */
+.macro LOAD_CPU_AND_NODE_SEG_LIMIT reg:req
+ movq $__CPUNODE_SEG, \reg
+ lsl \reg, \reg
+.endm
+
+/*
+ * Fetch the per-CPU GSBASE value for this processor and put it in @reg.
+ * We normally use %gs for accessing per-CPU data, but we are setting up
+ * %gs here and obviously can not use %gs itself to access per-CPU data.
+ */
+.macro FIND_PERCPU_BASE reg:req
+ /*
+ * The CPU/node NR is initialized earlier, directly in cpu_init().
+ * The CPU NR is extracted from it.
+ */
+ ALTERNATIVE \
+ "LOAD_CPU_AND_NODE_SEG_LIMIT \reg", \
+ "RDPID \reg", \
+ X86_FEATURE_RDPID
+ andq $VDSO_CPUNODE_MASK, \reg
+ movq __per_cpu_offset(, \reg, 8), \reg
+.endm
+
+#else
+
+.macro FIND_PERCPU_BASE reg:req
+ /* Tracking the base offset value */
+ movq pcpu_unit_offsets(%rip), \reg
+.endm
+
+#endif /* CONFIG_SMP */
+
#endif /* CONFIG_X86_64 */
#endif /* __ASSEMBLY__ */
diff --git a/arch/x86/include/asm/inst.h b/arch/x86/include/asm/inst.h
index f5a796da07f8..d063841a17e3 100644
--- a/arch/x86/include/asm/inst.h
+++ b/arch/x86/include/asm/inst.h
@@ -306,6 +306,21 @@
.endif
MODRM 0xc0 movq_r64_xmm_opd1 movq_r64_xmm_opd2
.endm
+
+.macro RDPID opd
+ REG_TYPE rdpid_opd_type \opd
+ .if rdpid_opd_type == REG_TYPE_R64
+ R64_NUM rdpid_opd \opd
+ .else
+ R32_NUM rdpid_opd \opd
+ .endif
+ .byte 0xf3
+ .if rdpid_opd > 7
+ PFX_REX rdpid_opd 0
+ .endif
+ .byte 0x0f, 0xc7
+ MODRM 0xc0 rdpid_opd 0x7
+.endm
#endif
#endif
--
2.19.1
next prev parent reply other threads:[~2019-01-16 22:49 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-16 22:48 [PATCH v4 00/13] x86: Enable FSGSBASE instructions Chang S. Bae
2019-01-16 22:48 ` [PATCH v4 01/13] taint: Introduce a new taint flag (insecure) Chang S. Bae
2019-01-16 22:48 ` [PATCH v4 02/13] x86/fsgsbase/64: Add 'unsafe_fsgsbase' to enable CR4.FSGSBASE Chang S. Bae
2019-01-16 22:48 ` [PATCH v4 03/13] kbuild: Raise the minimum required binutils version to 2.21 Chang S. Bae
2019-01-16 22:48 ` [PATCH v4 04/13] x86/fsgsbase/64: Add intrinsics/macros for FSGSBASE instructions Chang S. Bae
2019-01-17 5:09 ` Andi Kleen
2019-01-17 18:04 ` Bae, Chang Seok
2019-01-16 22:48 ` [PATCH v4 05/13] x86/fsgsbase/64: Enable FSGSBASE instructions in the helper functions Chang S. Bae
2019-01-16 22:48 ` [PATCH v4 06/13] x86/fsgsbase/64: Preserve FS/GS state in __switch_to() if FSGSBASE is on Chang S. Bae
2019-01-16 22:48 ` [PATCH v4 07/13] x86/fsgsbase/64: When copying a thread, use the FSGSBASE instructions if available Chang S. Bae
2019-01-16 22:48 ` Chang S. Bae [this message]
2019-01-16 22:48 ` [PATCH v4 09/13] x86/fsgsbase/64: Use the per-CPU base as GSBASE at the paranoid_entry Chang S. Bae
2019-01-16 22:48 ` [PATCH v4 10/13] selftests/x86/fsgsbase: Test WRGSBASE Chang S. Bae
2019-01-16 22:48 ` [PATCH v4 11/13] x86/fsgsbase/64: Enable FSGSBASE by default and add a chicken bit Chang S. Bae
2019-01-16 22:48 ` [PATCH v4 12/13] x86/elf: Enumerate kernel FSGSBASE capability in AT_HWCAP2 Chang S. Bae
2019-01-16 22:48 ` [PATCH v4 13/13] x86/fsgsbase/64: Add documentation for FSGSBASE Chang S. Bae
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