From: Fenghua Yu <fenghua.yu@intel.com>
To: "Thomas Gleixner" <tglx@linutronix.de>,
"Ingo Molnar" <mingo@redhat.com>, "H Peter Anvin" <hpa@zytor.com>,
"Dave Hansen" <dave.hansen@intel.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Ashok Raj" <ashok.raj@intel.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Xiaoyao Li " <xiaoyao.li@intel.com>,
"Michael Chan" <michael.chan@broadcom.com>,
"Ravi V Shankar" <ravi.v.shankar@intel.com>
Cc: "linux-kernel" <linux-kernel@vger.kernel.org>,
"x86" <x86@kernel.org>,
linux-wireless@vger.kernel.org, netdev@vger.kernel.org,
kvm@vger.kernel.org, Fenghua Yu <fenghua.yu@intel.com>
Subject: [PATCH v5 04/18] x86/split_lock: Align x86_capability to unsigned long to avoid split locked access
Date: Tue, 12 Mar 2019 16:00:22 -0700 [thread overview]
Message-ID: <1552431636-31511-5-git-send-email-fenghua.yu@intel.com> (raw)
In-Reply-To: <1552431636-31511-1-git-send-email-fenghua.yu@intel.com>
set_cpu_cap() calls locked BTS and clear_cpu_cap() calls locked BTR to
operate on bitmap defined in x86_capability.
Locked BTS/BTR accesses a single unsigned long location. In 64-bit mode,
the location is at:
base address of x86_capability + (bit offset in x86_capability % 64) * 8
Since base address of x86_capability may not aligned to unsigned long,
the single unsigned long location may cross two cache lines and
accessing the location by locked BTS/BTR introductions will trigger #AC.
To fix the split lock issue, align x86_capability to unsigned long so that
the location will be always within one cache line.
Changing x86_capability[]'s type to unsigned long may also fix the issue
because x86_capability[] will be naturally aligned to unsigned long. But
this needs additional code changes. So we choose the simpler solution
by enforcing alignment using __aligned(unsigned long).
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
arch/x86/include/asm/processor.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 2bb3a648fc12..b92296595fbe 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -93,7 +93,9 @@ struct cpuinfo_x86 {
__u32 extended_cpuid_level;
/* Maximum supported CPUID level, -1=no CPUID: */
int cpuid_level;
- __u32 x86_capability[NCAPINTS + NBUGINTS];
+ /* Unsigned long alignment to avoid split lock in atomic bitmap ops */
+ __u32 x86_capability[NCAPINTS + NBUGINTS]
+ __aligned(sizeof(unsigned long));
char x86_vendor_id[16];
char x86_model_id[64];
/* in KB - valid for CPUS which support this call: */
--
2.19.1
next prev parent reply other threads:[~2019-03-12 23:10 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-12 23:00 [PATCH v5 00/18] x86/split_lock: Enable #AC exception for split locked accesses Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 01/18] x86/common: Align cpu_caps_cleared and cpu_caps_set to unsigned long Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 02/18] drivers/net/b44: Align pwol_mask to unsigned long for better performance Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 03/18] wlcore: simplify/fix/optimize reg_ch_conf_pending operations Fenghua Yu
2019-03-14 13:16 ` Kalle Valo
2019-03-14 23:16 ` Fenghua Yu
2019-03-15 17:17 ` Paolo Bonzini
2019-03-26 7:55 ` Kalle Valo
2019-03-12 23:00 ` Fenghua Yu [this message]
2019-03-12 23:00 ` [PATCH v5 05/18] x86/cpufeatures: Enumerate IA32_CORE_CAPABILITIES MSR Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 06/18] x86/msr-index: Define IA32_CORE_CAPABILITY MSR and #AC exception for split lock bit Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 07/18] x86/split_lock: Enumerate #AC for split lock by MSR IA32_CORE_CAPABILITY Fenghua Yu
2019-03-12 23:52 ` Dave Hansen
2019-03-13 0:56 ` Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 08/18] x86/split_lock: Define MSR TEST_CTL register Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 09/18] x86/split_lock: Handle #AC exception for split lock Fenghua Yu
2019-03-12 23:51 ` Dave Hansen
2019-03-13 0:49 ` Fenghua Yu
2019-03-13 16:22 ` Dave Hansen
2019-03-12 23:00 ` [PATCH v5 10/18] kvm/x86: Emulate MSR IA32_CORE_CAPABILITY Fenghua Yu
2019-03-13 8:15 ` Paolo Bonzini
2019-03-12 23:00 ` [PATCH v5 11/18] kvm/vmx: Emulate MSR TEST_CTL Fenghua Yu
2019-03-13 8:15 ` Paolo Bonzini
2019-03-12 23:00 ` [PATCH v5 12/18] x86/split_lock: Enable #AC for split lock by default Fenghua Yu
2019-03-12 23:43 ` Dave Hansen
2019-03-12 23:00 ` [PATCH v5 13/18] x86/split_lock: Add a sysfs interface to allow user to enable or disable split lock detection on all CPUs during run time Fenghua Yu
2019-03-12 23:48 ` Dave Hansen
2019-03-13 0:53 ` Fenghua Yu
2019-03-13 1:08 ` Dave Hansen
2019-03-12 23:00 ` [PATCH v5 14/18] x86/clearcpuid: Support multiple clearcpuid options Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 15/18] x86/clearcpuid: Support feature flag string in kernel option clearcpuid Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 16/18] x86/clearcpuid: Apply cleared feature bits that are forced set before Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 17/18] x86/clearcpuid: Clear CPUID bit in CPUID faulting Fenghua Yu
2019-03-12 23:00 ` [PATCH v5 18/18] Change document for kernel option clearcpuid Fenghua Yu
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