From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: linux-arm-kernel@lists.infradead.org
Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org,
suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org,
coresight@lists.linaro.org, linux-kernel@vger.kernel.org
Subject: [PATCH v3 04/20] coresight: etm4x: Configure tracers to emit timestamps
Date: Wed, 3 Apr 2019 21:35:25 -0600 [thread overview]
Message-ID: <20190404033541.14072-5-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org>
Configure timestamps to be emitted at regular intervals in the trace
stream to temporally correlate instructions executed on different CPUs.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 101 +++++++++++++++++-
1 file changed, 100 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index d64192c29860..46d337fd8442 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -204,6 +204,90 @@ static void etm4_enable_hw_smp_call(void *info)
arg->rc = etm4_enable_hw(arg->drvdata);
}
+/*
+ * The goal of function etm4_config_timestamp_event() is to configure a
+ * counter that will tell the tracer to emit a timestamp packet when it
+ * reaches zero. This is done in order to get a more fine grained idea
+ * of when instructions are executed so that they can be correlated
+ * with execution on other CPUs.
+ *
+ * To do this the counter itself is configured to self reload and
+ * TRCRSCTLR1 (always true) used to get the counter to decrement. From
+ * there a resource selector is configured with the counter and the
+ * timestamp control register to use the resource selector to trigger the
+ * event that will insert a timestamp packet in the stream.
+ */
+static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
+{
+ int ctridx, ret = -EINVAL;
+ int counter, rselector;
+ u32 val = 0;
+ struct etmv4_config *config = &drvdata->config;
+
+ /* No point in trying if we don't have at least one counter */
+ if (!drvdata->nr_cntr)
+ goto out;
+
+ /* Find a counter that hasn't been initialised */
+ for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
+ if (config->cntr_val[ctridx] == 0)
+ break;
+
+ /* All the counters have been configured already, bail out */
+ if (ctridx == drvdata->nr_cntr) {
+ pr_debug("%s: no available counter found\n", __func__);
+ ret = -ENOSPC;
+ goto out;
+ }
+
+ /*
+ * Searching for an available resource selector to use, starting at
+ * '2' since every implementation has at least 2 resource selector.
+ * ETMIDR4 gives the number of resource selector _pairs_,
+ * hence multiply by 2.
+ */
+ for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
+ if (!config->res_ctrl[rselector])
+ break;
+
+ if (rselector == drvdata->nr_resource * 2) {
+ pr_debug("%s: no available resource selector found\n", __func__);
+ ret = -ENOSPC;
+ goto out;
+ }
+
+ /* Remember what counter we used */
+ counter = 1 << ctridx;
+
+ /*
+ * Initialise original and reload counter value to the smallest
+ * possible value in order to get as much precision as we can.
+ */
+ config->cntr_val[ctridx] = 1;
+ config->cntrldvr[ctridx] = 1;
+
+ /* Set the trace counter control register */
+ val = 0x1 << 16 | /* Bit 16, reload counter automatically */
+ 0x0 << 7 | /* Select single resource selector */
+ 0x1; /* Resource selector 1, i.e always true */
+
+ config->cntr_ctrl[ctridx] = val;
+
+ val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */
+ counter << 0; /* Counter to use */
+
+ config->res_ctrl[rselector] = val;
+
+ val = 0x0 << 7 | /* Select single resource selector */
+ rselector; /* Resource selector */
+
+ config->ts_ctrl = val;
+
+ ret = 0;
+out:
+ return ret;
+}
+
static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
struct perf_event *event)
{
@@ -239,9 +323,24 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
/* TRM: Must program this for cycacc to work */
config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
}
- if (attr->config & BIT(ETM_OPT_TS))
+ if (attr->config & BIT(ETM_OPT_TS)) {
+ /*
+ * Configure timestamps to be emitted at regular intervals in
+ * order to correlate instructions executed on different CPUs
+ * (CPU-wide trace scenarios).
+ */
+ ret = etm4_config_timestamp_event(drvdata);
+
+ /*
+ * No need to go further if timestamp intervals can't
+ * be configured.
+ */
+ if (ret)
+ goto out;
+
/* bit[11], Global timestamp tracing bit */
config->cfg |= BIT(11);
+ }
if (attr->config & BIT(ETM_OPT_CTXTID))
/* bit[6], Context ID tracing bit */
--
2.17.1
next prev parent reply other threads:[~2019-04-04 3:36 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-04 3:35 [PATCH v3 00/20] coresight: Add support for CPU-wide trace scenarios Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 01/20] coresight: pmu: Adding ITRACE property to cs_etm PMU Mathieu Poirier
2019-04-04 8:48 ` Suzuki K Poulose
2019-04-04 3:35 ` [PATCH v3 02/20] coresight: etm4x: Add kernel configuration for CONTEXTID Mathieu Poirier
2019-04-04 8:53 ` Suzuki K Poulose
2019-04-04 3:35 ` [PATCH v3 03/20] coresight: etm4x: Skip selector pair 0 Mathieu Poirier
2019-04-04 8:50 ` Suzuki K Poulose
2019-04-04 3:35 ` Mathieu Poirier [this message]
2019-04-04 4:47 ` [PATCH v3 04/20] coresight: etm4x: Configure tracers to emit timestamps Mike Leach
2019-04-04 3:35 ` [PATCH v3 05/20] coresight: Adding return code to sink::disable() operation Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 06/20] coresight: Move reference counting inside sink drivers Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 07/20] coresight: Properly address errors in sink::disable() functions Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 08/20] coresight: Properly address concurrency in sink::update() functions Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 09/20] coresight: perf: Clean up function etm_setup_aux() Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 10/20] coresight: perf: Refactor function free_event_data() Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 11/20] coresight: Communicate perf event to sink buffer allocation functions Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 12/20] coresight: tmc-etr: Refactor function tmc_etr_setup_perf_buf() Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 13/20] coresight: tmc-etr: Create per-thread buffer allocation function Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 14/20] coresight: tmc-etr: Introduce the notion of process ID to ETR devices Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 15/20] coresight: tmc-etr: Introduce the notion of reference counting " Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 16/20] coresight: tmc-etr: Introduce the notion of IDR " Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 17/20] coresight: tmc-etr: Allocate and free ETR memory buffers for CPU-wide scenarios Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 18/20] coresight: tmc-etr: Add support for CPU-wide trace scenarios Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 19/20] coresight: tmc-etf: " Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 20/20] coresight: etb10: " Mathieu Poirier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190404033541.14072-5-mathieu.poirier@linaro.org \
--to=mathieu.poirier@linaro.org \
--cc=alexander.shishkin@linux.intel.com \
--cc=coresight@lists.linaro.org \
--cc=leo.yan@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mike.leach@arm.com \
--cc=peterz@infradead.org \
--cc=suzuki.poulose@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).