From: Lukasz Luba <l.luba@partner.samsung.com>
To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org
Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org,
cw00.choi@samsung.com, kyungmin.park@samsung.com,
m.szyprowski@samsung.com, s.nawrocki@samsung.com,
myungjoo.ham@samsung.com, keescook@chromium.org,
tony@atomide.com, jroedel@suse.de, treding@nvidia.com,
digetx@gmail.com, willy.mh.wolff.ml@gmail.com,
Lukasz Luba <l.luba@partner.samsung.com>
Subject: [PATCH v7 03/13] clk: samsung: add BPLL rate table for Exynos 5422 SoC
Date: Mon, 6 May 2019 17:11:51 +0200 [thread overview]
Message-ID: <1557155521-30949-4-git-send-email-l.luba@partner.samsung.com> (raw)
In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com>
Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory
Controller frequencies for driver's DRAM timings.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index af62b6d..23c60a5 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1335,6 +1335,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini
PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
};
+static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {
+ PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
+ PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
+ PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
+ PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
+ PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
+ PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
+ PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
+ PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
+};
+
static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
@@ -1477,9 +1488,13 @@ static void __init exynos5x_clk_init(struct device_node *np,
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
- exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
}
+ if (soc == EXYNOS5420)
+ exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ else
+ exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
+
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
reg_base);
samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
--
2.7.4
next prev parent reply other threads:[~2019-05-06 15:13 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20190506151210eucas1p2c0821ddc691b150725b38398295f8d9b@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 0/13] Exynos5 Dynamic Memory Controller driver Lukasz Luba
[not found] ` <CGME20190506151210eucas1p13c2a4b86a6f987ff34fbe1e2d705fbbf@eucas1p1.samsung.com>
2019-05-06 15:11 ` [PATCH v7 01/13] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Lukasz Luba
2019-05-07 7:33 ` Chanwoo Choi
2019-05-07 8:51 ` Lukasz Luba
2019-05-07 9:17 ` Chanwoo Choi
2019-05-07 9:25 ` Lukasz Luba
[not found] ` <CGME20190506151211eucas1p2d96d7eaa4cda8f8d1787d8f1f1461b9b@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 02/13] clk: samsung: add new clocks for DMC for Exynos5422 SoC Lukasz Luba
2019-05-07 7:36 ` Chanwoo Choi
2019-05-07 8:59 ` Lukasz Luba
[not found] ` <CGME20190506151212eucas1p24110f75fa6ed945f9ae7614fbb8aa13d@eucas1p2.samsung.com>
2019-05-06 15:11 ` Lukasz Luba [this message]
2019-05-07 7:36 ` [PATCH v7 03/13] clk: samsung: add BPLL rate table for Exynos 5422 SoC Chanwoo Choi
2019-05-07 9:02 ` Lukasz Luba
[not found] ` <CGME20190506151213eucas1p2ca40029d09ddbbcd11e4a1dd60ae9654@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 04/13] dt-bindings: ddr: rename lpddr2 directory Lukasz Luba
2019-05-07 16:57 ` Rob Herring
2019-05-08 8:31 ` Lukasz Luba
[not found] ` <CGME20190506151214eucas1p17114a7dce506c77ae0bb96b93fd2d838@eucas1p1.samsung.com>
2019-05-06 15:11 ` [PATCH v7 05/13] dt-bindings: ddr: add LPDDR3 memories Lukasz Luba
2019-05-07 17:00 ` Rob Herring
2019-05-08 8:37 ` Lukasz Luba
[not found] ` <CGME20190506151214eucas1p2e87194b1ce66f7184d6770818d02814d@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 06/13] drivers: memory: extend of_memory by LPDDR3 support Lukasz Luba
[not found] ` <CGME20190506151215eucas1p2c57147edac5671c5ec9a223efb6b4adc@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 07/13] dt-bindings: memory-controllers: add Exynos5422 DMC device description Lukasz Luba
2019-05-07 17:04 ` Rob Herring
2019-05-08 7:19 ` Krzysztof Kozlowski
2019-05-08 9:45 ` Lukasz Luba
2019-05-08 10:19 ` Krzysztof Kozlowski
2019-05-08 20:35 ` Rob Herring
2019-05-10 13:12 ` Lukasz Luba
2019-05-08 9:17 ` Lukasz Luba
[not found] ` <CGME20190506151216eucas1p2f0c5ba0920b256789240b87fbb88f3fe@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 08/13] drivers: memory: add DMC driver for Exynos5422 Lukasz Luba
2019-05-08 7:11 ` Krzysztof Kozlowski
2019-05-08 9:32 ` Lukasz Luba
[not found] ` <CGME20190506151217eucas1p2c9348f2766870e7c22c2dabaab5d57a1@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 09/13] drivers: devfreq: events: add Exynos PPMU new events Lukasz Luba
[not found] ` <CGME20190506151218eucas1p1f3bf0b48470595537a893bd0b39e75b7@eucas1p1.samsung.com>
2019-05-06 15:11 ` [PATCH v7 10/13] ARM: dts: exynos: add chipid label and syscon compatible Lukasz Luba
[not found] ` <CGME20190506151219eucas1p2feab00f7b7c1c5fdd5614423fb38eae2@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 11/13] ARM: dts: exynos: add syscon to clock compatible Lukasz Luba
2019-05-08 7:22 ` Krzysztof Kozlowski
2019-05-08 9:50 ` Lukasz Luba
2019-05-08 10:17 ` Krzysztof Kozlowski
2019-05-08 13:13 ` Lukasz Luba
[not found] ` <CGME20190506151219eucas1p2b5c3368873696f51e7d0d3a3e6d6bf1e@eucas1p2.samsung.com>
2019-05-06 15:12 ` [PATCH v7 12/13] ARM: dts: exynos: add DMC device for exynos5422 Lukasz Luba
2019-05-08 7:25 ` Krzysztof Kozlowski
2019-05-08 10:05 ` Lukasz Luba
[not found] ` <CGME20190506151220eucas1p237812f2420594eb651d80cf91076510c@eucas1p2.samsung.com>
2019-05-06 15:12 ` [PATCH v7 13/13] ARM: exynos_defconfig: enable DMC driver Lukasz Luba
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