From: Rahul Tanwar <rahul.tanwar@linux.intel.com>
To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
hpa@zytor.com, tony.luck@intel.com, x86@kernel.org
Cc: andriy.shevchenko@intel.com, alan@linux.intel.com,
ricardo.neri-calderon@linux.intel.com,
rafael.j.wysocki@intel.com, linux-kernel@vger.kernel.org,
qi-ming.wu@intel.com, cheol.yong.kim@intel.com,
rahul.tanwar@intel.com,
Rahul Tanwar <rahul.tanwar@linux.intel.com>
Subject: [PATCH v2 3/3] x86/cpu: Update init data for new Atom CPU model
Date: Fri, 16 Aug 2019 16:18:59 +0800 [thread overview]
Message-ID: <2443a75b6b892a4311e900799e54df5e51b01f9e.1565940653.git.rahul.tanwar@linux.intel.com> (raw)
In-Reply-To: <cover.1565940653.git.rahul.tanwar@linux.intel.com>
In-Reply-To: <cover.1565940653.git.rahul.tanwar@linux.intel.com>
Update vulnerability init data for the newly added CPU model.
Enable setting CPU feature applicable for newly added CPU model.
Add TSC MSR freq_desc entry for newly added CPU model.
Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
---
arch/x86/kernel/cpu/common.c | 1 +
arch/x86/kernel/cpu/intel.c | 1 +
arch/x86/kernel/tsc_msr.c | 5 +++++
3 files changed, 7 insertions(+)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 5cc2d51cc25e..c6b4a578b280 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1059,6 +1059,7 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
VULNWL_INTEL(CORE_YONAH, NO_SSB),
VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
+ VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS),
VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS),
VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF | NO_SWAPGS),
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 66de4b84c369..d618be5ed0e2 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -268,6 +268,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
case INTEL_FAM6_ATOM_SALTWELL_MID:
case INTEL_FAM6_ATOM_SALTWELL_TABLET:
case INTEL_FAM6_ATOM_SILVERMONT_MID:
+ case INTEL_FAM6_ATOM_AIRMONT_NP:
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
break;
default:
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 067858fe4db8..e0cbe4f2af49 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -58,6 +58,10 @@ static const struct freq_desc freq_desc_ann = {
1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 }
};
+static const struct freq_desc freq_desc_lgm = {
+ 1, { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 }
+};
+
static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
INTEL_CPU_FAM6(ATOM_SALTWELL_MID, freq_desc_pnw),
INTEL_CPU_FAM6(ATOM_SALTWELL_TABLET, freq_desc_clv),
@@ -65,6 +69,7 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, freq_desc_tng),
INTEL_CPU_FAM6(ATOM_AIRMONT, freq_desc_cht),
INTEL_CPU_FAM6(ATOM_AIRMONT_MID, freq_desc_ann),
+ INTEL_CPU_FAM6(ATOM_AIRMONT_NP, freq_desc_lgm),
{}
};
--
2.11.0
prev parent reply other threads:[~2019-08-16 8:19 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-16 8:18 [PATCH v2 0/3] x86/cpu: Add new Airmont CPU model Rahul Tanwar
2019-08-16 8:18 ` [PATCH v2 1/3] x86/cpu: Use constant definitions for CPU type Rahul Tanwar
2019-08-17 8:40 ` [tip:x86/cleanups] x86/cpu: Use constant definitions for CPU models tip-bot for Rahul Tanwar
2019-08-16 8:18 ` [PATCH v2 2/3] x86/cpu: Add new Intel Atom CPU model name Rahul Tanwar
2019-08-20 12:22 ` Peter Zijlstra
2019-08-20 12:48 ` Luck, Tony
2019-08-20 13:22 ` Shevchenko, Andriy
2019-08-20 14:20 ` Luck, Tony
2019-08-20 14:57 ` Peter Zijlstra
2019-08-21 3:21 ` Tanwar, Rahul
2019-08-21 9:39 ` Peter Zijlstra
2019-08-21 20:18 ` Luck, Tony
2019-08-21 21:27 ` Thomas Gleixner
2019-08-22 10:29 ` Peter Zijlstra
2019-08-22 18:53 ` Luck, Tony
2019-08-22 20:35 ` [PATCH] x86/cpu: Add new Airmont variant to Intel family Luck, Tony
2019-08-23 9:03 ` Peter Zijlstra
2019-08-23 9:23 ` Tanwar, Rahul
2019-08-20 13:04 ` [PATCH v2 2/3] x86/cpu: Add new Intel Atom CPU model name Thomas Gleixner
2019-08-16 8:18 ` Rahul Tanwar [this message]
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