From: Xiaowei Bao <xiaowei.bao@nxp.com>
To: Zhiqiang.Hou@nxp.com, Minghuan.Lian@nxp.com, mingkai.hu@nxp.com,
bhelgaas@google.com, robh+dt@kernel.org, shawnguo@kernel.org,
leoyang.li@nxp.com, kishon@ti.com, lorenzo.pieralisi@arm.com,
roy.zang@nxp.com, amurray@thegoodpenguin.co.uk,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linuxppc-dev@lists.ozlabs.org
Cc: Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: [PATCH v5 10/11] arm64: dts: layerscape: Add PCIe EP node for ls1088a
Date: Sat, 7 Mar 2020 10:14:29 +0800 [thread overview]
Message-ID: <20200307021430.36826-11-xiaowei.bao@nxp.com> (raw)
In-Reply-To: <20200307021430.36826-1-xiaowei.bao@nxp.com>
Add PCIe EP node for ls1088a to support EP mode.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
---
v2:
- Remove the pf-offset proparty.
v3:
- No change.
v4:
- No change.
v5:
- No change.
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 ++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index ec6013a..cb0805b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -497,6 +497,17 @@
status = "disabled";
};
+ pcie_ep@3400000 {
+ compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x20 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <24>;
+ num-ob-windows = <128>;
+ max-functions = /bits/ 8 <2>;
+ status = "disabled";
+ };
+
pcie@3500000 {
compatible = "fsl,ls1088a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
@@ -522,6 +533,16 @@
status = "disabled";
};
+ pcie_ep@3500000 {
+ compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x28 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ status = "disabled";
+ };
+
pcie@3600000 {
compatible = "fsl,ls1088a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
@@ -547,6 +568,16 @@
status = "disabled";
};
+ pcie_ep@3600000 {
+ compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x00100000
+ 0x30 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ status = "disabled";
+ };
+
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
--
2.9.5
next prev parent reply other threads:[~2020-03-07 2:28 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-07 2:14 [PATCH v4 00/11] Add the multiple PF support for DWC and Layerscape Xiaowei Bao
2020-03-07 2:14 ` [PATCH v5 01/11] PCI: designware-ep: Add multiple PFs support for DWC Xiaowei Bao
2020-03-07 2:14 ` [PATCH v5 02/11] PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode Xiaowei Bao
2020-03-07 2:14 ` [PATCH v5 03/11] PCI: designware-ep: Move the function of getting MSI capability forward Xiaowei Bao
2020-03-07 2:14 ` [PATCH v5 04/11] PCI: designware-ep: Modify MSI and MSIX CAP way of finding Xiaowei Bao
2020-03-07 2:14 ` [PATCH v5 05/11] dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088a Xiaowei Bao
2020-03-07 2:14 ` [PATCH v5 06/11] PCI: layerscape: Fix some format issue of the code Xiaowei Bao
2020-03-07 2:14 ` [PATCH v5 07/11] PCI: layerscape: Modify the way of getting capability with different PEX Xiaowei Bao
2020-03-07 2:14 ` [PATCH v5 08/11] PCI: layerscape: Modify the MSIX to the doorbell mode Xiaowei Bao
2020-03-07 2:14 ` [PATCH v5 09/11] PCI: layerscape: Add EP mode support for ls1088a and ls2088a Xiaowei Bao
2020-03-07 2:14 ` Xiaowei Bao [this message]
2020-03-07 2:14 ` [PATCH v5 11/11] misc: pci_endpoint_test: Add LS1088a in pci_device_id table Xiaowei Bao
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