From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 07/15] coresight: etm4x: Handle TRCVIPCSSCTLR accesses
Date: Fri, 27 Nov 2020 10:52:48 -0700 [thread overview]
Message-ID: <20201127175256.1092685-8-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20201127175256.1092685-1-mathieu.poirier@linaro.org>
From: Suzuki K Poulose <suzuki.poulose@arm.com>
TRCVIPCSSCTLR is not present if the TRCIDR4.NUMPC > 0. Thus we
should only access the register if it is present, preventing
any undesired behavior.
Cc: stable@vger.kernel.org
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 28dd278f6d47..d78a37b6592c 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -141,8 +141,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR);
writel_relaxed(config->vissctlr,
drvdata->base + TRCVISSCTLR);
- writel_relaxed(config->vipcssctlr,
- drvdata->base + TRCVIPCSSCTLR);
+ if (drvdata->nr_pe_cmp)
+ writel_relaxed(config->vipcssctlr,
+ drvdata->base + TRCVIPCSSCTLR);
for (i = 0; i < drvdata->nrseqstate - 1; i++)
writel_relaxed(config->seq_ctrl[i],
drvdata->base + TRCSEQEVRn(i));
@@ -1202,7 +1203,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
state->trcvictlr = readl(drvdata->base + TRCVICTLR);
state->trcviiectlr = readl(drvdata->base + TRCVIIECTLR);
state->trcvissctlr = readl(drvdata->base + TRCVISSCTLR);
- state->trcvipcssctlr = readl(drvdata->base + TRCVIPCSSCTLR);
+ if (drvdata->nr_pe_cmp)
+ state->trcvipcssctlr = readl(drvdata->base + TRCVIPCSSCTLR);
state->trcvdctlr = readl(drvdata->base + TRCVDCTLR);
state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR);
state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR);
@@ -1310,7 +1312,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
writel_relaxed(state->trcvictlr, drvdata->base + TRCVICTLR);
writel_relaxed(state->trcviiectlr, drvdata->base + TRCVIIECTLR);
writel_relaxed(state->trcvissctlr, drvdata->base + TRCVISSCTLR);
- writel_relaxed(state->trcvipcssctlr, drvdata->base + TRCVIPCSSCTLR);
+ if (drvdata->nr_pe_cmp)
+ writel_relaxed(state->trcvipcssctlr, drvdata->base + TRCVIPCSSCTLR);
writel_relaxed(state->trcvdctlr, drvdata->base + TRCVDCTLR);
writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR);
writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR);
--
2.25.1
next prev parent reply other threads:[~2020-11-27 17:53 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-27 17:52 [PATCH 00/15] coresight: Patches for v5.11 Mathieu Poirier
2020-11-27 17:52 ` [PATCH 01/15] coresight: etm4x: Skip setting LPOVERRIDE bit for qcom,skip-power-up Mathieu Poirier
2020-11-27 17:52 ` [PATCH 02/15] coresight: core: Remove unneeded semicolon Mathieu Poirier
2020-11-27 17:52 ` [PATCH 03/15] coresight: etm4x: Fix accesses to TRCVMIDCTLR1 Mathieu Poirier
2020-11-27 17:52 ` [PATCH 04/15] coresight: etm4x: Fix accesses to TRCCIDCTLR1 Mathieu Poirier
2020-11-27 17:52 ` [PATCH 05/15] coresight: etm4x: Update TRCIDR3.NUMPROCS handling to match v4.2 Mathieu Poirier
2020-11-27 17:52 ` [PATCH 06/15] coresight: etm4x: Fix accesses to TRCPROCSELR Mathieu Poirier
2020-11-27 17:52 ` Mathieu Poirier [this message]
2020-11-27 17:52 ` [PATCH 08/15] coresight: Remove unnecessary THIS_MODULE of funnel and replicator driver Mathieu Poirier
2020-11-27 17:52 ` [PATCH 09/15] coresight: tmc-etf: Fix NULL ptr dereference in tmc_enable_etf_sink_perf() Mathieu Poirier
2020-11-27 17:52 ` [PATCH 10/15] coresight: etb10: Fix possible NULL ptr dereference in etb_enable_perf() Mathieu Poirier
2020-11-27 17:52 ` [PATCH 11/15] coresight: tmc-etr: Assign boolean values to a bool variable Mathieu Poirier
2020-11-27 17:52 ` [PATCH 12/15] coresight: tmc-etr: Check if page is valid before dma_map_page() Mathieu Poirier
2020-11-27 17:52 ` [PATCH 13/15] coresight: Fix W=1 warnings in core framework Mathieu Poirier
2020-11-27 17:52 ` [PATCH 14/15] coresight-tpiu: Fix W=1 warning in TPIU driver Mathieu Poirier
2020-11-27 17:52 ` [PATCH 15/15] coresight-stm: Fix W=1 warning in STM driver Mathieu Poirier
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