From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, Lai Jiangshan <laijs@linux.alibaba.com>,
Joerg Roedel <joro@8bytes.org>, Borislav Petkov <bp@suse.de>
Subject: [patch 1/2] x86/cpu: Init exception handling from cpu_init_secondary()
Date: Fri, 07 May 2021 13:02:11 +0200 [thread overview]
Message-ID: <20210507114000.429303187@linutronix.de> (raw)
In-Reply-To: 20210507110210.147106915@linutronix.de
From: Borislav Petkov <bp@suse.de>
SEV-ES guests require properly setup task register with which the TSS
descriptor in the GDT can be located so that the IST-type #VC exception
handler which they need to function properly, can be executed.
This setup needs to happen before attempting to load microcode in
ucode_cpu_init() on secondary CPUs which can cause such #VC exceptions.
Simplify the machinery by running that exception setup from a new function
cpu_init_secondary() and explicitly call cpu_init_exception_handling() for
the boot CPU before cpu_init(). The latter prepares for fixing and
simplifying the exception/IST setup on the boot CPU.
There should be no functional changes resulting from this patch.
[ tglx: Reworked it so cpu_init_exception_handling() stays separate ]
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/include/asm/processor.h | 1 +
arch/x86/kernel/cpu/common.c | 24 +++++++++++-------------
arch/x86/kernel/traps.c | 4 +---
3 files changed, 13 insertions(+), 16 deletions(-)
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -663,6 +663,7 @@ extern void load_direct_gdt(int);
extern void load_fixmap_gdt(int);
extern void load_percpu_segment(int);
extern void cpu_init(void);
+extern void cpu_init_secondary(void);
extern void cpu_init_exception_handling(void);
extern void cr4_init(void);
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1938,13 +1938,12 @@ void cpu_init_exception_handling(void)
/*
* cpu_init() initializes state that is per-CPU. Some data is already
- * initialized (naturally) in the bootstrap process, such as the GDT
- * and IDT. We reload them nevertheless, this function acts as a
- * 'CPU state barrier', nothing should get across.
+ * initialized (naturally) in the bootstrap process, such as the GDT. We
+ * reload it nevertheless, this function acts as a 'CPU state barrier',
+ * nothing should get across.
*/
void cpu_init(void)
{
- struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
struct task_struct *cur = current;
int cpu = raw_smp_processor_id();
@@ -1957,8 +1956,6 @@ void cpu_init(void)
early_cpu_to_node(cpu) != NUMA_NO_NODE)
set_numa_node(early_cpu_to_node(cpu));
#endif
- setup_getcpu(cpu);
-
pr_debug("Initializing CPU#%d\n", cpu);
if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
@@ -1970,7 +1967,6 @@ void cpu_init(void)
* and set up the GDT descriptor:
*/
switch_to_new_gdt(cpu);
- load_current_idt();
if (IS_ENABLED(CONFIG_X86_64)) {
loadsegment(fs, 0);
@@ -1990,12 +1986,6 @@ void cpu_init(void)
initialize_tlbstate_and_flush();
enter_lazy_tlb(&init_mm, cur);
- /* Initialize the TSS. */
- tss_setup_ist(tss);
- tss_setup_io_bitmap(tss);
- set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
-
- load_TR_desc();
/*
* sp0 points to the entry trampoline stack regardless of what task
* is running.
@@ -2017,6 +2007,14 @@ void cpu_init(void)
load_fixmap_gdt(cpu);
}
+#ifdef CONFIG_SMP
+void cpu_init_secondary(void)
+{
+ cpu_init_exception_handling();
+ cpu_init();
+}
+#endif
+
/*
* The microcode loader calls this upon late microcode load to recheck features,
* only when microcode has been updated. Caller holds microcode_mutex and CPU
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -1162,9 +1162,7 @@ void __init trap_init(void)
idt_setup_traps();
- /*
- * Should be a barrier for any external CPU state:
- */
+ cpu_init_exception_handling();
cpu_init();
idt_setup_ist_traps();
next prev parent reply other threads:[~2021-05-07 15:30 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-07 11:02 [patch 0/2] x86/idt: Consolidate IDT/TSS setup Thomas Gleixner
2021-05-07 11:02 ` Thomas Gleixner [this message]
2021-05-08 23:40 ` [patch 1/2] x86/cpu: Init exception handling from cpu_init_secondary() Lai Jiangshan
2021-05-09 13:55 ` Thomas Gleixner
2021-05-10 21:29 ` [patch 1/2 v2] x86/cpu: Init AP " Thomas Gleixner
2021-05-11 9:25 ` Lai Jiangshan
2021-05-12 8:37 ` Peter Zijlstra
2021-05-12 8:49 ` Peter Zijlstra
2021-05-12 9:52 ` Thomas Gleixner
2021-05-18 12:40 ` [tip: x86/apic] x86_cpu_Init_AP_exception_handling_from_cpu_init_secondary_ tip-bot2 for Borislav Petkov
2021-05-18 12:52 ` [tip: x86/apic] x86/cpu: Init AP exception handling from cpu_init_secondary() tip-bot2 for Borislav Petkov
2021-05-07 11:02 ` [patch 2/2] x86/idt: Rework IDT setup for boot CPU Thomas Gleixner
2021-05-18 12:40 ` [tip: x86/apic] " tip-bot2 for Thomas Gleixner
2021-05-18 12:52 ` tip-bot2 for Thomas Gleixner
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