From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, Linus Torvalds <torvalds@linux-foundation.org>,
Andy Lutomirsky <luto@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Dave Hansen <dave.hansen@intel.com>,
Borislav Petkov <bpetkov@suse.de>,
Greg KH <gregkh@linuxfoundation.org>,
keescook@google.com, hughd@google.com,
Brian Gerst <brgerst@gmail.com>,
Josh Poimboeuf <jpoimboe@redhat.com>,
Denys Vlasenko <dvlasenk@redhat.com>,
Rik van Riel <riel@redhat.com>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Juergen Gross <jgross@suse.com>,
David Laight <David.Laight@aculab.com>,
Eduardo Valentin <eduval@amazon.com>,
aliguori@amazon.com, Will Deacon <will.deacon@arm.com>,
daniel.gruss@iaik.tugraz.at,
Dave Hansen <dave.hansen@linux.intel.com>,
Ingo Molnar <mingo@kernel.org>, Borislav Petkov <bp@alien8.de>,
"H. Peter Anvin" <hpa@zytor.com>
Subject: [patch V149 44/50] x86/mm: Use INVPCID for __native_flush_tlb_single()
Date: Sat, 16 Dec 2017 22:24:38 +0100 [thread overview]
Message-ID: <20171216213140.052959404@linutronix.de> (raw)
In-Reply-To: 20171216212354.120930222@linutronix.de
[-- Attachment #1: 0054-x86-mm-Use-INVPCID-for-__native_flush_tlb_single.patch --]
[-- Type: text/plain, Size: 5627 bytes --]
From: Dave Hansen <dave.hansen@linux.intel.com>
This uses INVPCID to shoot down individual lines of the user mapping
instead of marking the entire user map as invalid. This
could/might/possibly be faster.
This for sure needs tlb_single_page_flush_ceiling to be redetermined;
esp. since INVPCID is _slow_.
[ Peterz: Split out from big combo patch ]
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Eduardo Valentin <eduval@amazon.com>
Cc: Greg KH <gregkh@linuxfoundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: aliguori@amazon.com
Cc: daniel.gruss@iaik.tugraz.at
Cc: hughd@google.com
Cc: keescook@google.com
---
arch/x86/include/asm/cpufeatures.h | 1
arch/x86/include/asm/tlbflush.h | 23 ++++++++++++-
arch/x86/mm/init.c | 64 +++++++++++++++++++++----------------
3 files changed, 60 insertions(+), 28 deletions(-)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -197,6 +197,7 @@
#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */
#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */
#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */
+#define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -85,6 +85,18 @@ static inline u16 kern_pcid(u16 asid)
return asid + 1;
}
+/*
+ * The user PCID is just the kernel one, plus the "switch bit".
+ */
+static inline u16 user_pcid(u16 asid)
+{
+ u16 ret = kern_pcid(asid);
+#ifdef CONFIG_PAGE_TABLE_ISOLATION
+ ret |= 1 << X86_CR3_PTI_SWITCH_BIT;
+#endif
+ return ret;
+}
+
struct pgd_t;
static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
{
@@ -338,6 +350,8 @@ static inline void __native_flush_tlb_gl
/*
* Using INVPCID is considerably faster than a pair of writes
* to CR4 sandwiched inside an IRQ flag save/restore.
+ *
+ * Note, this works with CR4.PCIDE=0 or 1.
*/
invpcid_flush_all();
return;
@@ -371,7 +385,14 @@ static inline void __native_flush_tlb_si
if (!static_cpu_has_bug(X86_BUG_CPU_SECURE_MODE_PTI))
return;
- invalidate_user_asid(loaded_mm_asid);
+ /*
+ * Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1.
+ * Just use invalidate_user_asid() in case we are called early.
+ */
+ if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE))
+ invalidate_user_asid(loaded_mm_asid);
+ else
+ invpcid_flush_one(user_pcid(loaded_mm_asid), addr);
}
/*
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -201,34 +201,44 @@ static void __init probe_page_size_mask(
static void setup_pcid(void)
{
-#ifdef CONFIG_X86_64
- if (boot_cpu_has(X86_FEATURE_PCID)) {
- if (boot_cpu_has(X86_FEATURE_PGE)) {
- /*
- * This can't be cr4_set_bits_and_update_boot() --
- * the trampoline code can't handle CR4.PCIDE and
- * it wouldn't do any good anyway. Despite the name,
- * cr4_set_bits_and_update_boot() doesn't actually
- * cause the bits in question to remain set all the
- * way through the secondary boot asm.
- *
- * Instead, we brute-force it and set CR4.PCIDE
- * manually in start_secondary().
- */
- cr4_set_bits(X86_CR4_PCIDE);
- } else {
- /*
- * flush_tlb_all(), as currently implemented, won't
- * work if PCID is on but PGE is not. Since that
- * combination doesn't exist on real hardware, there's
- * no reason to try to fully support it, but it's
- * polite to avoid corrupting data if we're on
- * an improperly configured VM.
- */
- setup_clear_cpu_cap(X86_FEATURE_PCID);
- }
+ if (!IS_ENABLED(CONFIG_X86_64))
+ return;
+
+ if (!boot_cpu_has(X86_FEATURE_PCID))
+ return;
+
+ if (boot_cpu_has(X86_FEATURE_PGE)) {
+ /*
+ * This can't be cr4_set_bits_and_update_boot() -- the
+ * trampoline code can't handle CR4.PCIDE and it wouldn't
+ * do any good anyway. Despite the name,
+ * cr4_set_bits_and_update_boot() doesn't actually cause
+ * the bits in question to remain set all the way through
+ * the secondary boot asm.
+ *
+ * Instead, we brute-force it and set CR4.PCIDE manually in
+ * start_secondary().
+ */
+ cr4_set_bits(X86_CR4_PCIDE);
+
+ /*
+ * INVPCID's single-context modes (2/3) only work if we set
+ * X86_CR4_PCIDE, *and* we INVPCID support. It's unusable
+ * on systems that have X86_CR4_PCIDE clear, or that have
+ * no INVPCID support at all.
+ */
+ if (boot_cpu_has(X86_FEATURE_INVPCID))
+ setup_force_cpu_cap(X86_FEATURE_INVPCID_SINGLE);
+ } else {
+ /*
+ * flush_tlb_all(), as currently implemented, won't work if
+ * PCID is on but PGE is not. Since that combination
+ * doesn't exist on real hardware, there's no reason to try
+ * to fully support it, but it's polite to avoid corrupting
+ * data if we're on an improperly configured VM.
+ */
+ setup_clear_cpu_cap(X86_FEATURE_PCID);
}
-#endif
}
#ifdef CONFIG_X86_32
next prev parent reply other threads:[~2017-12-16 21:40 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-16 21:23 [patch V149 00/50] x86/pti: Updated and reshuffled patch queue Thomas Gleixner
2017-12-16 21:23 ` [patch V149 01/50] x86/mm/dump_pagetables: Check PAGE_PRESENT for real Thomas Gleixner
2017-12-16 21:23 ` [patch V149 02/50] x86/vsyscall/64: Explicitly set _PAGE_USER in the pagetable hierarchy Thomas Gleixner
2017-12-16 21:23 ` [patch V149 03/50] x86/vsyscall/64: Warn and fail vsyscall emulation in NATIVE mode Thomas Gleixner
2017-12-16 21:23 ` [patch V149 04/50] arch: Allow arch_dup_mmap() to fail Thomas Gleixner
2017-12-16 21:23 ` [patch V149 05/50] x86/ldt: Rework locking Thomas Gleixner
2017-12-16 21:24 ` [patch V149 06/50] x86/ldt: Prevent ldt inheritance on exec Thomas Gleixner
2017-12-16 21:24 ` [patch V149 07/50] x86/mm/64: Improve the memory map documentation Thomas Gleixner
2017-12-16 21:24 ` [patch V149 08/50] x86/doc: Remove obvious weirdness Thomas Gleixner
2017-12-16 21:24 ` [patch V149 09/50] x86/entry: Remove SYSENTER_stack naming Thomas Gleixner
2017-12-16 21:24 ` [patch V149 10/50] x86/uv: Use the right tlbflush API Thomas Gleixner
2017-12-16 21:24 ` [patch V149 11/50] x86/microcode: Dont abuse the tlbflush interface Thomas Gleixner
2017-12-16 21:24 ` [patch V149 12/50] x86/mm: Use __flush_tlb_one() for kernel memory Thomas Gleixner
2017-12-16 21:24 ` [patch V149 13/50] x86/mm: Remove superfluous barriers Thomas Gleixner
2017-12-16 21:24 ` [patch V149 14/50] x86/mm: Clarify which functions are supposed to flush what Thomas Gleixner
2017-12-16 21:24 ` [patch V149 15/50] x86/mm: Move the CR3 construction functions to tlbflush.h Thomas Gleixner
2017-12-16 21:24 ` [patch V149 16/50] x86/mm: Remove hard-coded ASID limit checks Thomas Gleixner
2017-12-16 21:24 ` [patch V149 17/50] x86/mm: Put MMU to hardware ASID translation in one place Thomas Gleixner
2017-12-16 21:24 ` [patch V149 18/50] x86/mm: Create asm/invpcid.h Thomas Gleixner
2017-12-16 21:24 ` [patch V149 19/50] x86/cpufeatures: Add X86_BUG_CPU_INSECURE Thomas Gleixner
2017-12-16 21:24 ` [patch V149 20/50] x86/mm/pti: Disable global pages if PAGE_TABLE_ISOLATION=y Thomas Gleixner
2017-12-16 21:24 ` [patch V149 21/50] x86/mm/pti: Prepare the x86/entry assembly code for entry/exit CR3 switching Thomas Gleixner
2017-12-16 21:24 ` [patch V149 22/50] x86/mm/pti: Add infrastructure for page table isolation Thomas Gleixner
2017-12-16 21:24 ` [patch V149 23/50] x86/mm/pti: Add mapping helper functions Thomas Gleixner
2017-12-16 21:24 ` [patch V149 24/50] x86/mm/pti: Allow NX poison to be set in p4d/pgd Thomas Gleixner
2017-12-16 21:24 ` [patch V149 25/50] x86/mm/pti: Allocate a separate user PGD Thomas Gleixner
2017-12-16 21:24 ` [patch V149 26/50] x86/mm/pti: Populate " Thomas Gleixner
2017-12-16 21:24 ` [patch V149 27/50] x86/mm/pti: Add functions to clone kernel PMDs Thomas Gleixner
2017-12-16 21:24 ` [patch V149 28/50] x86/mm/pti: Force entry through trampoline when PTI active Thomas Gleixner
2017-12-16 21:24 ` [patch V149 29/50] x86/fixmap: Move the CPU entry area into a separate PMD Thomas Gleixner
2017-12-16 21:24 ` [patch V149 30/50] x86/mm/pti: Share cpu_entry_area PMDs Thomas Gleixner
2017-12-16 21:24 ` [patch V149 31/50] x86/entry: Align entry text section to PMD boundary Thomas Gleixner
2017-12-16 21:24 ` [patch V149 32/50] x86/mm/pti: Share entry text PMD Thomas Gleixner
2017-12-16 21:24 ` [patch V149 33/50] x86/mm/pti: Map ESPFIX into user space Thomas Gleixner
2017-12-16 21:24 ` [patch V149 34/50] x86/fixmap: Move IDT fixmap into the cpu_entry_area range Thomas Gleixner
2017-12-16 21:24 ` [patch V149 35/50] x86/fixmap: Add debugstore entries to cpu_entry_area Thomas Gleixner
2017-12-16 21:24 ` [patch V149 36/50] x86/events/intel/ds: Map debug buffers in fixmap Thomas Gleixner
2017-12-16 21:24 ` [patch V149 37/50] x86/mm/64: Make a full PGD-entry size hole in the memory map Thomas Gleixner
2017-12-17 11:07 ` Kirill A. Shutemov
2017-12-16 21:24 ` [patch V149 38/50] x86/pti: Put the LDT in its own PGD if PTI is on Thomas Gleixner
2017-12-17 11:09 ` Kirill A. Shutemov
2017-12-16 21:24 ` [patch V149 39/50] x86/pti: Map the vsyscall page if needed Thomas Gleixner
2017-12-16 21:24 ` [patch V149 40/50] x86/mm: Allow flushing for future ASID switches Thomas Gleixner
2017-12-16 21:24 ` [patch V149 41/50] x86/mm: Abstract switching CR3 Thomas Gleixner
2017-12-16 21:24 ` [patch V149 42/50] x86/mm: Use/Fix PCID to optimize user/kernel switches Thomas Gleixner
2017-12-16 21:24 ` [patch V149 43/50] x86/mm: Optimize RESTORE_CR3 Thomas Gleixner
2017-12-16 21:24 ` Thomas Gleixner [this message]
2017-12-16 21:24 ` [patch V149 45/50] x86/mm: Clarify the whole ASID/kernel PCID/user PCID naming Thomas Gleixner
2017-12-16 21:24 ` [patch V149 46/50] x86/mm/pti: Add Kconfig Thomas Gleixner
2017-12-16 21:24 ` [patch V149 47/50] x86/mm/dump_pagetables: Add page table directory Thomas Gleixner
2017-12-16 21:24 ` [patch V149 48/50] x86/mm/dump_pagetables: Check user space page table for WX pages Thomas Gleixner
2017-12-16 21:24 ` [patch V149 49/50] x86/mm/dump_pagetables: Allow dumping current pagetables Thomas Gleixner
2017-12-16 21:24 ` [patch V149 50/50] x86/ldt: Make the LDT mapping RO Thomas Gleixner
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