From: Tim Chen <tim.c.chen@linux.intel.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Andy Lutomirski <luto@kernel.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Greg KH <gregkh@linuxfoundation.org>
Cc: Tim Chen <tim.c.chen@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Andrea Arcangeli <aarcange@redhat.com>,
Andi Kleen <ak@linux.intel.com>,
Arjan Van De Ven <arjan.van.de.ven@intel.com>,
David Woodhouse <dwmw@amazon.co.uk>,
Peter Zijlstra <peterz@infradead.org>,
Dan Williams <dan.j.williams@intel.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Ashok Raj <ashok.raj@intel.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH v3 1/5] x86/feature: Detect the x86 IBRS feature to control Speculation
Date: Tue, 9 Jan 2018 18:26:45 -0800 [thread overview]
Message-ID: <348bd0cc7dd7ac415d2f162fc40d7e0b7236e303.1515542293.git.tim.c.chen@linux.intel.com> (raw)
In-Reply-To: <cover.1515542293.git.tim.c.chen@linux.intel.com>
In-Reply-To: <cover.1515542293.git.tim.c.chen@linux.intel.com>
cpuid ax=0x7, return rdx bit 26 to indicate presence of this feature
IA32_SPEC_CTRL (MSR 0x48)
IA32_SPEC_CTRL, bit0 – Indirect Branch Restricted Speculation (IBRS)
If IBRS is set, near returns and near indirect jumps/calls will not allow
their predicted target address to be controlled by code that executed in
a less privileged prediction mode before the IBRS mode was last written
with a value of 1 or on another logical processor so long as all return
stack buffer (RSB) entries from the previous less privileged prediction
mode are overwritten.
* Thus a near indirect jump/call/return may be affected by code in a
less privileged prediction mode that executed AFTER IBRS mode was last
written with a value of 1.
* Note: IBRS is not required in order to isolate branch predictions for
SMM or SGX enclaves.
* Code executed by a sibling logical processor cannot control indirect
jump/call/return predicted target when IBRS is set.
* SMEP will prevent supervisor mode using RSB entries filled by user code;
this can reduce the need for software to overwrite RSB entries.
CPU performance could be reduced when running with IBRS set.
Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
---
arch/x86/include/asm/cpufeatures.h | 2 ++
arch/x86/include/asm/msr-index.h | 4 ++++
arch/x86/kernel/cpu/scattered.c | 1 +
tools/arch/x86/include/asm/cpufeatures.h | 2 ++
4 files changed, 9 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index f275447..624b58e 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -211,6 +211,8 @@
#define X86_FEATURE_AVX512_4FMAPS ( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */
#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
+#define X86_FEATURE_SPEC_CTRL ( 7*32+19) /* Speculation Control */
+#define X86_FEATURE_SPEC_CTRL_IBRS ( 7*32+20) /* Speculation Control, use IBRS */
/* Virtualization flags: Linux defined, word 8 */
#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index fa11fb1..3e1cb18 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -42,6 +42,10 @@
#define MSR_PPIN_CTL 0x0000004e
#define MSR_PPIN 0x0000004f
+#define MSR_IA32_SPEC_CTRL 0x00000048
+#define SPEC_CTRL_DISABLE_IBRS (0 << 0)
+#define SPEC_CTRL_ENABLE_IBRS (1 << 0)
+
#define MSR_IA32_PERFCTR0 0x000000c1
#define MSR_IA32_PERFCTR1 0x000000c2
#define MSR_FSB_FREQ 0x000000cd
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 05459ad..bc50c40 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -24,6 +24,7 @@ static const struct cpuid_bit cpuid_bits[] = {
{ X86_FEATURE_INTEL_PT, CPUID_EBX, 25, 0x00000007, 0 },
{ X86_FEATURE_AVX512_4VNNIW, CPUID_EDX, 2, 0x00000007, 0 },
{ X86_FEATURE_AVX512_4FMAPS, CPUID_EDX, 3, 0x00000007, 0 },
+ { X86_FEATURE_SPEC_CTRL, CPUID_EDX, 26, 0x00000007, 0 },
{ X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 },
{ X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 },
{ X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 },
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 793690f..995d74b 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -205,6 +205,8 @@
#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */
#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
+#define X86_FEATURE_SPEC_CTRL ( 7*32+19) /* Speculation Control */
+#define X86_FEATURE_SPEC_CTRL_IBRS ( 7*32+20) /* Speculation Control, use IBRS */
/* Virtualization flags: Linux defined, word 8 */
#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
--
2.9.4
next prev parent reply other threads:[~2018-01-10 2:48 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-10 2:26 [PATCH v3 0/5] IBRS patch series Tim Chen
2018-01-10 2:26 ` Tim Chen [this message]
2018-01-10 2:26 ` [PATCH v3 2/5] x86/enter: Create macros to set/clear IBRS Tim Chen
2018-01-11 16:04 ` Thomas Gleixner
2018-01-11 21:05 ` Tim Chen
2018-01-11 21:24 ` Tim Chen
2018-01-10 2:26 ` [PATCH v3 3/5] x86/enter: Use IBRS on syscall and interrupts Tim Chen
2018-01-10 10:04 ` Peter Zijlstra
2018-01-10 11:27 ` Paolo Bonzini
2018-01-10 18:16 ` Tim Chen
2018-01-10 18:28 ` Peter Zijlstra
2018-01-10 18:44 ` Tim Chen
2018-01-10 18:47 ` Van De Ven, Arjan
2018-01-11 12:45 ` Woodhouse, David
2018-01-10 2:26 ` [PATCH v3 4/5] x86/ibrs: Create boot option for IBRS Tim Chen
2018-01-10 2:26 ` [PATCH v3 5/5] x86/idle: Disable IBRS entering idle and enable it on wakeup Tim Chen
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