[PATCH 00/10] memorder: Trivial fixups

[PATCH 00/10] memorder: Trivial fixups

[SeongJae Park]

From: SeongJae Park <sj38.park@gmail.com>

This patchset contains trivial fixups memorderdebugging/, which found
while doing Korean translation[1].

[1] https://github.com/sjp38/perfbook-ko_KR

SeongJae Park (10):
  memorder: Fix typos: s/,/./
  memorder/memorder: Add a missing space between column name and
    'column'
  memorder: Add missing unbreakable spaces between 'values', 'and', and
    numbers
  memorder: Remove an empty fcvref block
  memorder: Remove braces for single line if-else blocks
  memorder: Consistently use \co{} instead of {\tt } for code
  memorder: Consistently use '\co{}' for 'herd'
  memorder: Remove a redundant sentence for memory barrier strength
  memorder: Make clear the scope of READ_ONCE()/WRITE_ONCE() heavy uses
  memorder: Fix wrong primitive names in a quick quizz

 memorder/memorder.tex | 72 ++++++++++++++++++++-----------------------
 1 file changed, 33 insertions(+), 39 deletions(-)

-- 
2.17.1

[PATCH 01/10] memorder: Fix typos: s/,/./

[SeongJae Park]

From: SeongJae Park <sj38.park@gmail.com>

Two sentences in memorder.tex are having commas instead of ending
periods.  Fix those.

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index 1c882ea4..75e336dc 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -4103,7 +4103,7 @@ The following list of rules summarizes the lessons of this section:
 
 \item	If both legs of the \qco{if} statement begin with identical stores
 	to the same variable, then the control dependency will not order
-	those stores,
+	those stores.
 	If ordering is needed, precede both of them with \co{smp_mb()} or
 	use \co{smp_store_release()}.
 	Please note that it is \emph{not} sufficient to use \co{barrier()}
@@ -4763,7 +4763,7 @@ Perhaps surprisingly, despite the empty critical section, RCU nevertheless
 still manages to forbid the cycle.
 This can again be checked using the \co{herd} tool.
 Furthermore, the reasoning is once again similar to that for
-\cref{lst:memorder:What Happens Before RCU Readers?},
+\cref{lst:memorder:What Happens Before RCU Readers?}.
 Recapping, if \co{P1()}'s \co{WRITE_ONCE()} follows the end of a given
 grace period, then \co{P1()}'s RCU read-side critical section---and
 everything following it---must follow the beginning of that same grace
-- 
2.17.1

[PATCH 02/10] memorder/memorder: Add a missing space between column name and 'column'

[SeongJae Park]

From: SeongJae Park <sj38.park@gmail.com>

A sentence in memorder.tex is missing a space between the column name
and 'column'.  Add it.

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index 75e336dc..ba921ad8 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -1148,7 +1148,7 @@ are at most two threads involved.
 
 	The \co{WRITE_ONCE()} row captures the fact that accesses to
 	a single variable are always fully ordered, as indicated by
-	the ``SV''column.
+	the ``SV'' column.
 	Note that all other operations providing ordering against accesses
 	to multiple variables also provide this same-variable ordering.
 
-- 
2.17.1

[PATCH 03/10] memorder: Add missing unbreakable spaces between 'values', 'and', and numbers

[SeongJae Park]

From: SeongJae Park <sj38.park@gmail.com>

A sentence in memorder.tex is missing unbreakable spaces.  Add those.

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index ba921ad8..38ff3a55 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -2227,8 +2227,8 @@ situation arises.
 	But in
 	\cref{lst:memorder:Cache-Coherent IRIW Litmus Test},
 	wouldn't be just as bad if \co{P2()}'s \co{r1} and \co{r2}
-	obtained the values 2 and 1, respectively, while \co{P3()}'s
-	\co{r3} and \co{r4} obtained the values 1 and 2, respectively?
+	obtained the values~2 and~1, respectively, while \co{P3()}'s
+	\co{r3} and \co{r4} obtained the values~1 and~2, respectively?
 }\QuickQuizAnswer{
 	Yes, it would.
 	Feel free to modify the \co{exists} clause to
-- 
2.17.1

[PATCH 04/10] memorder: Remove an empty fcvref block

[SeongJae Park]

From: SeongJae Park <sj38.park@gmail.com>

memorder.tex is unnecessarily having one empty fcvref block.  Remove it.

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 2 --
 1 file changed, 2 deletions(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index 38ff3a55..5ad7e796 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -5431,8 +5431,6 @@ in v5.9 of the Linux kernel in favor of augmenting Alpha's definition
 of \co{READ_ONCE()}.
 Thus, as of v5.9, core kernel code no longer needs to concern itself
 with this aspect of DEC Alpha.
-\begin{fcvref}[ln:memorder:Insert and Lock-Free Search (No Ordering)]
-\end{fcvref}
 \begin{fcvref}[ln:memorder:Safe Insert and Lock-Free Search]
 However, it is better to use \co{rcu_dereference()}
 as shown on \clnref{deref1,deref2} of
-- 
2.17.1

[PATCH 05/10] memorder: Remove braces for single line if-else blocks

[SeongJae Park]

From: SeongJae Park <sj38.park@gmail.com>

Code snippets in memorder.tex usually don't use braces for signle-line
if blocks, like Linux kernel coding style.  However, some code snippets
use braces.  Don't use the braces to be consistent.

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index 5ad7e796..b5887764 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -3896,11 +3896,10 @@ optimization levels:
 q = READ_ONCE(x);
 barrier();
 WRITE_ONCE(y, 1);  /* BUG: No ordering!!! */
-if (q) {
+if (q)
 	do_something();
-} else {
+else
 	do_something_else();
-}
 \end{VerbatimN}
 
 Now there is no conditional between the load from~\co{x} and the store
@@ -4005,11 +4004,10 @@ not necessarily apply to code following the if-statement:
 
 \begin{VerbatimN}
 q = READ_ONCE(x);
-if (q) {
+if (q)
 	WRITE_ONCE(y, 1);
-} else {
+else
 	WRITE_ONCE(y, 2);
-}
 WRITE_ONCE(z, 1);  /* BUG: No ordering. */
 \end{VerbatimN}
 
-- 
2.17.1

[PATCH 06/10] memorder: Consistently use \co{} instead of {\tt } for code

[SeongJae Park]

From: SeongJae Park <sj38.park@gmail.com>

Some sentences in memorder.tex are using {\tt } for some code, while
others use \co{}.  Consistently use \co{}.

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 42 +++++++++++++++++++++---------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index b5887764..b7699129 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -5265,7 +5265,7 @@ of reordering memory optimizations across the barriers.
 }\QuickQuizEnd
 
 These primitives generate code only in SMP kernels, however, several
-have UP versions ({\tt mb()}, {\tt rmb()}, and {\tt wmb()},
+have UP versions (\co{mb()}, \co{rmb()}, and \co{wmb()},
 respectively) that generate a memory barrier even in UP kernels.
 The \co{smp_} versions should be used in most cases.
 However, these latter primitives are useful when writing drivers,
@@ -5486,8 +5486,8 @@ struct el *search(long searchkey)
 \end{listing}
 
 The Linux memory-barrier primitives took their names from the Alpha
-instructions, so \co{smp_mb()} is {\tt mb}, \co{smp_rmb()} is {\tt rmb},
-and \co{smp_wmb()} is {\tt wmb}.
+instructions, so \co{smp_mb()} is \co{mb}, \co{smp_rmb()} is \co{rmb},
+and \co{smp_wmb()} is \co{wmb}.
 Alpha is the only CPU whose \co{READ_ONCE()} includes an \co{smp_mb()}.
 
 \QuickQuizSeries{%
@@ -5657,17 +5657,17 @@ Itanium offers a \IXh{weak}{consistency}
 model, so that in absence of explicit
 memory-barrier instructions or dependencies, Itanium is within its rights
 to arbitrarily reorder memory references~\cite{IntelItanium02v2}.
-Itanium has a memory-fence instruction named {\tt mf}, but also has
+Itanium has a memory-fence instruction named \co{mf}, but also has
 ``half-memory fence'' modifiers to loads, stores, and to some of its atomic
 instructions~\cite{IntelItanium02v3}.
-The {\tt acq} modifier prevents subsequent memory-reference instructions
-from being reordered before the {\tt acq}, but permits
-prior memory-reference instructions to be reordered after the {\tt acq},
+The \co{acq} modifier prevents subsequent memory-reference instructions
+from being reordered before the \co{acq}, but permits
+prior memory-reference instructions to be reordered after the \co{acq},
 similar to the \ARMv8 load-acquire instructions.
-Similarly, the {\tt rel} modifier prevents prior memory-reference
-instructions from being reordered after the {\tt rel}, but allows
+Similarly, the \co{rel} modifier prevents prior memory-reference
+instructions from being reordered after the \co{rel}, but allows
 subsequent memory-reference instructions to be reordered before
-the {\tt rel}.
+the \co{rel}.
 
 These half-memory fences are useful for critical sections, since
 it is safe to push operations into a critical section, but can be
@@ -5796,7 +5796,7 @@ void synchronize_rcu(void)
 \end{fcvref}
 }\QuickQuizEnd
 
-The Itanium {\tt mf} instruction is used for the \co{smp_rmb()},
+The Itanium \co{mf} instruction is used for the \co{smp_rmb()},
 \co{smp_mb()}, and \co{smp_wmb()} primitives in the Linux kernel.
 Despite persistent rumors to the contrary, the \qco{mf} mnemonic stands
 for ``memory fence''.
@@ -5887,7 +5887,7 @@ instructions~\cite{PowerPC94,MichaelLyons05a}:
 	loads.
 	The \co{lwsync} instruction may be used to implement
 	load-acquire and store-release operations.
-	Interestingly enough, the {\tt lwsync} instruction enforces
+	Interestingly enough, the \co{lwsync} instruction enforces
 	the same within-CPU ordering as does x86, z~Systems, and coincidentally,
 	SPARC TSO\@.
 	However, placing the \co{lwsync} instruction between each
@@ -5903,7 +5903,7 @@ instructions~\cite{PowerPC94,MichaelLyons05a}:
 	were wondering) causes all preceding cacheable stores to appear
 	to have completed before all subsequent stores.
 	However, stores to cacheable memory are ordered separately from
-	stores to non-cacheable memory, which means that {\tt eieio}
+	stores to non-cacheable memory, which means that \co{eieio}
 	will not force an MMIO store to precede a spinlock release.
 	This instruction may well be unique in having a five-vowel mnemonic.
 \item	[\tco{isync}] forces all preceding instructions to appear to have
@@ -5964,7 +5964,7 @@ Thankfully, few people write self-modifying code these days, but JITs
 and compilers do it all the time.
 Furthermore, recompiling a recently run program looks just like
 self-modifying code from the CPU's viewpoint.
-The {\tt icbi} instruction (instruction cache block invalidate)
+The \co{icbi} instruction (instruction cache block invalidate)
 invalidates a specified cache line from
 the instruction cache, and may be used in these situations.
 
@@ -6018,12 +6018,12 @@ However, the heavier-weight \qco{membar #MemIssue} must be used when
 a write to a given MMIO register affects the value that will next be
 read from {\em some other} MMIO register.
 
-SPARC requires a {\tt flush} instruction be used between the time that
+SPARC requires a \co{flush} instruction be used between the time that
 the instruction stream is modified and the time that any of these
 instructions are executed~\cite{SPARC94}.
 This is needed to flush any prior value for that location from
 the SPARC's instruction cache.
-Note that {\tt flush} takes an address, and will flush only that address
+Note that \co{flush} takes an address, and will flush only that address
 from the instruction cache.
 On SMP systems, all CPUs' caches are flushed, but there is no
 convenient way to determine when the off-CPU flushes complete,
@@ -6044,7 +6044,7 @@ primitive to be a no-op for the CPU~\cite{IntelXeonV3-96a}.
 Of course, a compiler directive was also required to prevent optimizations
 that would reorder across the \co{smp_wmb()} primitive.
 In ancient times, certain x86 CPUs gave no ordering guarantees for loads, so
-the \co{smp_mb()} and \co{smp_rmb()} primitives expanded to {\tt lock;addl}.
+the \co{smp_mb()} and \co{smp_rmb()} primitives expanded to \co{lock;addl}.
 This atomic instruction acts as a barrier to both loads and stores.
 
 But those were ancient times.
@@ -6074,14 +6074,14 @@ For example, if you write a program where one CPU atomically increments
 a byte while another CPU executes a 4-byte atomic increment on
 that same location, you are on your own.
 
-Some SSE instructions are weakly ordered ({\tt clflush}
+Some SSE instructions are weakly ordered (\co{clflush}
 and non-temporal move instructions~\cite{IntelXeonV2b-96a}).
 Code that uses these non-temporal move instructions
-can also use {\tt mfence} for \co{smp_mb()},
-{\tt lfence} for \co{smp_rmb()}, and {\tt sfence} for \co{smp_wmb()}.
+can also use \co{mfence} for \co{smp_mb()},
+\co{lfence} for \co{smp_rmb()}, and \co{sfence} for \co{smp_wmb()}.
 A few older variants of the x86 CPU have a mode bit that enables out-of-order
 stores, and for these CPUs, \co{smp_wmb()} must also be defined to
-be {\tt lock;addl}.
+be \co{lock;addl}.
 
 Although newer x86 implementations accommodate self-modifying code
 without any special instructions, to be fully compatible with
-- 
2.17.1

[PATCH 07/10] memorder: Consistently use '\co{}' for 'herd'

[SeongJae Park]

From: SeongJae Park <sj38.park@gmail.com>

All sentences but one in memorder.tex use \co{} for herd.  Use it
consistently.

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index b7699129..5ded6988 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -527,7 +527,7 @@ sometimes substitute \co{WRITE_ONCE()} plus \co{smp_wmb()} for
 and \co{READ_ONCE()} plus \co{smp_rmb()} for \co{smp_load_acquire()}
 on the other.
 However, the wise developer will check such substitutions carefully,
-for example, using the herd tool as described in
+for example, using the \co{herd} tool as described in
 \cref{sec:formal:Axiomatic Approaches}
 on
 \cpageref{sec:formal:Axiomatic Approaches}.
-- 
2.17.1

[PATCH 08/10] memorder: Remove a redundant sentence for memory barrier strength

[SeongJae Park]

From: SeongJae Park <sj38.park@gmail.com>

A sentence in memorder.tex explains the strength of smp_mb() and its
cost.  Then, a quick quiz having very same answer follows.  Remove the
sentence to reduce the redundancy.

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 2 --
 1 file changed, 2 deletions(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index 5ded6988..bd24b14c 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -1346,8 +1346,6 @@ illustrates this for memory barriers.
 Assuming that both memory barriers are strong enough, if CPU~1's access
 Y1 happens after CPU~0's access Y0, then CPU~1's access X1 is guaranteed
 to happen after CPU~0's access X0.
-When in doubt as to which memory barriers are strong enough, \co{smp_mb()}
-will always do the job, albeit at a price.
 
 \QuickQuiz{
 	How can you tell which memory barriers are strong enough for
-- 
2.17.1

[PATCH 09/10] memorder: Make clear the scope of READ_ONCE()/WRITE_ONCE() heavy uses

[SeongJae Park]

From: SeongJae Park <sj38.park@gmail.com>

A sentence in memorder.tex is saying READ_ONCE() and WRITE_ONCE() will
be heavily used in a section.  But, it's widely used in the chapter.
Modify the sentence to make it more clear.

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index bd24b14c..5c978fbe 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -668,7 +668,7 @@ even on relatively strongly ordered systems such as x86.
 	\co{READ_ONCE()} and \co{WRITE_ONCE()}
 	prevent the compiler from reordering.
 	And also from doing much else as well, so the examples in this
-	section will be making heavy use of
+	chapter will be making heavy use of
 	\co{READ_ONCE()} and \co{WRITE_ONCE()}.
 	See \cref{sec:memorder:Compile-Time Consternation}
 	for more detail on the need for \co{READ_ONCE()} and \co{WRITE_ONCE()}.
-- 
2.17.1

[PATCH 10/10] memorder: Fix wrong primitive names in a quick quizz

[SeongJae Park]

From: SeongJae Park <sj38.park@gmail.com>

memorder.tex explains READ_ONCE() is having smp_mb(), but the following
quick quizz asks why it has mb() instead of rmb().  Fix the wrong names
in the quick quizz.

Signed-off-by: SeongJae Park <sj38.park@gmail.com>
---
 memorder/memorder.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index 5c978fbe..b3acc14a 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -5491,7 +5491,7 @@ Alpha is the only CPU whose \co{READ_ONCE()} includes an \co{smp_mb()}.
 \QuickQuizSeries{%
 \QuickQuizB{
 	Why does Alpha's \co{READ_ONCE()} include an
-	\co{mb()} rather than \co{rmb()}?
+	\co{smp_mb()} rather than \co{smp_rmb()}?
 }\QuickQuizAnswerB{
 	Alpha has only \co{mb} and \co{wmb} instructions,
 	so \co{smp_rmb()} would be implemented by the Alpha \co{mb}
-- 
2.17.1

Re: [PATCH 10/10] memorder: Fix wrong primitive names in a quick quizz

[Akira Yokosawa]

Hi,

On 2023/09/24 1:32, SeongJae Park wrote:
> From: SeongJae Park <sj38.park@gmail.com>
> 
> memorder.tex explains READ_ONCE() is having smp_mb(), but the following
> quick quizz asks why it has mb() instead of rmb().  Fix the wrong names
> in the quick quizz.
> 
> Signed-off-by: SeongJae Park <sj38.park@gmail.com>
> ---
>  memorder/memorder.tex | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/memorder/memorder.tex b/memorder/memorder.tex
> index 5c978fbe..b3acc14a 100644
> --- a/memorder/memorder.tex
> +++ b/memorder/memorder.tex
> @@ -5491,7 +5491,7 @@ Alpha is the only CPU whose \co{READ_ONCE()} includes an \co{smp_mb()}.
>  \QuickQuizSeries{%
>  \QuickQuizB{
>  	Why does Alpha's \co{READ_ONCE()} include an
> -	\co{mb()} rather than \co{rmb()}?
> +	\co{smp_mb()} rather than \co{smp_rmb()}?

Definition in Linux kernel's arch/alpha/include/asm/rwonce.h reads:

#define __READ_ONCE(x)							\
({									\
	__unqual_scalar_typeof(x) __x =					\
		(*(volatile typeof(__x) *)(&(x)));			\
	mb();								\
	(typeof(x))__x;							\
})

So I don't think this change is needed.

As this quiz is talking about Alpha ISA, how about rewording the
quiz to:

    Why does Alpha's \co{READ_ONCE()} include an
    \co{mb} instruction rather than a \co{rmb}?

        Thanks, Akira

>  }\QuickQuizAnswerB{
>  	Alpha has only \co{mb} and \co{wmb} instructions,
>  	so \co{smp_rmb()} would be implemented by the Alpha \co{mb}
> -- 
> 2.17.1

Re: [PATCH 00/10] memorder: Trivial fixups

[Paul E. McKenney]

On Sat, Sep 23, 2023 at 09:31:54AM -0700, SeongJae Park wrote:
> From: SeongJae Park <sj38.park@gmail.com>
> 
> This patchset contains trivial fixups memorderdebugging/, which found
> while doing Korean translation[1].
> 
> [1] https://github.com/sjp38/perfbook-ko_KR

Very good, thank you!!!  I have queued and pushed all but the last one.

							Thanx, Paul

> SeongJae Park (10):
>   memorder: Fix typos: s/,/./
>   memorder/memorder: Add a missing space between column name and
>     'column'
>   memorder: Add missing unbreakable spaces between 'values', 'and', and
>     numbers
>   memorder: Remove an empty fcvref block
>   memorder: Remove braces for single line if-else blocks
>   memorder: Consistently use \co{} instead of {\tt } for code
>   memorder: Consistently use '\co{}' for 'herd'
>   memorder: Remove a redundant sentence for memory barrier strength
>   memorder: Make clear the scope of READ_ONCE()/WRITE_ONCE() heavy uses
>   memorder: Fix wrong primitive names in a quick quizz
> 
>  memorder/memorder.tex | 72 ++++++++++++++++++++-----------------------
>  1 file changed, 33 insertions(+), 39 deletions(-)
> 
> -- 
> 2.17.1
> 

Re: [PATCH 10/10] memorder: Fix wrong primitive names in a quick quizz

[SeongJae Park]

Hi Akira,

On Sun, 24 Sep 2023 09:02:53 +0900 Akira Yokosawa <akiyks@gmail.com> wrote:

> Hi,
> 
> On 2023/09/24 1:32, SeongJae Park wrote:
> > From: SeongJae Park <sj38.park@gmail.com>
> > 
> > memorder.tex explains READ_ONCE() is having smp_mb(), but the following
> > quick quizz asks why it has mb() instead of rmb().  Fix the wrong names
> > in the quick quizz.
> > 
> > Signed-off-by: SeongJae Park <sj38.park@gmail.com>
> > ---
> >  memorder/memorder.tex | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/memorder/memorder.tex b/memorder/memorder.tex
> > index 5c978fbe..b3acc14a 100644
> > --- a/memorder/memorder.tex
> > +++ b/memorder/memorder.tex
> > @@ -5491,7 +5491,7 @@ Alpha is the only CPU whose \co{READ_ONCE()} includes an \co{smp_mb()}.
> >  \QuickQuizSeries{%
> >  \QuickQuizB{
> >  	Why does Alpha's \co{READ_ONCE()} include an
> > -	\co{mb()} rather than \co{rmb()}?
> > +	\co{smp_mb()} rather than \co{smp_rmb()}?
> 
> Definition in Linux kernel's arch/alpha/include/asm/rwonce.h reads:
> 
> #define __READ_ONCE(x)							\
> ({									\
> 	__unqual_scalar_typeof(x) __x =					\
> 		(*(volatile typeof(__x) *)(&(x)));			\
> 	mb();								\
> 	(typeof(x))__x;							\
> })
> 
> So I don't think this change is needed.
> 
> As this quiz is talking about Alpha ISA, how about rewording the
> quiz to:
> 
>     Why does Alpha's \co{READ_ONCE()} include an
>     \co{mb} instruction rather than a \co{rmb}?
> 
>         Thanks, Akira
> 
> >  }\QuickQuizAnswerB{
> >  	Alpha has only \co{mb} and \co{wmb} instructions,
> >  	so \co{smp_rmb()} would be implemented by the Alpha \co{mb}
> > -- 
> > 2.17.1

That makes sense.  Thank you for nice review and suggestion!  I will make the
second version of this patch following your comment.


Thanks,
SJ