From: Konrad Dybcio <konrad.dybcio@somainline.org>
To: phone-devel@vger.kernel.org
Cc: ~postmarketos/upstreaming@lists.sr.ht,
martin.botka@somainline.org,
angelogioacchino.delregno@somainline.org,
marijn.suijten@somainline.org,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Taniya Das <tdas@codeaurora.org>,
Craig Tatlor <ctatlor97@gmail.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: [PATCH 5/6] clk: qcom: gcc-sdm660: Account for needed adjustments in probe function
Date: Sat, 20 Feb 2021 16:56:16 +0100 [thread overview]
Message-ID: <20210220155618.176559-5-konrad.dybcio@somainline.org> (raw)
In-Reply-To: <20210220155618.176559-1-konrad.dybcio@somainline.org>
Downstream kernel executes a bunch of commands, such as keeping
GPU/MMSS interface clocks alive to make sure all subsystems can
work properly. Add these to make sure they do.
Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
drivers/clk/qcom/gcc-sdm660.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
index bc8dfcd6d629..db2185c88b77 100644
--- a/drivers/clk/qcom/gcc-sdm660.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -11,6 +11,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
+#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
@@ -2622,7 +2623,27 @@ static int gcc_sdm660_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap);
+ ret = qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap);
+ if (ret)
+ return ret;
+
+ /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
+ regmap_update_bits(regmap, 0x0902c, 0x3, 0x3);
+ regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
+
+ /* This clock is used for all MMSSCC register access */
+ clk_prepare_enable(gcc_mmss_noc_cfg_ahb_clk.clkr.hw.clk);
+
+ /* This clock is used for all GPUCC register access */
+ clk_prepare_enable(gcc_gpu_cfg_ahb_clk.clkr.hw.clk);
+
+ /* Keep bimc gfx clock port on all the time */
+ clk_prepare_enable(gcc_bimc_gfx_clk.clkr.hw.clk);
+
+ /* Set the HMSS_GPLL0_SRC for 300MHz to CPU subsystem */
+ clk_set_rate(hmss_gpll0_clk_src.clkr.hw.clk, 300000000);
+
+ return ret;
}
static struct platform_driver gcc_sdm660_driver = {
--
2.30.1
next prev parent reply other threads:[~2021-02-20 15:58 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-20 15:56 [PATCH 1/6] clk: qcom: gcc-sdm660: Fix hmss_gpll0_clk_src parent_map Konrad Dybcio
2021-02-20 15:56 ` [PATCH 2/6] clk: qcom: gcc-sdm660: Set HWCG bit to 1 on some clocks Konrad Dybcio
2021-02-20 15:56 ` [PATCH 3/6] clk: qcom: gcc-sdm660: Add missing clocks and GDSCs Konrad Dybcio
2021-02-20 15:56 ` [PATCH 4/6] clk: qcom: gcc-sdm660: Remove gds_hw_ctrl from GDSCs Konrad Dybcio
2021-02-20 15:56 ` Konrad Dybcio [this message]
2021-02-23 0:39 ` [PATCH 5/6] clk: qcom: gcc-sdm660: Account for needed adjustments in probe function Stephen Boyd
2021-02-25 19:09 ` Konrad Dybcio
2021-04-01 1:53 ` Stephen Boyd
2021-04-01 21:10 ` Konrad Dybcio
2021-05-26 19:11 ` Konrad Dybcio
2021-05-26 22:32 ` Stephen Boyd
2021-02-20 15:56 ` [PATCH 6/6] clk: qcom: gcc-sdm660: Add CLK_SET_RATE_PARENT where applicable Konrad Dybcio
2021-02-23 0:42 ` Stephen Boyd
2021-02-25 19:27 ` Konrad Dybcio
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