From: Marijn Suijten <marijn.suijten@somainline.org>
To: phone-devel@vger.kernel.org
Cc: ~postmarketos/upstreaming@lists.sr.ht,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org>,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Martin Botka <martin.botka@somainline.org>,
Jami Kettunen <jami.kettunen@somainline.org>,
Marijn Suijten <marijn.suijten@somainline.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Taniya Das <tdas@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 3/8] clk: qcom: gcc-msm8998: Remove transient global "xo" clock
Date: Sat, 11 Sep 2021 14:13:35 +0200 [thread overview]
Message-ID: <20210911121340.261920-4-marijn.suijten@somainline.org> (raw)
In-Reply-To: <20210911121340.261920-1-marijn.suijten@somainline.org>
Now that all clock controllers and the DSI PLL clocks rely on "xo" being
passed in DT as phandle instead of looking it up by the global "xo" name
this transient clock can be removed, leaving only the fixed-factor
"xo_board" clock in DT.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
---
drivers/clk/qcom/gcc-msm8998.c | 57 ++++++++++++++++++----------------
1 file changed, 30 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 9320e2ba659a..407e2c5caea4 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -25,17 +25,6 @@
#include "reset.h"
#include "gdsc.h"
-static struct clk_fixed_factor xo = {
- .mult = 1,
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "xo",
- .parent_names = (const char *[]){ "xo_board" },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-};
-
static struct pll_vco fabia_vco[] = {
{ 250000000, 2000000000, 0 },
{ 125000000, 1000000000, 1 },
@@ -51,7 +40,9 @@ static struct clk_alpha_pll gpll0 = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xo" },
+ },
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
@@ -120,7 +111,9 @@ static struct clk_alpha_pll gpll1 = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xo" },
+ },
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
@@ -189,7 +182,9 @@ static struct clk_alpha_pll gpll2 = {
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll2",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xo" },
+ },
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
@@ -258,7 +253,9 @@ static struct clk_alpha_pll gpll3 = {
.enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){
.name = "gpll3",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xo" },
+ },
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
@@ -327,7 +324,9 @@ static struct clk_alpha_pll gpll4 = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gpll4",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xo" },
+ },
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_fabia_ops,
}
@@ -2761,7 +2760,9 @@ static struct clk_branch gcc_hdmi_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_hdmi_clkref_clk",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xo" },
+ },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
@@ -2775,7 +2776,9 @@ static struct clk_branch gcc_ufs_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_clkref_clk",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xo" },
+ },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
@@ -2789,7 +2792,9 @@ static struct clk_branch gcc_usb3_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_clkref_clk",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xo" },
+ },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
@@ -2803,7 +2808,9 @@ static struct clk_branch gcc_pcie_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_clkref_clk",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xo" },
+ },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
@@ -2817,7 +2824,9 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_rx1_usb2_clkref_clk",
- .parent_names = (const char *[]){ "xo" },
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xo" },
+ },
.num_parents = 1,
.ops = &clk_branch2_ops,
},
@@ -3155,10 +3164,6 @@ static const struct regmap_config gcc_msm8998_regmap_config = {
.fast_io = true,
};
-static struct clk_hw *gcc_msm8998_hws[] = {
- &xo.hw,
-};
-
static const struct qcom_cc_desc gcc_msm8998_desc = {
.config = &gcc_msm8998_regmap_config,
.clks = gcc_msm8998_clocks,
@@ -3167,8 +3172,6 @@ static const struct qcom_cc_desc gcc_msm8998_desc = {
.num_resets = ARRAY_SIZE(gcc_msm8998_resets),
.gdscs = gcc_msm8998_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
- .clk_hws = gcc_msm8998_hws,
- .num_clk_hws = ARRAY_SIZE(gcc_msm8998_hws),
};
static int gcc_msm8998_probe(struct platform_device *pdev)
--
2.33.0
next prev parent reply other threads:[~2021-09-11 12:14 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-11 12:13 [PATCH 0/8] msm8998 clock-controller cleanup Marijn Suijten
2021-09-11 12:13 ` [PATCH 1/8] clk: qcom: gcc-msm8998: Move parent names and mapping below GPLLs Marijn Suijten
2021-09-14 21:41 ` Stephen Boyd
2021-09-11 12:13 ` [PATCH 2/8] clk: qcom: gcc-msm8998: Use parent_data/hws for internal clock relations Marijn Suijten
2021-09-14 21:41 ` Stephen Boyd
2021-09-11 12:13 ` Marijn Suijten [this message]
2021-09-14 21:42 ` [PATCH 3/8] clk: qcom: gcc-msm8998: Remove transient global "xo" clock Stephen Boyd
2021-09-11 12:13 ` [PATCH 4/8] clk: qcom: gpucc-msm8998: Use ARRAY_SIZE for num_parents Marijn Suijten
2021-09-14 21:42 ` Stephen Boyd
2021-09-11 12:13 ` [PATCH 5/8] clk: qcom: mmcc-msm8998: " Marijn Suijten
2021-09-14 21:42 ` Stephen Boyd
2021-09-11 12:13 ` [PATCH 6/8] dt-bindings: clocks: qcom,gcc-msm8998: Reflect actually referenced clks Marijn Suijten
2021-09-14 21:42 ` Stephen Boyd
2021-09-11 12:13 ` [PATCH 7/8] clk: qcom: gpucc-msm8998: Remove unnecessary fallbacks to global clocks Marijn Suijten
2021-09-14 21:42 ` Stephen Boyd
2021-09-11 12:13 ` [PATCH 8/8] clk: qcom: mmcc-msm8998: " Marijn Suijten
2021-09-14 21:42 ` Stephen Boyd
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