[PATCH v1 0/4] Add Alder Lake PCH-S support to PMC core driver

[PATCH v1 0/4] Add Alder Lake PCH-S support to PMC core driver

[Gayatri Kammela]

Hi,
The patch series add Alder Lake PCH-S support to PMC core driver.

Patch 1: Add Alderlake support to pmc_core driver
Patch 2: Add Latency Tolerance Reporting (LTR) support to Alder Lake
Patch 3: Add Alder Lake low power mode support for pmc_core
Patch 4: Add GBE Package C10 fix for Alder Lake

David E. Box (1):
  platform/x86: intel_pmc_core: Add GBE Package C10 fix for Alder Lake
    PCH

Gayatri Kammela (3):
  platform/x86: intel_pmc_core: Add Alderlake support to pmc_core driver
  platform/x86: intel_pmc_core: Add Latency Tolerance Reporting (LTR)
    support to Alder Lake
  platform/x86: intel_pmc_core: Add Alder Lake low power mode support
    for pmc_core

 drivers/platform/x86/intel_pmc_core.c | 307 +++++++++++++++++++++++++-
 drivers/platform/x86/intel_pmc_core.h |  17 ++
 2 files changed, 321 insertions(+), 3 deletions(-)

Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David Box <david.e.box@intel.com>

base-commit: 62fb9874f5da54fdb243003b386128037319b219
-- 
2.25.1

[PATCH v1 1/4] platform/x86: intel_pmc_core: Add Alderlake support to pmc_core driver

[Gayatri Kammela]

Add Alder Lake client and mobile support to pmc_core driver.

Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David Box <david.e.box@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
 drivers/platform/x86/intel_pmc_core.c | 68 +++++++++++++++++++++++++++
 drivers/platform/x86/intel_pmc_core.h |  2 +
 2 files changed, 70 insertions(+)

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index b0e486a6bdfb..441018e3ce96 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -645,6 +645,73 @@ static void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev)
 	ACPI_FREE(out_obj);
 }
 
+/* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */
+static const struct pmc_bit_map adl_pfear_map[] = {
+	{"SPI/eSPI",		BIT(2)},
+	{"XHCI",		BIT(3)},
+	{"SPA",			BIT(4)},
+	{"SPB",			BIT(5)},
+	{"SPC",			BIT(6)},
+	{"GBE",			BIT(7)},
+
+	{"SATA",		BIT(0)},
+	{"HDA_PGD0",		BIT(1)},
+	{"HDA_PGD1",		BIT(2)},
+	{"HDA_PGD2",		BIT(3)},
+	{"HDA_PGD3",		BIT(4)},
+	{"SPD",			BIT(5)},
+	{"LPSS",		BIT(6)},
+
+	{"SMB",			BIT(0)},
+	{"ISH",			BIT(1)},
+	{"ITH",			BIT(3)},
+
+	{"XDCI",		BIT(1)},
+	{"DCI",			BIT(2)},
+	{"CSE",			BIT(3)},
+	{"CSME_KVM",		BIT(4)},
+	{"CSME_PMT",		BIT(5)},
+	{"CSME_CLINK",		BIT(6)},
+	{"CSME_PTIO",		BIT(7)},
+
+	{"CSME_USBR",		BIT(0)},
+	{"CSME_SUSRAM",		BIT(1)},
+	{"CSME_SMT1",		BIT(2)},
+	{"CSME_SMS2",		BIT(4)},
+	{"CSME_SMS1",		BIT(5)},
+	{"CSME_RTC",		BIT(6)},
+	{"CSME_PSF",		BIT(7)},
+
+	{"CNVI",		BIT(3)},
+
+	{"HDA_PGD4",		BIT(2)},
+	{"HDA_PGD5",		BIT(3)},
+	{"HDA_PGD6",		BIT(4)},
+	{}
+};
+
+static const struct pmc_bit_map *ext_adl_pfear_map[] = {
+	/*
+	 * Check intel_pmc_core_ids[] users of cnp_reg_map for
+	 * a list of core SoCs using this.
+	 */
+	adl_pfear_map,
+	NULL
+};
+
+static const struct pmc_reg_map adl_reg_map = {
+	.pfear_sts = ext_adl_pfear_map,
+	.slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET,
+	.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
+	.msr_sts = msr_map,
+	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
+	.regmap_length = CNP_PMC_MMIO_REG_LEN,
+	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
+	.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
+	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
+	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
+};
+
 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
 {
 	return readl(pmcdev->regbase + reg_offset);
@@ -1574,6 +1641,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
 	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,	&icl_reg_map),
 	X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,		&tgl_reg_map),
 	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&tgl_reg_map),
+	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&adl_reg_map),
 	{}
 };
 
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h
index e8dae9c6c45f..c0ca20b32c6b 100644
--- a/drivers/platform/x86/intel_pmc_core.h
+++ b/drivers/platform/x86/intel_pmc_core.h
@@ -197,6 +197,8 @@ enum ppfear_regs {
 #define TGL_NUM_IP_IGN_ALLOWED			23
 #define TGL_PMC_LPM_RES_COUNTER_STEP_X2		61	/* 30.5us * 2 */
 
+#define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET	0x1098
+
 /*
  * Tigerlake Power Management Controller register offsets
  */
-- 
2.25.1

[PATCH v1 2/4] platform/x86: intel_pmc_core: Add Latency Tolerance Reporting (LTR) support to Alder Lake

[Gayatri Kammela]

Add support to show the Latency Tolerance Reporting for the IPs on
the Alder Lake PCH as reported by the PMC. This LTR support on
Alder Lake is slightly different from the Cannon lake PCH that is being
reused by all platforms till Tiger Lake.

Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David Box <david.e.box@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
 drivers/platform/x86/intel_pmc_core.c | 39 +++++++++++++++++++++++++++
 drivers/platform/x86/intel_pmc_core.h |  2 ++
 2 files changed, 41 insertions(+)

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index 441018e3ce96..611019bfe685 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -699,10 +699,48 @@ static const struct pmc_bit_map *ext_adl_pfear_map[] = {
 	NULL
 };
 
+static const struct pmc_bit_map adl_ltr_show_map[] = {
+	{"SOUTHPORT_A",		CNP_PMC_LTR_SPA},
+	{"SOUTHPORT_B",		CNP_PMC_LTR_SPB},
+	{"SATA",		CNP_PMC_LTR_SATA},
+	{"GIGABIT_ETHERNET",	CNP_PMC_LTR_GBE},
+	{"XHCI",		CNP_PMC_LTR_XHCI},
+	{"SOUTHPORT_F",		ADL_PMC_LTR_SPF},
+	{"ME",			CNP_PMC_LTR_ME},
+	/* EVA is Enterprise Value Add, doesn't really exist on PCH */
+	{"SATA1",		CNP_PMC_LTR_EVA},
+	{"SOUTHPORT_C",		CNP_PMC_LTR_SPC},
+	{"HD_AUDIO",		CNP_PMC_LTR_AZ},
+	{"CNV",			CNP_PMC_LTR_CNV},
+	{"LPSS",		CNP_PMC_LTR_LPSS},
+	{"SOUTHPORT_D",		CNP_PMC_LTR_SPD},
+	{"SOUTHPORT_E",		CNP_PMC_LTR_SPE},
+	{"SATA2",		CNP_PMC_LTR_CAM},
+	{"ESPI",		CNP_PMC_LTR_ESPI},
+	{"SCC",			CNP_PMC_LTR_SCC},
+	{"ISH",			CNP_PMC_LTR_ISH},
+	{"UFSX2",		CNP_PMC_LTR_UFSX2},
+	{"EMMC",		CNP_PMC_LTR_EMMC},
+	/*
+	 * Check intel_pmc_core_ids[] users of cnp_reg_map for
+	 * a list of core SoCs using this.
+	 */
+	{"WIGIG",		ICL_PMC_LTR_WIGIG},
+	{"THC0",		TGL_PMC_LTR_THC0},
+	{"THC1",		TGL_PMC_LTR_THC1},
+	{"SOUTHPORT_G",		CNP_PMC_LTR_RESERVED},
+
+	/* Below two cannot be used for LTR_IGNORE */
+	{"CURRENT_PLATFORM",	CNP_PMC_LTR_CUR_PLT},
+	{"AGGREGATED_SYSTEM",	CNP_PMC_LTR_CUR_ASLT},
+	{}
+};
+
 static const struct pmc_reg_map adl_reg_map = {
 	.pfear_sts = ext_adl_pfear_map,
 	.slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET,
 	.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
+	.ltr_show_sts = adl_ltr_show_map,
 	.msr_sts = msr_map,
 	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 	.regmap_length = CNP_PMC_MMIO_REG_LEN,
@@ -710,6 +748,7 @@ static const struct pmc_reg_map adl_reg_map = {
 	.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
 	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
 	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
+	.ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
 };
 
 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h
index c0ca20b32c6b..45b352ece6db 100644
--- a/drivers/platform/x86/intel_pmc_core.h
+++ b/drivers/platform/x86/intel_pmc_core.h
@@ -197,6 +197,8 @@ enum ppfear_regs {
 #define TGL_NUM_IP_IGN_ALLOWED			23
 #define TGL_PMC_LPM_RES_COUNTER_STEP_X2		61	/* 30.5us * 2 */
 
+#define ADL_PMC_LTR_SPF				0x1C00
+#define ADL_NUM_IP_IGN_ALLOWED			23
 #define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET	0x1098
 
 /*
-- 
2.25.1

[PATCH v1 3/4] platform/x86: intel_pmc_core: Add Alder Lake low power mode support for pmc_core

[Gayatri Kammela]

Alder Lake has 14 status registers that are memory mapped. These
registers show the status of the low power mode requirements. The
registers are latched on every C10 entry or exit and on every s0ix.y
entry/exit. Accessing these registers is useful for debugging any low
power related activities.

Thus, add debugfs entry to access low power mode status registers.

Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David Box <david.e.box@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
 drivers/platform/x86/intel_pmc_core.c | 194 ++++++++++++++++++++++++++
 drivers/platform/x86/intel_pmc_core.h |  13 ++
 2 files changed, 207 insertions(+)

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index 611019bfe685..27346ff5a924 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -736,6 +736,189 @@ static const struct pmc_bit_map adl_ltr_show_map[] = {
 	{}
 };
 
+static const struct pmc_bit_map adl_clocksource_status_map[] = {
+	{"CLKPART1_OFF_STS",			BIT(0)},
+	{"CLKPART2_OFF_STS",			BIT(1)},
+	{"CLKPART3_OFF_STS",			BIT(2)},
+	{"CLKPART4_OFF_STS",			BIT(3)},
+	{"CLKPART5_OFF_STS",			BIT(4)},
+	{"CLKPART6_OFF_STS",			BIT(5)},
+	{"CLKPART7_OFF_STS",			BIT(6)},
+	{"CLKPART8_OFF_STS",			BIT(7)},
+	{"PCIE0PLL_OFF_STS",			BIT(10)},
+	{"PCIE1PLL_OFF_STS",			BIT(11)},
+	{"PCIE2PLL_OFF_STS",			BIT(12)},
+	{"PCIE3PLL_OFF_STS",			BIT(13)},
+	{"PCIE4PLL_OFF_STS",			BIT(14)},
+	{"PCIE5PLL_OFF_STS",			BIT(15)},
+	{"PCIE6PLL_OFF_STS",			BIT(16)},
+	{"USB2PLL_OFF_STS",			BIT(18)},
+	{"OCPLL_OFF_STS",			BIT(22)},
+	{"AUDIOPLL_OFF_STS",			BIT(23)},
+	{"GBEPLL_OFF_STS",			BIT(24)},
+	{"Fast_XTAL_Osc_OFF_STS",		BIT(25)},
+	{"AC_Ring_Osc_OFF_STS",			BIT(26)},
+	{"MC_Ring_Osc_OFF_STS",			BIT(27)},
+	{"SATAPLL_OFF_STS",			BIT(29)},
+	{"USB3PLL_OFF_STS",			BIT(31)},
+	{}
+};
+
+static const struct pmc_bit_map adl_power_gating_status_0_map[] = {
+	{"PMC_PGD0_PG_STS",			BIT(0)},
+	{"DMI_PGD0_PG_STS",			BIT(1)},
+	{"ESPISPI_PGD0_PG_STS",			BIT(2)},
+	{"XHCI_PGD0_PG_STS",			BIT(3)},
+	{"SPA_PGD0_PG_STS",			BIT(4)},
+	{"SPB_PGD0_PG_STS",			BIT(5)},
+	{"SPC_PGD0_PG_STS",			BIT(6)},
+	{"GBE_PGD0_PG_STS",			BIT(7)},
+	{"SATA_PGD0_PG_STS",			BIT(8)},
+	{"DSP_PGD0_PG_STS",			BIT(9)},
+	{"DSP_PGD1_PG_STS",			BIT(10)},
+	{"DSP_PGD2_PG_STS",			BIT(11)},
+	{"DSP_PGD3_PG_STS",			BIT(12)},
+	{"SPD_PGD0_PG_STS",			BIT(13)},
+	{"LPSS_PGD0_PG_STS",			BIT(14)},
+	{"SMB_PGD0_PG_STS",			BIT(16)},
+	{"ISH_PGD0_PG_STS",			BIT(17)},
+	{"NPK_PGD0_PG_STS",			BIT(19)},
+	{"PECI_PGD0_PG_STS",			BIT(21)},
+	{"XDCI_PGD0_PG_STS",			BIT(25)},
+	{"EXI_PGD0_PG_STS",			BIT(26)},
+	{"CSE_PGD0_PG_STS",			BIT(27)},
+	{"KVMCC_PGD0_PG_STS",			BIT(28)},
+	{"PMT_PGD0_PG_STS",			BIT(29)},
+	{"CLINK_PGD0_PG_STS",			BIT(30)},
+	{"PTIO_PGD0_PG_STS",			BIT(31)},
+	{}
+};
+
+static const struct pmc_bit_map adl_power_gating_status_1_map[] = {
+	{"USBR0_PGD0_PG_STS",			BIT(0)},
+	{"SMT1_PGD0_PG_STS",			BIT(2)},
+	{"CSMERTC_PGD0_PG_STS",			BIT(6)},
+	{"CSMEPSF_PGD0_PG_STS",			BIT(7)},
+	{"CNVI_PGD0_PG_STS",			BIT(19)},
+	{"DSP_PGD4_PG_STS",			BIT(26)},
+	{"SPG_PGD0_PG_STS",			BIT(27)},
+	{"SPE_PGD0_PG_STS",			BIT(28)},
+	{}
+};
+
+static const struct pmc_bit_map adl_power_gating_status_2_map[] = {
+	{"THC0_PGD0_PG_STS",			BIT(7)},
+	{"THC1_PGD0_PG_STS",			BIT(8)},
+	{"SPF_PGD0_PG_STS",			BIT(14)},
+	{}
+};
+
+static const struct pmc_bit_map adl_d3_status_0_map[] = {
+	{"ISH_D3_STS",				BIT(2)},
+	{"LPSS_D3_STS",				BIT(3)},
+	{"XDCI_D3_STS",				BIT(4)},
+	{"XHCI_D3_STS",				BIT(5)},
+	{"SPA_D3_STS",				BIT(12)},
+	{"SPB_D3_STS",				BIT(13)},
+	{"SPC_D3_STS",				BIT(14)},
+	{"SPD_D3_STS",				BIT(15)},
+	{"SPE_D3_STS",				BIT(16)},
+	{"DSP_D3_STS",				BIT(19)},
+	{"SATA_D3_STS",				BIT(20)},
+	{"DMI_D3_STS",				BIT(22)},
+	{}
+};
+
+static const struct pmc_bit_map adl_d3_status_1_map[] = {
+	{"GBE_D3_STS",				BIT(19)},
+	{"CNVI_D3_STS",				BIT(27)},
+	{}
+};
+
+static const struct pmc_bit_map adl_d3_status_2_map[] = {
+	{"CSMERTC_D3_STS",			BIT(1)},
+	{"CSE_D3_STS",				BIT(4)},
+	{"KVMCC_D3_STS",			BIT(5)},
+	{"USBR0_D3_STS",			BIT(6)},
+	{"SMT1_D3_STS",				BIT(8)},
+	{"PTIO_D3_STS",				BIT(16)},
+	{"PMT_D3_STS",				BIT(17)},
+	{}
+};
+
+static const struct pmc_bit_map adl_d3_status_3_map[] = {
+	{"THC0_D3_STS",				BIT(14)},
+	{"THC1_D3_STS",				BIT(15)},
+	{}
+};
+
+static const struct pmc_bit_map adl_vnn_req_status_0_map[] = {
+	{"ISH_VNN_REQ_STS",			BIT(2)},
+	{"ESPISPI_VNN_REQ_STS",			BIT(18)},
+	{"DSP_VNN_REQ_STS",			BIT(19)},
+	{}
+};
+
+static const struct pmc_bit_map adl_vnn_req_status_1_map[] = {
+	{"NPK_VNN_REQ_STS",			BIT(4)},
+	{"EXI_VNN_REQ_STS",			BIT(9)},
+	{"GBE_VNN_REQ_STS",			BIT(19)},
+	{"SMB_VNN_REQ_STS",			BIT(25)},
+	{"CNVI_VNN_REQ_STS",			BIT(27)},
+	{}
+};
+
+static const struct pmc_bit_map adl_vnn_req_status_2_map[] = {
+	{"CSMERTC_VNN_REQ_STS",			BIT(1)},
+	{"CSE_VNN_REQ_STS",			BIT(4)},
+	{"SMT1_VNN_REQ_STS",			BIT(8)},
+	{"CLINK_VNN_REQ_STS",			BIT(14)},
+	{"GPIOCOM4_VNN_REQ_STS",		BIT(20)},
+	{"GPIOCOM3_VNN_REQ_STS",		BIT(21)},
+	{"GPIOCOM2_VNN_REQ_STS",		BIT(22)},
+	{"GPIOCOM1_VNN_REQ_STS",		BIT(23)},
+	{"GPIOCOM0_VNN_REQ_STS",		BIT(24)},
+	{}
+};
+
+static const struct pmc_bit_map adl_vnn_req_status_3_map[] = {
+	{"GPIOCOM5_VNN_REQ_STS",		BIT(11)},
+	{}
+};
+
+static const struct pmc_bit_map adl_vnn_misc_status_map[] = {
+	{"CPU_C10_REQ_STS",			BIT(0)},
+	{"PCIe_LPM_En_REQ_STS",			BIT(3)},
+	{"ITH_REQ_STS",				BIT(5)},
+	{"CNVI_REQ_STS",			BIT(6)},
+	{"ISH_REQ_STS",				BIT(7)},
+	{"USB2_SUS_PG_Sys_REQ_STS",		BIT(10)},
+	{"PCIe_Clk_REQ_STS",			BIT(12)},
+	{"MPHY_Core_DL_REQ_STS",		BIT(16)},
+	{"Break-even_En_REQ_STS",		BIT(17)},
+	{"MPHY_SUS_REQ_STS",			BIT(22)},
+	{"xDCI_attached_REQ_STS",		BIT(24)},
+	{}
+};
+
+static const struct pmc_bit_map *adl_lpm_maps[] = {
+	adl_clocksource_status_map,
+	adl_power_gating_status_0_map,
+	adl_power_gating_status_1_map,
+	adl_power_gating_status_2_map,
+	adl_d3_status_0_map,
+	adl_d3_status_1_map,
+	adl_d3_status_2_map,
+	adl_d3_status_3_map,
+	adl_vnn_req_status_0_map,
+	adl_vnn_req_status_1_map,
+	adl_vnn_req_status_2_map,
+	adl_vnn_req_status_3_map,
+	adl_vnn_misc_status_map,
+	tgl_signal_status_map,
+	NULL
+};
+
 static const struct pmc_reg_map adl_reg_map = {
 	.pfear_sts = ext_adl_pfear_map,
 	.slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET,
@@ -749,6 +932,17 @@ static const struct pmc_reg_map adl_reg_map = {
 	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
 	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
 	.ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
+	.lpm_num_modes = ADL_LPM_NUM_MODES,
+	.lpm_num_maps = ADL_LPM_NUM_MAPS,
+	.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
+	.etr3_offset = ETR3_OFFSET,
+	.lpm_sts_latch_en_offset = ADL_LPM_STATUS_LATCH_EN_OFFSET,
+	.lpm_priority_offset = ADL_LPM_PRI_OFFSET,
+	.lpm_en_offset = ADL_LPM_EN_OFFSET,
+	.lpm_residency_offset = ADL_LPM_RESIDENCY_OFFSET,
+	.lpm_sts = adl_lpm_maps,
+	.lpm_status_offset = ADL_LPM_STATUS_OFFSET,
+	.lpm_live_status_offset = ADL_LPM_LIVE_STATUS_OFFSET,
 };
 
 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h
index 45b352ece6db..333e25981e8e 100644
--- a/drivers/platform/x86/intel_pmc_core.h
+++ b/drivers/platform/x86/intel_pmc_core.h
@@ -222,6 +222,18 @@ enum ppfear_regs {
 /* Extended Test Mode Register LPM bits (TGL and later */
 #define ETR3_CLEAR_LPM_EVENTS			BIT(28)
 
+/* Alder Lake Power Management Controller register offsets */
+#define ADL_LPM_EN_OFFSET			0x179C
+#define ADL_LPM_RESIDENCY_OFFSET		0x17A4
+#define ADL_LPM_NUM_MODES			2
+#define ADL_LPM_NUM_MAPS			14
+
+/* Alder Lake Low Power Mode debug registers */
+#define ADL_LPM_STATUS_OFFSET			0x170C
+#define ADL_LPM_PRI_OFFSET			0x17A0
+#define ADL_LPM_STATUS_LATCH_EN_OFFSET		0x1704
+#define ADL_LPM_LIVE_STATUS_OFFSET		0x1764
+
 const char *pmc_lpm_modes[] = {
 	"S0i2.0",
 	"S0i2.1",
@@ -281,6 +293,7 @@ struct pmc_reg_map {
 	const u32 pm_vric1_offset;
 	/* Low Power Mode registers */
 	const int lpm_num_maps;
+	const int lpm_num_modes;
 	const int lpm_res_counter_step_x2;
 	const u32 lpm_sts_latch_en_offset;
 	const u32 lpm_en_offset;
-- 
2.25.1

[PATCH v1 4/4] platform/x86: intel_pmc_core: Add GBE Package C10 fix for Alder Lake PCH

[Gayatri Kammela]

From: "David E. Box" <david.e.box@linux.intel.com>

Alder PCH uses the same Gigabit Ethernet (GBE) device as Tiger Lake PCH
which cannot achieve PC10 without ignoring the PMC GBE LTR. Add this
work around for Alder Lake PCH as well.

Signed-off-by: David E. Box <david.e.box@linux.intel.com>
---
 drivers/platform/x86/intel_pmc_core.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index 27346ff5a924..84b58b557a49 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -1983,10 +1983,10 @@ static int pmc_core_probe(struct platform_device *pdev)
 		pmc_core_get_tgl_lpm_reqs(pdev);
 
 	/*
-	 * On TGL, due to a hardware limitation, the GBE LTR blocks PC10 when
-	 * a cable is attached. Tell the PMC to ignore it.
+	 * On TGL and ADL, due to a hardware limitation, the GBE LTR blocks PC10
+	 * when a cable is attached. Tell the PMC to ignore it.
 	 */
-	if (pmcdev->map == &tgl_reg_map) {
+	if (pmcdev->map == &tgl_reg_map || pmcdev->map == &adl_reg_map) {
 		dev_dbg(&pdev->dev, "ignoring GBE LTR\n");
 		pmc_core_send_ltr_ignore(pmcdev, 3);
 	}
-- 
2.25.1

Re: [PATCH v1 0/4] Add Alder Lake PCH-S support to PMC core driver

[Andy Shevchenko]

On Thu, Jul 01, 2021 at 07:19:59PM -0700, Gayatri Kammela wrote:
> Hi,
> The patch series add Alder Lake PCH-S support to PMC core driver.
> 
> Patch 1: Add Alderlake support to pmc_core driver
> Patch 2: Add Latency Tolerance Reporting (LTR) support to Alder Lake
> Patch 3: Add Alder Lake low power mode support for pmc_core
> Patch 4: Add GBE Package C10 fix for Alder Lake

I have seen only three out of four patches. I think to avoid such you better
use --cc parameter to the `git send-email ...` (Or you may utilize the script
I'm using myself:
https://github.com/andy-shev/home-bin-tools/blob/master/ge2maintainer.sh).

Nevertheless, before doing anything on this, can you move the stuff under
drivers/platform/x86/intel/pmc/ first, please?

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v1 0/4] Add Alder Lake PCH-S support to PMC core driver

[You-Sheng Yang]

Hi, this works for me.

Tested-By: You-Sheng Yang <vicamo.yang@canonical.com>

On 7/2/21 10:19 AM, Gayatri Kammela wrote:
> Hi,
> The patch series add Alder Lake PCH-S support to PMC core driver.
> 
> Patch 1: Add Alderlake support to pmc_core driver
> Patch 2: Add Latency Tolerance Reporting (LTR) support to Alder Lake
> Patch 3: Add Alder Lake low power mode support for pmc_core
> Patch 4: Add GBE Package C10 fix for Alder Lake
> 
> David E. Box (1):
>   platform/x86: intel_pmc_core: Add GBE Package C10 fix for Alder Lake
>     PCH
> 
> Gayatri Kammela (3):
>   platform/x86: intel_pmc_core: Add Alderlake support to pmc_core driver
>   platform/x86: intel_pmc_core: Add Latency Tolerance Reporting (LTR)
>     support to Alder Lake
>   platform/x86: intel_pmc_core: Add Alder Lake low power mode support
>     for pmc_core
> 
>  drivers/platform/x86/intel_pmc_core.c | 307 +++++++++++++++++++++++++-
>  drivers/platform/x86/intel_pmc_core.h |  17 ++
>  2 files changed, 321 insertions(+), 3 deletions(-)
> 
> Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: David Box <david.e.box@intel.com>
> 
> base-commit: 62fb9874f5da54fdb243003b386128037319b219
> 

Re: [PATCH v1 0/4] Add Alder Lake PCH-S support to PMC core driver

[Hans de Goede]

Hi,

On 7/2/21 4:19 AM, Gayatri Kammela wrote:
> Hi,
> The patch series add Alder Lake PCH-S support to PMC core driver.
> 
> Patch 1: Add Alderlake support to pmc_core driver
> Patch 2: Add Latency Tolerance Reporting (LTR) support to Alder Lake
> Patch 3: Add Alder Lake low power mode support for pmc_core
> Patch 4: Add GBE Package C10 fix for Alder Lake
> 
> David E. Box (1):
>   platform/x86: intel_pmc_core: Add GBE Package C10 fix for Alder Lake
>     PCH
> 
> Gayatri Kammela (3):
>   platform/x86: intel_pmc_core: Add Alderlake support to pmc_core driver
>   platform/x86: intel_pmc_core: Add Latency Tolerance Reporting (LTR)
>     support to Alder Lake
>   platform/x86: intel_pmc_core: Add Alder Lake low power mode support
>     for pmc_core
> 
>  drivers/platform/x86/intel_pmc_core.c | 307 +++++++++++++++++++++++++-
>  drivers/platform/x86/intel_pmc_core.h |  17 ++
>  2 files changed, 321 insertions(+), 3 deletions(-)
> 
> Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: David Box <david.e.box@intel.com>
> 
> base-commit: 62fb9874f5da54fdb243003b386128037319b219

Thanks, the series looks good to me:

Reviewed-by: Hans de Goede <hdegoede@redhat.com>

For the series. As Andy already mentioned we are trying to move all
the Intel files to drivers/platform/x86/intel. Can you please send
a new version with an extra patch which first moves all the

drivers/platform/x86/intel_pmc_*.c files to: drivers/platform/x86/intel/pmc
and then apply the 4 patches from this series on top, see:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=72fbcac2f40e690e1a5584358750e546a2678c2c

For an example of a commit moving files to under drivers/platform/x86/intel/<subdir>

Regards,

Hans

RE: [PATCH v1 0/4] Add Alder Lake PCH-S support to PMC core driver

[Kammela, Gayatri]

> -----Original Message-----
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Sent: Friday, July 2, 2021 3:02 AM
> To: Kammela, Gayatri <gayatri.kammela@intel.com>
> Cc: platform-driver-x86@vger.kernel.org; mgross@linux.intel.com;
> hdegoede@redhat.com; irenic.rajneesh@gmail.com; Pandruvada, Srinivas
> <srinivas.pandruvada@intel.com>; Box, David E <david.e.box@intel.com>
> Subject: Re: [PATCH v1 0/4] Add Alder Lake PCH-S support to PMC core driver
> 
> On Thu, Jul 01, 2021 at 07:19:59PM -0700, Gayatri Kammela wrote:
> > Hi,
> > The patch series add Alder Lake PCH-S support to PMC core driver.
> >
> > Patch 1: Add Alderlake support to pmc_core driver Patch 2: Add Latency
> > Tolerance Reporting (LTR) support to Alder Lake Patch 3: Add Alder
> > Lake low power mode support for pmc_core Patch 4: Add GBE Package C10
> > fix for Alder Lake
> 
> I have seen only three out of four patches. I think to avoid such you better
> use --cc parameter to the `git send-email ...` (Or you may utilize the script I'm
> using myself:
> https://github.com/andy-shev/home-bin-
> tools/blob/master/ge2maintainer.sh).
Hi Andy, my bad, I didn't notice the 4th patch missing the Cc. thanks! I will use the script going forward.
> 
> Nevertheless, before doing anything on this, can you move the stuff under
> drivers/platform/x86/intel/pmc/ first, please?
Yes, sure I will do that.
> 
> --
> With Best Regards,
> Andy Shevchenko
> 

RE: [PATCH v1 0/4] Add Alder Lake PCH-S support to PMC core driver

[Kammela, Gayatri]

> -----Original Message-----
> From: You-Sheng Yang <vicamo.yang@canonical.com>
> Sent: Monday, July 5, 2021 3:59 AM
> To: Kammela, Gayatri <gayatri.kammela@intel.com>; platform-driver-
> x86@vger.kernel.org
> Cc: mgross@linux.intel.com; hdegoede@redhat.com;
> irenic.rajneesh@gmail.com; Pandruvada, Srinivas
> <srinivas.pandruvada@intel.com>; Andy Shevchenko
> <andriy.shevchenko@linux.intel.com>; Box, David E
> <david.e.box@intel.com>
> Subject: Re: [PATCH v1 0/4] Add Alder Lake PCH-S support to PMC core driver
> 
> Hi, this works for me.
> 
> Tested-By: You-Sheng Yang <vicamo.yang@canonical.com>
Thank you!
> 
> On 7/2/21 10:19 AM, Gayatri Kammela wrote:
> > Hi,
> > The patch series add Alder Lake PCH-S support to PMC core driver.
> >
> > Patch 1: Add Alderlake support to pmc_core driver Patch 2: Add Latency
> > Tolerance Reporting (LTR) support to Alder Lake Patch 3: Add Alder
> > Lake low power mode support for pmc_core Patch 4: Add GBE Package C10
> > fix for Alder Lake
> >
> > David E. Box (1):
> >   platform/x86: intel_pmc_core: Add GBE Package C10 fix for Alder Lake
> >     PCH
> >
> > Gayatri Kammela (3):
> >   platform/x86: intel_pmc_core: Add Alderlake support to pmc_core driver
> >   platform/x86: intel_pmc_core: Add Latency Tolerance Reporting (LTR)
> >     support to Alder Lake
> >   platform/x86: intel_pmc_core: Add Alder Lake low power mode support
> >     for pmc_core
> >
> >  drivers/platform/x86/intel_pmc_core.c | 307
> > +++++++++++++++++++++++++-  drivers/platform/x86/intel_pmc_core.h |
> > 17 ++
> >  2 files changed, 321 insertions(+), 3 deletions(-)
> >
> > Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
> > Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Cc: David Box <david.e.box@intel.com>
> >
> > base-commit: 62fb9874f5da54fdb243003b386128037319b219
> >

RE: [PATCH v1 0/4] Add Alder Lake PCH-S support to PMC core driver

[Kammela, Gayatri]

> -----Original Message-----
> From: Hans de Goede <hdegoede@redhat.com>
> Sent: Tuesday, July 6, 2021 4:11 AM
> To: Kammela, Gayatri <gayatri.kammela@intel.com>; platform-driver-
> x86@vger.kernel.org
> Cc: mgross@linux.intel.com; irenic.rajneesh@gmail.com; Pandruvada,
> Srinivas <srinivas.pandruvada@intel.com>; Andy Shevchenko
> <andriy.shevchenko@linux.intel.com>; Box, David E
> <david.e.box@intel.com>
> Subject: Re: [PATCH v1 0/4] Add Alder Lake PCH-S support to PMC core driver
> 
> Hi,
> 
> On 7/2/21 4:19 AM, Gayatri Kammela wrote:
> > Hi,
> > The patch series add Alder Lake PCH-S support to PMC core driver.
> >
> > Patch 1: Add Alderlake support to pmc_core driver Patch 2: Add Latency
> > Tolerance Reporting (LTR) support to Alder Lake Patch 3: Add Alder
> > Lake low power mode support for pmc_core Patch 4: Add GBE Package C10
> > fix for Alder Lake
> >
> > David E. Box (1):
> >   platform/x86: intel_pmc_core: Add GBE Package C10 fix for Alder Lake
> >     PCH
> >
> > Gayatri Kammela (3):
> >   platform/x86: intel_pmc_core: Add Alderlake support to pmc_core driver
> >   platform/x86: intel_pmc_core: Add Latency Tolerance Reporting (LTR)
> >     support to Alder Lake
> >   platform/x86: intel_pmc_core: Add Alder Lake low power mode support
> >     for pmc_core
> >
> >  drivers/platform/x86/intel_pmc_core.c | 307
> > +++++++++++++++++++++++++-  drivers/platform/x86/intel_pmc_core.h |
> > 17 ++
> >  2 files changed, 321 insertions(+), 3 deletions(-)
> >
> > Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
> > Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Cc: David Box <david.e.box@intel.com>
> >
> > base-commit: 62fb9874f5da54fdb243003b386128037319b219
> 
> Thanks, the series looks good to me:
> 
> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
> 
> For the series. As Andy already mentioned we are trying to move all the Intel
> files to drivers/platform/x86/intel. Can you please send a new version with
> an extra patch which first moves all the
> 
> drivers/platform/x86/intel_pmc_*.c files to: drivers/platform/x86/intel/pmc
> and then apply the 4 patches from this series on top, see:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?i
> d=72fbcac2f40e690e1a5584358750e546a2678c2c
> 
> For an example of a commit moving files to under
> drivers/platform/x86/intel/<subdir>
> 
> Regards,
> 
> Hans

Thanks Hans! Sure, I will send the new version.