* [PATCH v2 1/2] platform/x86/amd: pmc: Get STB DRAM size from PMFW
@ 2023-04-12 10:21 Shyam Sundar S K
2023-04-12 10:21 ` [PATCH v2 2/2] platform/x86/amd: pmc: update metrics table info for Pink Sardine Shyam Sundar S K
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Shyam Sundar S K @ 2023-04-12 10:21 UTC (permalink / raw)
To: hdegoede, markgross
Cc: Sanket.Goswami, mario.limonciello, platform-driver-x86, Shyam Sundar S K
Recent PMFW's have support for querying the STB DRAM size. Add this
support to the driver.
Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
---
v2:
- Based on review-hans branch
- Add a switch for cpu-id check based on feedback from Mario.
drivers/platform/x86/amd/pmc.c | 32 +++++++++++++++++++++++++++++++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/platform/x86/amd/pmc.c b/drivers/platform/x86/amd/pmc.c
index 877b629e5cae..9f8bc6711413 100644
--- a/drivers/platform/x86/amd/pmc.c
+++ b/drivers/platform/x86/amd/pmc.c
@@ -114,6 +114,7 @@ enum s2d_arg {
S2D_PHYS_ADDR_LOW,
S2D_PHYS_ADDR_HIGH,
S2D_NUM_SAMPLES,
+ S2D_DRAM_SIZE,
};
struct amd_pmc_bit_map {
@@ -146,6 +147,7 @@ struct amd_pmc_dev {
u32 base_addr;
u32 cpu_id;
u32 active_ips;
+ u32 dram_size;
/* SMU version information */
u8 smu_program;
u8 major;
@@ -888,11 +890,34 @@ static const struct pci_device_id pmc_pci_ids[] = {
{ }
};
+static int amd_pmc_get_dram_size(struct amd_pmc_dev *dev)
+{
+ switch (dev->cpu_id) {
+ case AMD_CPU_ID_YC:
+ if (!(dev->major > 90 || (dev->major == 90 && dev->minor > 39)))
+ goto err_dram_size;
+ break;
+ default:
+ goto err_dram_size;
+ }
+
+ amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, STB_SPILL_TO_DRAM, 1);
+ if (!dev->dram_size)
+ goto err_dram_size;
+
+ return 0;
+
+err_dram_size:
+ dev_err(dev->dev, "DRAM size command not supported for this platform\n");
+ return -EINVAL;
+}
+
static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
{
u32 phys_addr_low, phys_addr_hi;
u64 stb_phys_addr;
u32 size = 0;
+ int ret;
/* Spill to DRAM feature uses separate SMU message port */
dev->msg_port = 1;
@@ -901,6 +926,11 @@ static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
if (size != S2D_TELEMETRY_BYTES_MAX)
return -EIO;
+ /* Get DRAM size */
+ ret = amd_pmc_get_dram_size(dev);
+ if (ret)
+ dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX;
+
/* Get STB DRAM address */
amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
@@ -910,7 +940,7 @@ static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
/* Clear msg_port for other SMU operation */
dev->msg_port = 0;
- dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
+ dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, dev->dram_size);
if (!dev->stb_virt_addr)
return -ENOMEM;
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] platform/x86/amd: pmc: update metrics table info for Pink Sardine
2023-04-12 10:21 [PATCH v2 1/2] platform/x86/amd: pmc: Get STB DRAM size from PMFW Shyam Sundar S K
@ 2023-04-12 10:21 ` Shyam Sundar S K
2023-04-12 11:03 ` Ilpo Järvinen
2023-04-12 10:46 ` [PATCH v2 1/2] platform/x86/amd: pmc: Get STB DRAM size from PMFW Ilpo Järvinen
2023-04-17 9:31 ` Hans de Goede
2 siblings, 1 reply; 5+ messages in thread
From: Shyam Sundar S K @ 2023-04-12 10:21 UTC (permalink / raw)
To: hdegoede, markgross
Cc: Sanket.Goswami, mario.limonciello, platform-driver-x86, Shyam Sundar S K
Starting from Pink Sardine, number of IP blocks were added to the SoC
and the PMFW has the ability to give debug stats on each the IP blocks
after a S0ix cycle within part of the SMU metrics table. Add this new
capability to the driver.
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
---
v2:
- Based on review-hans branch
- No code change
drivers/platform/x86/amd/pmc.c | 56 ++++++++++++++++++++++++++--------
1 file changed, 43 insertions(+), 13 deletions(-)
diff --git a/drivers/platform/x86/amd/pmc.c b/drivers/platform/x86/amd/pmc.c
index 9f8bc6711413..bb7597ca334f 100644
--- a/drivers/platform/x86/amd/pmc.c
+++ b/drivers/platform/x86/amd/pmc.c
@@ -45,7 +45,6 @@
#define AMD_PMC_STB_DUMMY_PC 0xC6000007
/* STB S2D(Spill to DRAM) has different message port offset */
-#define STB_SPILL_TO_DRAM 0xBE
#define AMD_S2D_REGISTER_MESSAGE 0xA20
#define AMD_S2D_REGISTER_RESPONSE 0xA80
#define AMD_S2D_REGISTER_ARGUMENT 0xA88
@@ -98,7 +97,6 @@
#define PMC_MSG_DELAY_MIN_US 50
#define RESPONSE_REGISTER_LOOP_MAX 20000
-#define SOC_SUBSYSTEM_IP_MAX 12
#define DELAY_MIN_US 2000
#define DELAY_MAX_US 3000
#define FIFO_SIZE 4096
@@ -132,9 +130,18 @@ static const struct amd_pmc_bit_map soc15_ip_blk[] = {
{"ISP", BIT(6)},
{"NBIO", BIT(7)},
{"DF", BIT(8)},
- {"USB0", BIT(9)},
- {"USB1", BIT(10)},
+ {"USB3_0", BIT(9)},
+ {"USB3_1", BIT(10)},
{"LAPIC", BIT(11)},
+ {"USB3_2", BIT(12)},
+ {"USB3_3", BIT(13)},
+ {"USB3_4", BIT(14)},
+ {"USB4_0", BIT(15)},
+ {"USB4_1", BIT(16)},
+ {"MPM", BIT(17)},
+ {"JPEG", BIT(18)},
+ {"IPU", BIT(19)},
+ {"UMSCH", BIT(20)},
{}
};
@@ -148,6 +155,8 @@ struct amd_pmc_dev {
u32 cpu_id;
u32 active_ips;
u32 dram_size;
+ u32 num_ips;
+ u32 s2d_msg_id;
/* SMU version information */
u8 smu_program;
u8 major;
@@ -195,8 +204,8 @@ struct smu_metrics {
u64 timein_s0i3_totaltime;
u64 timein_swdrips_lastcapture;
u64 timein_swdrips_totaltime;
- u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
- u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
+ u64 timecondition_notmet_lastcapture[32];
+ u64 timecondition_notmet_totaltime[32];
} __packed;
static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
@@ -262,7 +271,7 @@ static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
dev->msg_port = 1;
/* Get the num_samples to calculate the last push location */
- ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, STB_SPILL_TO_DRAM, 1);
+ ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, dev->s2d_msg_id, 1);
/* Clear msg_port for other SMU operation */
dev->msg_port = 0;
if (ret) {
@@ -308,6 +317,23 @@ static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
.release = amd_pmc_stb_debugfs_release_v2,
};
+static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
+{
+ switch (dev->cpu_id) {
+ case AMD_CPU_ID_PCO:
+ case AMD_CPU_ID_RN:
+ case AMD_CPU_ID_YC:
+ case AMD_CPU_ID_CB:
+ dev->num_ips = 12;
+ dev->s2d_msg_id = 0xBE;
+ break;
+ case AMD_CPU_ID_PS:
+ dev->num_ips = 21;
+ dev->s2d_msg_id = 0x85;
+ break;
+ }
+}
+
static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
{
if (dev->cpu_id == AMD_CPU_ID_PCO) {
@@ -470,7 +496,7 @@ static int smu_fw_info_show(struct seq_file *s, void *unused)
table.timeto_resume_to_os_lastcapture);
seq_puts(s, "\n=== Active time (in us) ===\n");
- for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
+ for (idx = 0 ; idx < dev->num_ips ; idx++) {
if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
table.timecondition_notmet_lastcapture[idx]);
@@ -901,7 +927,7 @@ static int amd_pmc_get_dram_size(struct amd_pmc_dev *dev)
goto err_dram_size;
}
- amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, STB_SPILL_TO_DRAM, 1);
+ amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, dev->s2d_msg_id, 1);
if (!dev->dram_size)
goto err_dram_size;
@@ -922,7 +948,10 @@ static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
/* Spill to DRAM feature uses separate SMU message port */
dev->msg_port = 1;
- amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
+ /* Get num of IP blocks within the SoC */
+ amd_pmc_get_ip_info(dev);
+
+ amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, dev->s2d_msg_id, 1);
if (size != S2D_TELEMETRY_BYTES_MAX)
return -EIO;
@@ -932,8 +961,8 @@ static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX;
/* Get STB DRAM address */
- amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
- amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
+ amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, dev->s2d_msg_id, 1);
+ amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, dev->s2d_msg_id, 1);
stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
@@ -1022,7 +1051,8 @@ static int amd_pmc_probe(struct platform_device *pdev)
mutex_init(&dev->lock);
- if (enable_stb && (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB)) {
+ if (enable_stb && (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB ||
+ dev->cpu_id == AMD_CPU_ID_PS)) {
err = amd_pmc_s2d_init(dev);
if (err)
goto err_pci_dev_put;
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] platform/x86/amd: pmc: Get STB DRAM size from PMFW
2023-04-12 10:21 [PATCH v2 1/2] platform/x86/amd: pmc: Get STB DRAM size from PMFW Shyam Sundar S K
2023-04-12 10:21 ` [PATCH v2 2/2] platform/x86/amd: pmc: update metrics table info for Pink Sardine Shyam Sundar S K
@ 2023-04-12 10:46 ` Ilpo Järvinen
2023-04-17 9:31 ` Hans de Goede
2 siblings, 0 replies; 5+ messages in thread
From: Ilpo Järvinen @ 2023-04-12 10:46 UTC (permalink / raw)
To: Shyam Sundar S K
Cc: hdegoede, markgross, Sanket.Goswami, mario.limonciello,
platform-driver-x86
On Wed, 12 Apr 2023, Shyam Sundar S K wrote:
> Recent PMFW's have support for querying the STB DRAM size. Add this
> support to the driver.
>
> Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com>
> Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
> ---
> v2:
> - Based on review-hans branch
> - Add a switch for cpu-id check based on feedback from Mario.
>
> drivers/platform/x86/amd/pmc.c | 32 +++++++++++++++++++++++++++++++-
> 1 file changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/platform/x86/amd/pmc.c b/drivers/platform/x86/amd/pmc.c
> index 877b629e5cae..9f8bc6711413 100644
> --- a/drivers/platform/x86/amd/pmc.c
> +++ b/drivers/platform/x86/amd/pmc.c
> @@ -114,6 +114,7 @@ enum s2d_arg {
> S2D_PHYS_ADDR_LOW,
> S2D_PHYS_ADDR_HIGH,
> S2D_NUM_SAMPLES,
> + S2D_DRAM_SIZE,
> };
>
> struct amd_pmc_bit_map {
> @@ -146,6 +147,7 @@ struct amd_pmc_dev {
> u32 base_addr;
> u32 cpu_id;
> u32 active_ips;
> + u32 dram_size;
> /* SMU version information */
> u8 smu_program;
> u8 major;
> @@ -888,11 +890,34 @@ static const struct pci_device_id pmc_pci_ids[] = {
> { }
> };
>
> +static int amd_pmc_get_dram_size(struct amd_pmc_dev *dev)
> +{
> + switch (dev->cpu_id) {
> + case AMD_CPU_ID_YC:
> + if (!(dev->major > 90 || (dev->major == 90 && dev->minor > 39)))
> + goto err_dram_size;
> + break;
> + default:
> + goto err_dram_size;
> + }
> +
> + amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, STB_SPILL_TO_DRAM, 1);
Passing true to bool argument, not 1.
> + if (!dev->dram_size)
> + goto err_dram_size;
Don't overwrite the error code from amd_pmc_send_cmd() with -EINVAL on
the error path but pass the same errorcode on.
It might warrant splitting the error path such that the amd_pmc_send_cmd()
errors do not print the error in this function but only return the error
code (amd_pmc_send_cmd() already has dev_err() for each of the error
return cases). That only leaves what to do on non-error return and zero
dram_size, is that expected to happen?
--
i.
> +
> + return 0;
> +
> +err_dram_size:
> + dev_err(dev->dev, "DRAM size command not supported for this platform\n");
> + return -EINVAL;
> +}
> +
> static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
> {
> u32 phys_addr_low, phys_addr_hi;
> u64 stb_phys_addr;
> u32 size = 0;
> + int ret;
>
> /* Spill to DRAM feature uses separate SMU message port */
> dev->msg_port = 1;
> @@ -901,6 +926,11 @@ static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
> if (size != S2D_TELEMETRY_BYTES_MAX)
> return -EIO;
>
> + /* Get DRAM size */
> + ret = amd_pmc_get_dram_size(dev);
> + if (ret)
> + dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX;
> +
> /* Get STB DRAM address */
> amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
> amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
> @@ -910,7 +940,7 @@ static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
> /* Clear msg_port for other SMU operation */
> dev->msg_port = 0;
>
> - dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
> + dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, dev->dram_size);
> if (!dev->stb_virt_addr)
> return -ENOMEM;
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] platform/x86/amd: pmc: update metrics table info for Pink Sardine
2023-04-12 10:21 ` [PATCH v2 2/2] platform/x86/amd: pmc: update metrics table info for Pink Sardine Shyam Sundar S K
@ 2023-04-12 11:03 ` Ilpo Järvinen
0 siblings, 0 replies; 5+ messages in thread
From: Ilpo Järvinen @ 2023-04-12 11:03 UTC (permalink / raw)
To: Shyam Sundar S K
Cc: hdegoede, markgross, Sanket.Goswami, mario.limonciello,
platform-driver-x86
On Wed, 12 Apr 2023, Shyam Sundar S K wrote:
> Starting from Pink Sardine, number of IP blocks were added to the SoC
> and the PMFW has the ability to give debug stats on each the IP blocks
> after a S0ix cycle within part of the SMU metrics table. Add this new
> capability to the driver.
>
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
> ---
> v2:
> - Based on review-hans branch
> - No code change
>
> drivers/platform/x86/amd/pmc.c | 56 ++++++++++++++++++++++++++--------
> 1 file changed, 43 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/platform/x86/amd/pmc.c b/drivers/platform/x86/amd/pmc.c
> index 9f8bc6711413..bb7597ca334f 100644
> --- a/drivers/platform/x86/amd/pmc.c
> +++ b/drivers/platform/x86/amd/pmc.c
> @@ -45,7 +45,6 @@
> #define AMD_PMC_STB_DUMMY_PC 0xC6000007
>
> /* STB S2D(Spill to DRAM) has different message port offset */
> -#define STB_SPILL_TO_DRAM 0xBE
> #define AMD_S2D_REGISTER_MESSAGE 0xA20
> #define AMD_S2D_REGISTER_RESPONSE 0xA80
> #define AMD_S2D_REGISTER_ARGUMENT 0xA88
> @@ -98,7 +97,6 @@
> #define PMC_MSG_DELAY_MIN_US 50
> #define RESPONSE_REGISTER_LOOP_MAX 20000
>
> -#define SOC_SUBSYSTEM_IP_MAX 12
> #define DELAY_MIN_US 2000
> #define DELAY_MAX_US 3000
> #define FIFO_SIZE 4096
> @@ -132,9 +130,18 @@ static const struct amd_pmc_bit_map soc15_ip_blk[] = {
> {"ISP", BIT(6)},
> {"NBIO", BIT(7)},
> {"DF", BIT(8)},
> - {"USB0", BIT(9)},
> - {"USB1", BIT(10)},
> + {"USB3_0", BIT(9)},
> + {"USB3_1", BIT(10)},
> {"LAPIC", BIT(11)},
> + {"USB3_2", BIT(12)},
> + {"USB3_3", BIT(13)},
> + {"USB3_4", BIT(14)},
> + {"USB4_0", BIT(15)},
> + {"USB4_1", BIT(16)},
> + {"MPM", BIT(17)},
> + {"JPEG", BIT(18)},
> + {"IPU", BIT(19)},
> + {"UMSCH", BIT(20)},
> {}
> };
>
> @@ -148,6 +155,8 @@ struct amd_pmc_dev {
> u32 cpu_id;
> u32 active_ips;
> u32 dram_size;
> + u32 num_ips;
> + u32 s2d_msg_id;
> /* SMU version information */
> u8 smu_program;
> u8 major;
> @@ -195,8 +204,8 @@ struct smu_metrics {
> u64 timein_s0i3_totaltime;
> u64 timein_swdrips_lastcapture;
> u64 timein_swdrips_totaltime;
> - u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
> - u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
> + u64 timecondition_notmet_lastcapture[32];
> + u64 timecondition_notmet_totaltime[32];
> } __packed;
>
> static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
> @@ -262,7 +271,7 @@ static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
> dev->msg_port = 1;
>
> /* Get the num_samples to calculate the last push location */
> - ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, STB_SPILL_TO_DRAM, 1);
> + ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, dev->s2d_msg_id, 1);
> /* Clear msg_port for other SMU operation */
> dev->msg_port = 0;
> if (ret) {
> @@ -308,6 +317,23 @@ static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
> .release = amd_pmc_stb_debugfs_release_v2,
> };
>
> +static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
> +{
> + switch (dev->cpu_id) {
> + case AMD_CPU_ID_PCO:
> + case AMD_CPU_ID_RN:
> + case AMD_CPU_ID_YC:
> + case AMD_CPU_ID_CB:
> + dev->num_ips = 12;
> + dev->s2d_msg_id = 0xBE;
> + break;
> + case AMD_CPU_ID_PS:
> + dev->num_ips = 21;
> + dev->s2d_msg_id = 0x85;
> + break;
> + }
> +}
> +
> static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
> {
> if (dev->cpu_id == AMD_CPU_ID_PCO) {
> @@ -470,7 +496,7 @@ static int smu_fw_info_show(struct seq_file *s, void *unused)
> table.timeto_resume_to_os_lastcapture);
>
> seq_puts(s, "\n=== Active time (in us) ===\n");
> - for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
> + for (idx = 0 ; idx < dev->num_ips ; idx++) {
> if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
> seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
> table.timecondition_notmet_lastcapture[idx]);
> @@ -901,7 +927,7 @@ static int amd_pmc_get_dram_size(struct amd_pmc_dev *dev)
> goto err_dram_size;
> }
>
> - amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, STB_SPILL_TO_DRAM, 1);
> + amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, dev->s2d_msg_id, 1);
> if (!dev->dram_size)
> goto err_dram_size;
>
> @@ -922,7 +948,10 @@ static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
> /* Spill to DRAM feature uses separate SMU message port */
> dev->msg_port = 1;
>
> - amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
> + /* Get num of IP blocks within the SoC */
> + amd_pmc_get_ip_info(dev);
> +
> + amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, dev->s2d_msg_id, 1);
> if (size != S2D_TELEMETRY_BYTES_MAX)
> return -EIO;
>
> @@ -932,8 +961,8 @@ static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
> dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX;
>
> /* Get STB DRAM address */
> - amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
> - amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
> + amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, dev->s2d_msg_id, 1);
> + amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, dev->s2d_msg_id, 1);
>
> stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
>
> @@ -1022,7 +1051,8 @@ static int amd_pmc_probe(struct platform_device *pdev)
>
> mutex_init(&dev->lock);
>
> - if (enable_stb && (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB)) {
> + if (enable_stb && (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB ||
> + dev->cpu_id == AMD_CPU_ID_PS)) {
These same cpu_id checks are now done in two place. Create a helper for
it.
Curiously enough, the other place already had _PS added there, was this
place perhaps missed when 035c8a91a11f ("platform/x86/amd/pmc: Add new
platform support") was done? The debugfs will use incorrect
STB_SPILL_TO_DRAM for _PS in amd_pmc_stb_debugfs_open_v2() before this
change?
> err = amd_pmc_s2d_init(dev);
> if (err)
> goto err_pci_dev_put;
>
--
i.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] platform/x86/amd: pmc: Get STB DRAM size from PMFW
2023-04-12 10:21 [PATCH v2 1/2] platform/x86/amd: pmc: Get STB DRAM size from PMFW Shyam Sundar S K
2023-04-12 10:21 ` [PATCH v2 2/2] platform/x86/amd: pmc: update metrics table info for Pink Sardine Shyam Sundar S K
2023-04-12 10:46 ` [PATCH v2 1/2] platform/x86/amd: pmc: Get STB DRAM size from PMFW Ilpo Järvinen
@ 2023-04-17 9:31 ` Hans de Goede
2 siblings, 0 replies; 5+ messages in thread
From: Hans de Goede @ 2023-04-17 9:31 UTC (permalink / raw)
To: Shyam Sundar S K, markgross
Cc: Sanket.Goswami, mario.limonciello, platform-driver-x86
Hi Shyam,
On 4/12/23 12:21, Shyam Sundar S K wrote:
> Recent PMFW's have support for querying the STB DRAM size. Add this
> support to the driver.
>
> Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com>
> Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Please prepare a new version of this series addressing
Ilpo's review remarks.
Regards,
Hans
> ---
> v2:
> - Based on review-hans branch
> - Add a switch for cpu-id check based on feedback from Mario.
>
> drivers/platform/x86/amd/pmc.c | 32 +++++++++++++++++++++++++++++++-
> 1 file changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/platform/x86/amd/pmc.c b/drivers/platform/x86/amd/pmc.c
> index 877b629e5cae..9f8bc6711413 100644
> --- a/drivers/platform/x86/amd/pmc.c
> +++ b/drivers/platform/x86/amd/pmc.c
> @@ -114,6 +114,7 @@ enum s2d_arg {
> S2D_PHYS_ADDR_LOW,
> S2D_PHYS_ADDR_HIGH,
> S2D_NUM_SAMPLES,
> + S2D_DRAM_SIZE,
> };
>
> struct amd_pmc_bit_map {
> @@ -146,6 +147,7 @@ struct amd_pmc_dev {
> u32 base_addr;
> u32 cpu_id;
> u32 active_ips;
> + u32 dram_size;
> /* SMU version information */
> u8 smu_program;
> u8 major;
> @@ -888,11 +890,34 @@ static const struct pci_device_id pmc_pci_ids[] = {
> { }
> };
>
> +static int amd_pmc_get_dram_size(struct amd_pmc_dev *dev)
> +{
> + switch (dev->cpu_id) {
> + case AMD_CPU_ID_YC:
> + if (!(dev->major > 90 || (dev->major == 90 && dev->minor > 39)))
> + goto err_dram_size;
> + break;
> + default:
> + goto err_dram_size;
> + }
> +
> + amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, STB_SPILL_TO_DRAM, 1);
> + if (!dev->dram_size)
> + goto err_dram_size;
> +
> + return 0;
> +
> +err_dram_size:
> + dev_err(dev->dev, "DRAM size command not supported for this platform\n");
> + return -EINVAL;
> +}
> +
> static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
> {
> u32 phys_addr_low, phys_addr_hi;
> u64 stb_phys_addr;
> u32 size = 0;
> + int ret;
>
> /* Spill to DRAM feature uses separate SMU message port */
> dev->msg_port = 1;
> @@ -901,6 +926,11 @@ static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
> if (size != S2D_TELEMETRY_BYTES_MAX)
> return -EIO;
>
> + /* Get DRAM size */
> + ret = amd_pmc_get_dram_size(dev);
> + if (ret)
> + dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX;
> +
> /* Get STB DRAM address */
> amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
> amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
> @@ -910,7 +940,7 @@ static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
> /* Clear msg_port for other SMU operation */
> dev->msg_port = 0;
>
> - dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
> + dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, dev->dram_size);
> if (!dev->stb_virt_addr)
> return -ENOMEM;
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-04-17 9:34 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-12 10:21 [PATCH v2 1/2] platform/x86/amd: pmc: Get STB DRAM size from PMFW Shyam Sundar S K
2023-04-12 10:21 ` [PATCH v2 2/2] platform/x86/amd: pmc: update metrics table info for Pink Sardine Shyam Sundar S K
2023-04-12 11:03 ` Ilpo Järvinen
2023-04-12 10:46 ` [PATCH v2 1/2] platform/x86/amd: pmc: Get STB DRAM size from PMFW Ilpo Järvinen
2023-04-17 9:31 ` Hans de Goede
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