From: Richard Henderson <richard.henderson@linaro.org>
To: Stefan Brankovic <stefan.brankovic@rt-rk.com>, qemu-devel@nongnu.org
Cc: david@gibson.dropbear.id.au
Subject: Re: [Qemu-devel] [PATCH 1/8] target/ppc: Optimize emulation of lvsl and lvsr instructions
Date: Wed, 26 Jun 2019 17:28:28 +0200 [thread overview]
Message-ID: <10c6ff6c-22c3-eb18-3c22-f9e48e236b97@linaro.org> (raw)
In-Reply-To: <1560942225-24728-2-git-send-email-stefan.brankovic@rt-rk.com>
On 6/19/19 1:03 PM, Stefan Brankovic wrote:
> Adding simple macro that is calling tcg implementation of appropriate
> instruction if altivec support is active.
>
> Optimization of altivec instruction lvsl (Load Vector for Shift Left).
> Place bytes sh:sh+15 of value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F
> in destination register. Sh is calculated by adding 2 source registers and
> getting bits 60-63 of result.
>
> First, the bits [28-31] are placed from EA to variable sh. After that,
> the bytes are created in the following way:
> sh:(sh+7) of X(from description) by multiplying sh with 0x0101010101010101
> followed by addition of the result with 0x0001020304050607. Value obtained
> is placed in higher doubleword element of vD.
> (sh+8):(sh+15) by adding the result of previous multiplication with
> 0x08090a0b0c0d0e0f. Value obtained is placed in lower doubleword element
> of vD.
>
> Optimization of altivec instruction lvsr (Load Vector for Shift Right).
> Place bytes 16-sh:31-sh of value 0x00 || 0x01 || 0x02 || ... || 0x1E ||
> 0x1F in destination register. Sh is calculated by adding 2 source
> registers and getting bits 60-63 of result.
>
> First, the bits [28-31] are placed from EA to variable sh. After that,
> the bytes are created in the following way:
> sh:(sh+7) of X(from description) by multiplying sh with 0x0101010101010101
> followed by substraction of the result from 0x1011121314151617. Value
> obtained is placed in higher doubleword element of vD.
> (sh+8):(sh+15) by substracting the result of previous multiplication from
> 0x18191a1b1c1d1e1f. Value obtained is placed in lower doubleword element
> of vD.
>
> Signed-off-by: Stefan Brankovic <stefan.brankovic@rt-rk.com>
> ---
> target/ppc/helper.h | 2 -
> target/ppc/int_helper.c | 18 ------
> target/ppc/translate/vmx-impl.inc.c | 120 ++++++++++++++++++++++++++----------
> 3 files changed, 88 insertions(+), 52 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2019-06-26 18:38 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-19 11:03 [Qemu-devel] [PATCH 0/8] target/ppc: Optimize emulation of some Altivec instructions Stefan Brankovic
2019-06-19 11:03 ` [Qemu-devel] [PATCH 1/8] target/ppc: Optimize emulation of lvsl and lvsr instructions Stefan Brankovic
2019-06-26 15:28 ` Richard Henderson [this message]
2019-06-26 15:48 ` Richard Henderson
2019-06-19 11:03 ` [Qemu-devel] [PATCH 2/8] target/ppc: Optimize emulation of vsl and vsr instructions Stefan Brankovic
2019-06-26 15:34 ` Richard Henderson
2019-06-19 11:03 ` [Qemu-devel] [PATCH 3/8] target/ppc: Optimize emulation of vpkpx instruction Stefan Brankovic
2019-06-19 11:03 ` [Qemu-devel] [PATCH 4/8] target/ppc: Optimize emulation of vgbbd instruction Stefan Brankovic
2019-06-26 15:37 ` Richard Henderson
2019-06-19 11:03 ` [Qemu-devel] [PATCH 5/8] target/ppc: Optimize emulation of vclzd instruction Stefan Brankovic
2019-06-19 11:03 ` [Qemu-devel] [PATCH 6/8] target/ppc: Optimize emulation of vclzw instruction Stefan Brankovic
2019-06-26 15:38 ` Richard Henderson
2019-06-19 11:03 ` [Qemu-devel] [PATCH 7/8] target/ppc: Optimize emulation of vclzh and vclzb instructions Stefan Brankovic
2019-06-19 11:03 ` [Qemu-devel] [PATCH 8/8] target/ppc: Refactor emulation of vmrgew and vmrgow instructions Stefan Brankovic
2019-06-19 11:47 ` [Qemu-devel] [PATCH 0/8] target/ppc: Optimize emulation of some Altivec instructions no-reply
-- strict thread matches above, loose matches on Subject: below --
2019-06-06 10:15 [Qemu-devel] [PATCH 0/8] Optimize emulation of ten Altivec instructions: lvsl, Stefan Brankovic
2019-06-06 10:15 ` [Qemu-devel] [PATCH 1/8] target/ppc: Optimize emulation of lvsl and lvsr instructions Stefan Brankovic
2019-06-06 16:46 ` Richard Henderson
2019-06-17 11:31 ` Stefan Brankovic
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