Re: [Qemu-devel] [PATCH 2/8] target/ppc: Optimize emulation of vsl and vsr instructions

[Richard Henderson <richard.henderson@linaro.org>]

On 6/19/19 1:03 PM, Stefan Brankovic wrote:
> Optimization of altivec instructions vsl and vsr(Vector Shift Left/Rigt).
> Perform shift operation (left and right respectively) on 128 bit value of
> register vA by value specified in bits 125-127 of register vB. Lowest 3
> bits in each byte element of register vB must be identical or result is
> undefined.
> 
> For vsl instruction, the first step is bits 125-127 of register vB have
> to be saved in variable sh. Then, the highest sh bits of the lower
> doubleword element of register vA are saved in variable shifted,
> in order not to lose those bits when shift operation is performed on
> the lower doubleword element of register vA, which is the next
> step. After shifting the lower doubleword element shift operation
> is performed on higher doubleword element of vA, with replacement of
> the lowest sh bits(that are now 0) with bits saved in shifted.
> 
> For vsr instruction, firstly, the bits 125-127 of register vB have
> to be saved in variable sh. Then, the lowest sh bits of the higher
> doubleword element of register vA are saved in variable shifted,
> in odred not to lose those bits when the shift operation is
> performed on the higher doubleword element of register vA, which is
> the next step. After shifting higher doubleword element, shift operation
> is performed on lower doubleword element of vA, with replacement of
> highest sh bits(that are now 0) with bits saved in shifted.
> 
> Signed-off-by: Stefan Brankovic <stefan.brankovic@rt-rk.com>
> ---
>  target/ppc/helper.h                 |  2 -
>  target/ppc/int_helper.c             | 35 -------------
>  target/ppc/translate/vmx-impl.inc.c | 99 ++++++++++++++++++++++++++++++++++++-
>  3 files changed, 97 insertions(+), 39 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


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