From: Peter Maydell <peter.maydell@linaro.org>
To: Anthony Liguori <aliguori@amazon.com>
Cc: Blue Swirl <blauwirbel@gmail.com>,
qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PULL 03/29] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD
Date: Sat, 8 Feb 2014 15:57:38 +0000 [thread overview]
Message-ID: <1391875084-12772-4-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1391875084-12772-1-git-send-email-peter.maydell@linaro.org>
Implement the pairwise integer operations in the 3-reg-same SIMD group:
ADDP, SMAXP, SMINP, UMAXP and UMINP.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-arm/translate-a64.c | 124 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 123 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 8d996e9..01f6b79 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -6580,7 +6580,129 @@ static void gen_min_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
/* Pairwise op subgroup of C3.6.16. */
static void disas_simd_3same_pair(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
+ int is_q = extract32(insn, 30, 1);
+ int u = extract32(insn, 29, 1);
+ int size = extract32(insn, 22, 2);
+ int opcode = extract32(insn, 11, 5);
+ int rm = extract32(insn, 16, 5);
+ int rn = extract32(insn, 5, 5);
+ int rd = extract32(insn, 0, 5);
+ int pass;
+
+ if (size == 3 && !is_q) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ switch (opcode) {
+ case 0x14: /* SMAXP, UMAXP */
+ case 0x15: /* SMINP, UMINP */
+ if (size == 3) {
+ unallocated_encoding(s);
+ return;
+ }
+ break;
+ case 0x17:
+ if (u) {
+ unallocated_encoding(s);
+ return;
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ /* These operations work on the concatenated rm:rn, with each pair of
+ * adjacent elements being operated on to produce an element in the result.
+ */
+ if (size == 3) {
+ TCGv_i64 tcg_res[2];
+
+ for (pass = 0; pass < 2; pass++) {
+ TCGv_i64 tcg_op1 = tcg_temp_new_i64();
+ TCGv_i64 tcg_op2 = tcg_temp_new_i64();
+ int passreg = (pass == 0) ? rn : rm;
+
+ read_vec_element(s, tcg_op1, passreg, 0, MO_64);
+ read_vec_element(s, tcg_op2, passreg, 1, MO_64);
+ tcg_res[pass] = tcg_temp_new_i64();
+
+ /* The only 64 bit pairwise integer op is ADDP */
+ assert(opcode == 0x17);
+ tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);
+
+ tcg_temp_free_i64(tcg_op1);
+ tcg_temp_free_i64(tcg_op2);
+ }
+
+ for (pass = 0; pass < 2; pass++) {
+ write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
+ tcg_temp_free_i64(tcg_res[pass]);
+ }
+ } else {
+ int maxpass = is_q ? 4 : 2;
+ TCGv_i32 tcg_res[4];
+
+ for (pass = 0; pass < maxpass; pass++) {
+ TCGv_i32 tcg_op1 = tcg_temp_new_i32();
+ TCGv_i32 tcg_op2 = tcg_temp_new_i32();
+ NeonGenTwoOpFn *genfn;
+ int passreg = pass < (maxpass / 2) ? rn : rm;
+ int passelt = (is_q && (pass & 1)) ? 2 : 0;
+
+ read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32);
+ read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32);
+ tcg_res[pass] = tcg_temp_new_i32();
+
+ switch (opcode) {
+ case 0x17: /* ADDP */
+ {
+ static NeonGenTwoOpFn * const fns[3] = {
+ gen_helper_neon_padd_u8,
+ gen_helper_neon_padd_u16,
+ tcg_gen_add_i32,
+ };
+ genfn = fns[size];
+ break;
+ }
+ case 0x14: /* SMAXP, UMAXP */
+ {
+ static NeonGenTwoOpFn * const fns[3][2] = {
+ { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 },
+ { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 },
+ { gen_max_s32, gen_max_u32 },
+ };
+ genfn = fns[size][u];
+ break;
+ }
+ case 0x15: /* SMINP, UMINP */
+ {
+ static NeonGenTwoOpFn * const fns[3][2] = {
+ { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 },
+ { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 },
+ { gen_min_s32, gen_min_u32 },
+ };
+ genfn = fns[size][u];
+ break;
+ }
+ default:
+ g_assert_not_reached();
+ }
+
+ genfn(tcg_res[pass], tcg_op1, tcg_op2);
+
+ tcg_temp_free_i32(tcg_op1);
+ tcg_temp_free_i32(tcg_op2);
+ }
+
+ for (pass = 0; pass < maxpass; pass++) {
+ write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);
+ tcg_temp_free_i32(tcg_res[pass]);
+ }
+ if (!is_q) {
+ clear_vec_high(s, rd);
+ }
+ }
}
/* Floating point op subgroup of C3.6.16. */
--
1.8.5
next prev parent reply other threads:[~2014-02-08 15:58 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-08 15:57 [Qemu-devel] [PULL 00/29] target-arm queue Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 01/29] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 02/29] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns Peter Maydell
2014-02-08 15:57 ` Peter Maydell [this message]
2014-02-08 15:57 ` [Qemu-devel] [PULL 04/29] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 05/29] target-arm: A64: Implement scalar pairwise ops Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 06/29] target-arm: A64: Implement remaining integer scalar-3-same insns Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 07/29] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 08/29] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 09/29] target-arm: A64: Implement 2-register misc compares, ABS, NEG Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 10/29] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 11/29] target-arm: A64: Add narrowing 2-reg-misc instructions Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 12/29] target-arm: A64: Add 2-reg-misc REV* instructions Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 13/29] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 14/29] target-arm: Add support for AArch32 64bit VCVTB and VCVTT Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 15/29] arm_gic: Fix GIC pending behavior Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 16/29] arm_gic: Keep track of SGI sources Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 17/29] arm_gic: Support setting/getting binary point reg Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 18/29] vmstate: Add uint32 2D-array support Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 19/29] arm_gic: Add GICC_APRn state to the GICState Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 20/29] rules.mak: Support .cc as a C++ source file suffix Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 21/29] rules.mak: Link with C++ if we have a C++ compiler Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 22/29] disas: Add subset of libvixl sources for A64 disassembler Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 23/29] disas/libvixl: Fix upstream libvixl compilation issues Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 24/29] disas: Implement disassembly output for A64 Peter Maydell
2014-02-08 15:58 ` [Qemu-devel] [PULL 25/29] util/fifo8: implement push/pop of multiple bytes Peter Maydell
2014-02-08 15:58 ` [Qemu-devel] [PULL 26/29] util/fifo8: clear fifo head upon reset Peter Maydell
2014-02-08 15:58 ` [Qemu-devel] [PULL 27/29] hw/net: add support for Allwinner EMAC Fast Ethernet controller Peter Maydell
2014-02-08 15:58 ` [Qemu-devel] [PULL 28/29] hw/arm/allwinner-a10: initialize EMAC Peter Maydell
2014-02-08 15:58 ` [Qemu-devel] [PULL 29/29] arm/zynq: Add software system reset via SCLR Peter Maydell
2014-02-11 11:59 ` [Qemu-devel] [PULL 00/29] target-arm queue Peter Maydell
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