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From: Peter Maydell <peter.maydell@linaro.org>
To: Anthony Liguori <aliguori@amazon.com>
Cc: Blue Swirl <blauwirbel@gmail.com>,
	qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PULL 05/29] target-arm: A64: Implement scalar pairwise ops
Date: Sat,  8 Feb 2014 15:57:40 +0000	[thread overview]
Message-ID: <1391875084-12772-6-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1391875084-12772-1-git-send-email-peter.maydell@linaro.org>

Implement the instructions in the scalar pairwise group (C3.6.8).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
 target-arm/translate-a64.c | 114 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 113 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 01f6b79..452b1fb 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -5501,7 +5501,119 @@ static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
  */
 static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
 {
-    unsupported_encoding(s, insn);
+    int u = extract32(insn, 29, 1);
+    int size = extract32(insn, 22, 2);
+    int opcode = extract32(insn, 12, 5);
+    int rn = extract32(insn, 5, 5);
+    int rd = extract32(insn, 0, 5);
+    TCGv_ptr fpst;
+
+    /* For some ops (the FP ones), size[1] is part of the encoding.
+     * For ADDP strictly it is not but size[1] is always 1 for valid
+     * encodings.
+     */
+    opcode |= (extract32(size, 1, 1) << 5);
+
+    switch (opcode) {
+    case 0x3b: /* ADDP */
+        if (u || size != 3) {
+            unallocated_encoding(s);
+            return;
+        }
+        TCGV_UNUSED_PTR(fpst);
+        break;
+    case 0xc: /* FMAXNMP */
+    case 0xd: /* FADDP */
+    case 0xf: /* FMAXP */
+    case 0x2c: /* FMINNMP */
+    case 0x2f: /* FMINP */
+        /* FP op, size[0] is 32 or 64 bit */
+        if (!u) {
+            unallocated_encoding(s);
+            return;
+        }
+        size = extract32(size, 0, 1) ? 3 : 2;
+        fpst = get_fpstatus_ptr();
+        break;
+    default:
+        unallocated_encoding(s);
+        return;
+    }
+
+    if (size == 3) {
+        TCGv_i64 tcg_op1 = tcg_temp_new_i64();
+        TCGv_i64 tcg_op2 = tcg_temp_new_i64();
+        TCGv_i64 tcg_res = tcg_temp_new_i64();
+
+        read_vec_element(s, tcg_op1, rn, 0, MO_64);
+        read_vec_element(s, tcg_op2, rn, 1, MO_64);
+
+        switch (opcode) {
+        case 0x3b: /* ADDP */
+            tcg_gen_add_i64(tcg_res, tcg_op1, tcg_op2);
+            break;
+        case 0xc: /* FMAXNMP */
+            gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0xd: /* FADDP */
+            gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0xf: /* FMAXP */
+            gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x2c: /* FMINNMP */
+            gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x2f: /* FMINP */
+            gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        default:
+            g_assert_not_reached();
+        }
+
+        write_fp_dreg(s, rd, tcg_res);
+
+        tcg_temp_free_i64(tcg_op1);
+        tcg_temp_free_i64(tcg_op2);
+        tcg_temp_free_i64(tcg_res);
+    } else {
+        TCGv_i32 tcg_op1 = tcg_temp_new_i32();
+        TCGv_i32 tcg_op2 = tcg_temp_new_i32();
+        TCGv_i32 tcg_res = tcg_temp_new_i32();
+
+        read_vec_element_i32(s, tcg_op1, rn, 0, MO_32);
+        read_vec_element_i32(s, tcg_op2, rn, 1, MO_32);
+
+        switch (opcode) {
+        case 0xc: /* FMAXNMP */
+            gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0xd: /* FADDP */
+            gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0xf: /* FMAXP */
+            gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x2c: /* FMINNMP */
+            gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        case 0x2f: /* FMINP */
+            gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
+            break;
+        default:
+            g_assert_not_reached();
+        }
+
+        write_fp_sreg(s, rd, tcg_res);
+
+        tcg_temp_free_i32(tcg_op1);
+        tcg_temp_free_i32(tcg_op2);
+        tcg_temp_free_i32(tcg_res);
+    }
+
+    if (!TCGV_IS_UNUSED_PTR(fpst)) {
+        tcg_temp_free_ptr(fpst);
+    }
 }
 
 /*
-- 
1.8.5

  parent reply	other threads:[~2014-02-08 15:58 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-02-08 15:57 [Qemu-devel] [PULL 00/29] target-arm queue Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 01/29] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 02/29] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 03/29] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 04/29] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR Peter Maydell
2014-02-08 15:57 ` Peter Maydell [this message]
2014-02-08 15:57 ` [Qemu-devel] [PULL 06/29] target-arm: A64: Implement remaining integer scalar-3-same insns Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 07/29] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 08/29] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 09/29] target-arm: A64: Implement 2-register misc compares, ABS, NEG Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 10/29] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 11/29] target-arm: A64: Add narrowing 2-reg-misc instructions Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 12/29] target-arm: A64: Add 2-reg-misc REV* instructions Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 13/29] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 14/29] target-arm: Add support for AArch32 64bit VCVTB and VCVTT Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 15/29] arm_gic: Fix GIC pending behavior Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 16/29] arm_gic: Keep track of SGI sources Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 17/29] arm_gic: Support setting/getting binary point reg Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 18/29] vmstate: Add uint32 2D-array support Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 19/29] arm_gic: Add GICC_APRn state to the GICState Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 20/29] rules.mak: Support .cc as a C++ source file suffix Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 21/29] rules.mak: Link with C++ if we have a C++ compiler Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 22/29] disas: Add subset of libvixl sources for A64 disassembler Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 23/29] disas/libvixl: Fix upstream libvixl compilation issues Peter Maydell
2014-02-08 15:57 ` [Qemu-devel] [PULL 24/29] disas: Implement disassembly output for A64 Peter Maydell
2014-02-08 15:58 ` [Qemu-devel] [PULL 25/29] util/fifo8: implement push/pop of multiple bytes Peter Maydell
2014-02-08 15:58 ` [Qemu-devel] [PULL 26/29] util/fifo8: clear fifo head upon reset Peter Maydell
2014-02-08 15:58 ` [Qemu-devel] [PULL 27/29] hw/net: add support for Allwinner EMAC Fast Ethernet controller Peter Maydell
2014-02-08 15:58 ` [Qemu-devel] [PULL 28/29] hw/arm/allwinner-a10: initialize EMAC Peter Maydell
2014-02-08 15:58 ` [Qemu-devel] [PULL 29/29] arm/zynq: Add software system reset via SCLR Peter Maydell
2014-02-11 11:59 ` [Qemu-devel] [PULL 00/29] target-arm queue Peter Maydell

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