From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-devel] [PATCH v6 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines
Date: Tue, 27 Aug 2019 07:58:22 -0700 [thread overview]
Message-ID: <1566917919-25381-14-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1566917919-25381-1-git-send-email-bmeng.cn@gmail.com>
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/hw/riscv/sifive_cpu.h | 31 +++++++++++++++++++++++++++++++
include/hw/riscv/sifive_e.h | 7 +------
include/hw/riscv/sifive_u.h | 7 +------
3 files changed, 33 insertions(+), 12 deletions(-)
create mode 100644 include/hw/riscv/sifive_cpu.h
diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h
new file mode 100644
index 0000000..1367996
--- /dev/null
+++ b/include/hw/riscv/sifive_cpu.h
@@ -0,0 +1,31 @@
+/*
+ * SiFive CPU types
+ *
+ * Copyright (c) 2017 SiFive, Inc.
+ * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_SIFIVE_CPU_H
+#define HW_SIFIVE_CPU_H
+
+#if defined(TARGET_RISCV32)
+#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
+#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
+#elif defined(TARGET_RISCV64)
+#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
+#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
+#endif
+
+#endif /* HW_SIFIVE_CPU_H */
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index d175b24..e17cdfd 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -19,6 +19,7 @@
#ifndef HW_SIFIVE_E_H
#define HW_SIFIVE_E_H
+#include "hw/riscv/sifive_cpu.h"
#include "hw/riscv/sifive_gpio.h"
#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
@@ -83,10 +84,4 @@ enum {
#define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000
#define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000
-#if defined(TARGET_RISCV32)
-#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
-#elif defined(TARGET_RISCV64)
-#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
-#endif
-
#endif
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 892f0ee..4abc621 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -20,6 +20,7 @@
#define HW_SIFIVE_U_H
#include "hw/net/cadence_gem.h"
+#include "hw/riscv/sifive_cpu.h"
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
#define RISCV_U_SOC(obj) \
@@ -77,10 +78,4 @@ enum {
#define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000
#define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
-#if defined(TARGET_RISCV32)
-#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
-#elif defined(TARGET_RISCV64)
-#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
-#endif
-
#endif
--
2.7.4
next prev parent reply other threads:[~2019-08-27 15:17 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-27 14:58 [Qemu-devel] [PATCH v6 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 01/30] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 03/30] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 04/30] riscv: hw: Change create_fdt() to return void Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 07/30] riscv: roms: Remove executable attribute of opensbi images Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 08/30] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 11/30] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 12/30] riscv: sifive_e: Drop sifive_mmio_emulate() Bin Meng
2019-08-27 14:58 ` Bin Meng [this message]
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 14/30] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng
2019-08-30 21:18 ` Alistair Francis
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 16/30] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 18/30] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 19/30] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 21/30] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 23/30] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 24/30] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 25/30] riscv: roms: Update default bios for sifive_u machine Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 27/30] riscv: sifive_u: Instantiate OTP memory with a serial number Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 28/30] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 30/30] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng
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