From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-devel] [PATCH v6 18/30] riscv: sifive_u: Update PLIC hart topology configuration string
Date: Tue, 27 Aug 2019 07:58:27 -0700 [thread overview]
Message-ID: <1566917919-25381-19-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1566917919-25381-1-git-send-email-bmeng.cn@gmail.com>
With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.
Suggested-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7f51d9d..24ae3d1 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -424,10 +424,11 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
plic_hart_config = g_malloc0(plic_hart_config_len);
for (i = 0; i < ms->smp.cpus; i++) {
if (i != 0) {
- strncat(plic_hart_config, ",", plic_hart_config_len);
+ strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
+ plic_hart_config_len);
+ } else {
+ strncat(plic_hart_config, "M", plic_hart_config_len);
}
- strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG,
- plic_hart_config_len);
plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
}
--
2.7.4
next prev parent reply other threads:[~2019-08-27 15:13 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-27 14:58 [Qemu-devel] [PATCH v6 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 01/30] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 03/30] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 04/30] riscv: hw: Change create_fdt() to return void Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 07/30] riscv: roms: Remove executable attribute of opensbi images Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 08/30] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 11/30] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 12/30] riscv: sifive_e: Drop sifive_mmio_emulate() Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 14/30] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng
2019-08-30 21:18 ` Alistair Francis
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 16/30] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-08-27 14:58 ` Bin Meng [this message]
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 19/30] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 21/30] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 23/30] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 24/30] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 25/30] riscv: roms: Update default bios for sifive_u machine Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 27/30] riscv: sifive_u: Instantiate OTP memory with a serial number Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 28/30] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng
2019-08-27 14:58 ` [Qemu-devel] [PATCH v6 30/30] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng
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