From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-devel] [PATCH v8 14/32] riscv: sifive_e: Drop sifive_mmio_emulate()
Date: Fri, 6 Sep 2019 09:20:01 -0700 [thread overview]
Message-ID: <1567786819-22142-15-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1567786819-22142-1-git-send-email-bmeng.cn@gmail.com>
Use create_unimplemented_device() instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v8:
- select UNIMP in sifive_e Kconfig due to applied commit
"hw/misc: Add a config switch for the "unimplemented" device"
in latest qemu/master
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- drop patch "riscv: sifive: Move sifive_mmio_emulate() to a common place"
- new patch "riscv: sifive_e: Drop sifive_mmio_emulate()"
hw/riscv/Kconfig | 1 +
hw/riscv/sifive_e.c | 23 ++++++++---------------
2 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 8674211..33e54b0 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -12,6 +12,7 @@ config SIFIVE_E
bool
select HART
select SIFIVE
+ select UNIMP
config SIFIVE_U
bool
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 1428a99..0f9d641 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -36,6 +36,7 @@
#include "hw/loader.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
+#include "hw/misc/unimp.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
@@ -74,14 +75,6 @@ static const struct MemmapEntry {
[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
};
-static void sifive_mmio_emulate(MemoryRegion *parent, const char *name,
- uintptr_t offset, uintptr_t length)
-{
- MemoryRegion *mock_mmio = g_new(MemoryRegion, 1);
- memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal);
- memory_region_add_subregion(parent, offset, mock_mmio);
-}
-
static void riscv_sifive_e_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_e_memmap;
@@ -172,7 +165,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
+ create_unimplemented_device("riscv.sifive.e.aon",
memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
@@ -199,19 +192,19 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0",
+ create_unimplemented_device("riscv.sifive.e.qspi0",
memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0",
+ create_unimplemented_device("riscv.sifive.e.pwm0",
memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1",
+ create_unimplemented_device("riscv.sifive.e.qspi1",
memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1",
+ create_unimplemented_device("riscv.sifive.e.pwm1",
memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2",
+ create_unimplemented_device("riscv.sifive.e.qspi2",
memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2",
+ create_unimplemented_device("riscv.sifive.e.pwm2",
memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
/* Flash memory */
--
2.7.4
next prev parent reply other threads:[~2019-09-06 16:30 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-06 16:19 [Qemu-devel] [PATCH v8 00/32] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 01/32] riscv: hw: Remove duplicated "hw/hw.h" inclusion Bin Meng
2019-09-06 21:20 ` Alistair Francis
2019-09-09 16:20 ` Palmer Dabbelt
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 02/32] riscv: sifive_test: Add reset functionality Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 03/32] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 04/32] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 05/32] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 06/32] riscv: hw: Change create_fdt() to return void Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 07/32] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 08/32] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 09/32] riscv: roms: Remove executable attribute of opensbi images Bin Meng
2019-09-06 16:25 ` Philippe Mathieu-Daudé
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 10/32] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 11/32] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 12/32] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 13/32] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-09-06 16:20 ` Bin Meng [this message]
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 15/32] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 16/32] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 17/32] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-09-13 14:33 ` Palmer Dabbelt
2019-09-13 15:25 ` Bin Meng
2019-09-14 19:00 ` Palmer Dabbelt
2019-09-15 13:07 ` Bin Meng
2019-09-15 17:31 ` Palmer Dabbelt
2019-09-15 17:39 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-09-15 22:16 ` Palmer Dabbelt
2019-09-16 7:51 ` Bin Meng
2019-09-16 17:02 ` [Qemu-devel] " Alistair Francis
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 19/32] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 20/32] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 21/32] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-09-09 16:20 ` Palmer Dabbelt
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 23/32] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 24/32] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 25/32] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 26/32] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 27/32] riscv: roms: Update default bios for sifive_u machine Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 28/32] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 29/32] riscv: sifive_u: Instantiate OTP memory with a serial number Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 30/32] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 31/32] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 32/32] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng
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