From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-devel] [PATCH v8 05/32] riscv: hw: Remove not needed PLIC properties in device tree
Date: Fri, 6 Sep 2019 09:19:52 -0700 [thread overview]
Message-ID: <1567786819-22142-6-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1567786819-22142-1-git-send-email-bmeng.cn@gmail.com>
This removes "reg-names" and "riscv,max-priority" properties of the
PLIC node from device tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jonathan Behrens <fintelia@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- keep the PLIC compatible string unchanged as OpenSBI uses that
for DT fix up
hw/riscv/sifive_u.c | 2 --
hw/riscv/virt.c | 2 --
2 files changed, 4 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 762223c..e8acdd9 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -180,8 +180,6 @@ static void *create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_PLIC].base,
0x0, memmap[SIFIVE_U_PLIC].size);
- qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
- qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6852178..090512b 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -244,8 +244,6 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[VIRT_PLIC].base,
0x0, memmap[VIRT_PLIC].size);
- qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
- qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
--
2.7.4
next prev parent reply other threads:[~2019-09-06 16:24 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-06 16:19 [Qemu-devel] [PATCH v8 00/32] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 01/32] riscv: hw: Remove duplicated "hw/hw.h" inclusion Bin Meng
2019-09-06 21:20 ` Alistair Francis
2019-09-09 16:20 ` Palmer Dabbelt
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 02/32] riscv: sifive_test: Add reset functionality Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 03/32] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 04/32] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-09-06 16:19 ` Bin Meng [this message]
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 06/32] riscv: hw: Change create_fdt() to return void Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 07/32] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 08/32] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 09/32] riscv: roms: Remove executable attribute of opensbi images Bin Meng
2019-09-06 16:25 ` Philippe Mathieu-Daudé
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 10/32] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 11/32] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-09-06 16:19 ` [Qemu-devel] [PATCH v8 12/32] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 13/32] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 14/32] riscv: sifive_e: Drop sifive_mmio_emulate() Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 15/32] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 16/32] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 17/32] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-09-13 14:33 ` Palmer Dabbelt
2019-09-13 15:25 ` Bin Meng
2019-09-14 19:00 ` Palmer Dabbelt
2019-09-15 13:07 ` Bin Meng
2019-09-15 17:31 ` Palmer Dabbelt
2019-09-15 17:39 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-09-15 22:16 ` Palmer Dabbelt
2019-09-16 7:51 ` Bin Meng
2019-09-16 17:02 ` [Qemu-devel] " Alistair Francis
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 19/32] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 20/32] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 21/32] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-09-09 16:20 ` Palmer Dabbelt
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 23/32] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 24/32] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 25/32] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 26/32] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 27/32] riscv: roms: Update default bios for sifive_u machine Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 28/32] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 29/32] riscv: sifive_u: Instantiate OTP memory with a serial number Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 30/32] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 31/32] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng
2019-09-06 16:20 ` [Qemu-devel] [PATCH v8 32/32] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1567786819-22142-6-git-send-email-bmeng.cn@gmail.com \
--to=bmeng.cn@gmail.com \
--cc=Alistair.Francis@wdc.com \
--cc=palmer@sifive.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).